Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the following steps of: forming a first sacrificial structure penetrating through a laminated structure and a grid line gap penetrating through the laminated structure and extending along a first direction, wherein the first direction is vertical to a stacking direction of the laminated structure; removing the first sacrificial structure to form a storage hole; and forming a grid line gap structure and a storage structure in the grid line gap and the storage hole respectively.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the storage density requirements for semiconductor structures such as three-dimensional semiconductor memory devices are becoming increasingly higher. However, with the increase in the number of stacked layers in the semiconductor structure and the increase in the storage density per unit area, the process steps in the preparation of the three-dimensional semiconductor structure have become complicated and lengthy. Therefore, how to simplify the preparation process of the semiconductor structure while taking into account the reliability and overall performance of the semiconductor structure is one of the problems that need to be solved urgently. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method includes: forming a first sacrificial structure penetrating a stacked structure and a gate line gap penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; removing the first sacrificial structure to form a storage hole; and forming a gate line gap structure and a storage structure in the gate line gap and the storage hole, respectively.

[0005] In one embodiment, a first sacrificial structure penetrating a stacked structure and a gate line gap penetrating the stacked structure and extending along a first direction are formed, including: forming a plurality of first sacrificial structures and second sacrificial structures penetrating the stacked structure, wherein the first sacrificial structures and the second sacrificial structures are adjacently distributed along the second direction, a plurality of second sacrificial structures are arranged along the first direction, and the first direction, the second direction and the stacking direction are perpendicular to each other; removing the plurality of second sacrificial structures to form gate line holes; and engraving the gate line holes back to the gate line holes adjacent to the gate line holes along the first direction to form gate line gaps extending along the first direction.

[0006] In one embodiment, forming a plurality of first sacrificial structures and a second sacrificial structure penetrating a stacked structure includes: forming a plurality of first sacrificial holes and a second sacrificial hole penetrating the stacked structure; and filling the first sacrificial holes and the second sacrificial holes with sacrificial materials to form the first sacrificial structures and the second sacrificial structures.

[0007] In one embodiment, the method includes: alternately stacking first dielectric layers and first conductive layers to form a stacked structure.

[0008] In one embodiment, a gate line gap structure and a storage structure are formed in the gate line gap and the storage hole, respectively, including: forming a capacitor dielectric layer and an inner electrode layer in the gate line gap and the storage hole from the outside to the inside in sequence to form the gate line gap structure and the storage structure, respectively, wherein the capacitor dielectric layer and the inner electrode layer in the gate line gap structure extend along a first direction.

[0009] In one embodiment, a gate line gap structure and a storage structure are formed in the gate line gap and the storage hole, respectively, including: forming a first external electrode layer, a capacitor dielectric layer and an internal electrode layer in the gate line gap and the storage hole from the outside to the inside in sequence to form the gate line gap structure and the storage structure, respectively, wherein the first external electrode layer, the capacitor dielectric layer and the internal electrode layer in the gate line gap structure extend along a first direction.

[0010] In one embodiment, the method further includes: sequentially stacking a second dielectric layer and a second conductive layer on the surface of the stacked structure to form a top selection gate structure; and forming a transistor that passes through the top selection gate structure and extends to the storage structure along the stacking direction.

[0011] In one embodiment, a transistor is formed that passes through a top selection gate structure and extends to a storage structure along a stacking direction, including: forming an opening that passes through a top selection gate structure and extends to the storage structure along a stacking direction; and sequentially forming a dielectric layer and a channel layer from outside to inside in the opening, wherein the dielectric layer is in direct contact with the second conductive layer.

[0012] In one embodiment, a transistor is formed that passes through a top selection gate structure and extends to a storage structure along a stacking direction, including: forming an opening that passes through a top selection gate structure and extends to the storage structure along a stacking direction; and forming a second external electrode layer, a dielectric layer, and a channel layer in the opening in sequence from outside to inside.

[0013] In one embodiment, the method further includes: forming a plurality of bit lines extending along the first direction and connected to corresponding transistors; and forming a plurality of contact structures extending along the stacking direction to the second conductive layer.

[0014] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a storage structure that penetrates the stacked structure, wherein the stacked structure includes a first dielectric layer and a first conductive layer that are alternately stacked; and a gate line gap structure that penetrates the stacked structure and extends along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure, and the storage structure and the gate line gap structure include a capacitor dielectric layer and an inner electrode layer in sequence from the outside to the inside.

[0015] In one embodiment, the capacitor dielectric layer and the inner electrode layer in the gate line gap structure extend along a first direction, and the gate line gap structure divides the stacked structure into multiple storage blocks distributed along a second direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

[0016] In one embodiment, the first conductive layer is in direct contact with the capacitor dielectric layer.

[0017] In one embodiment, the storage structure and the gate line gap structure further include: a first outer electrode layer located outside the capacitor dielectric layer.

[0018] In one embodiment, the semiconductor structure also includes: a top selection gate structure located on the surface of the stacked structure, including a second dielectric layer and a second conductive layer stacked in sequence; a transistor passing through the top selection gate structure along the stacking direction and extending to the storage structure; a plurality of bit lines extending along the first direction and connected to the corresponding transistors; and a plurality of contact structures extending along the stacking direction to the second conductive layer.

[0019] In one embodiment, the material of the first conductive layer and the internal electrode layer includes at least one conductive material selected from the group consisting of polysilicon, titanium nitride, metal tungsten, metal platinum, and tantalum nitride.

[0020] In one embodiment, the material of the capacitor dielectric layer includes at least one of a ferroelectric material and an antiferroelectric material.

[0021] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory includes the semiconductor structure as described above; and a controller coupled to the semiconductor structure and used to control the three-dimensional memory to store data.

[0022] In one or more embodiments of the present application, by forming a gate line gap structure and a storage structure in the gate line gap and the storage hole respectively, the gate line gap structure and the storage structure can be simultaneously formed in one process step, which is beneficial to reducing process steps and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0024] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0025] Figures 2 to 7 is a process step diagram for forming a first sacrificial structure and a gate line gap according to an exemplary embodiment of the present application;

[0026] Figure 8 is a process step diagram for forming a storage hole according to an exemplary embodiment of the present application;

[0027] Fig. 9 and Fig.10is a process step diagram of forming a gate line gap structure and a storage structure according to an exemplary embodiment of the present application;

[0028] Fig.11 is a schematic side view of a structure in which a gate line gap structure and a storage structure are respectively formed in a gate line gap and a storage hole according to an exemplary embodiment of the present application;

[0029] Fig.12 is a side view structural schematic diagram of forming a gate line gap structure and a storage structure in a gate line gap and a storage hole respectively according to another exemplary embodiment of the present application;

[0030] Fig.13 is a process step diagram for forming a top selection gate structure, a transistor, a bit line and a contact structure according to an exemplary embodiment of the present application;

[0031] Fig.14 is a schematic side view of a transistor according to an exemplary embodiment of the present application;

[0032] Fig.15 is a schematic side view of a transistor according to another exemplary embodiment of the present application;

[0033] Fig.16 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0034] Fig.17A and Fig. 17B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0036] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first sacrificial structure discussed in this application may also be referred to as the second sacrificial structure, the first direction may also be referred to as the second direction, and vice versa.

[0037] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0038] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0039] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0040] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0042] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0043] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0044] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0046] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a first sacrificial structure penetrating a stacked structure and a gate line gap penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; S1200, removing the first sacrificial structure to form a storage hole; and S1300, forming a gate line gap structure and a storage structure in the gate line gap and the storage hole, respectively. Steps S1100 to S1300 will be described in detail below.

[0047] In the exemplary embodiment of the present application, Figure 7 As shown, a first sacrificial structure 1210 penetrating the stacked structure 1100 and a gate line gap 1310 penetrating the stacked structure 1100 and extending along a first direction Y may be formed, wherein the first direction Y is perpendicular to the stacking direction Z of the stacked structure 1100 .

[0048] For example, Figures 2 to 7 A process for forming a first sacrificial structure 1210 and a gate line gap 1310 provided in the present application is shown.

[0049] The first sacrificial structure 1210 penetrating the stacked structure 1100 and the gate line gap 1310 penetrating the stacked structure 1100 and extending along the first direction Y may include: forming a plurality of first sacrificial structures 1210 and second sacrificial structures 1410 penetrating the stacked structure 1100, wherein the first sacrificial structures 1210 and the second sacrificial structures 1410 are adjacently distributed along the second direction X, and the plurality of second sacrificial structures 1410 are arranged along the first direction Y, and the first direction Y, the second direction X, and the stacking direction Z are perpendicular to each other ( Figure 4 ); removing the plurality of second sacrificial structures 1410 to form a gate line hole 1420 ( Figure 6 ); and back-engraving the gate line hole 1420 to the gate line hole 1420 adjacent to the first direction Y to form a gate line gap 1310 extending along the first direction Y ( Figure 7 ).

[0050] Specifically, Figure 2 As shown, the first dielectric layer 1110 and the first conductive layer 1120 may be alternately stacked to form a stacked structure 1100. For example, the stacked structure 1100 may be formed by sequentially stacking the first dielectric layer 1110 and the first conductive layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0051] It should be understood that the number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 are not limited to Figure 2 With reference to the numbers and thicknesses shown in FIG, those skilled in the art may set any numbers and thicknesses of the first dielectric layer 1110 and the first conductive layer 1120 as needed without departing from the concept of the present application.

[0052] In addition, the materials of the first dielectric layer 1110 and the first conductive layer 1120 may be selected from suitable materials known in the art, for example, the material of the first dielectric layer 1110 may include an insulating material, and the material of the first conductive layer 1120 may include a conductive material. Exemplarily, the material of the first dielectric layer 1110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the first conductive layer 1120 may include at least one of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0053] Exemplarily, a stacked structure 1100 may be formed on a substrate 100. In an exemplary embodiment of the present application, the material of the substrate 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 100 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, or a multi-layer structure such as a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, a plurality of layers prepared from different materials may be sequentially arranged by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 100. In another exemplary embodiment of the present application, the material of the substrate 100 may include at least one of glass, plastic, sapphire wafer, or other non-conductive materials known in the art.

[0054] In the exemplary embodiment of the present application, Figure 3 As shown, a plurality of first sacrificial holes 1220 and second sacrificial holes 1430 may be formed to penetrate the stacked structure 1100. For example, the first sacrificial holes 1220 and the second sacrificial holes 1430 may be adjacently distributed along the second direction X, and the plurality of second sacrificial holes 1430 may be arranged along the first direction Y.

[0055] For example, the plurality of first sacrificial holes 1220 and the second sacrificial holes 1430 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The plurality of first sacrificial holes 1220 and the second sacrificial holes 1430 may have a cylindrical or columnar shape extending along the stacking direction Z in the stacked structure 1100.

[0056] In the present application, the first sacrificial hole 1220 and the second sacrificial hole 1430 may have substantially the same shape, and the plurality of first sacrificial holes 1220 and the second sacrificial holes 1430 may be evenly distributed in the laminated structure 1100, that is, the plurality of first sacrificial holes 1220 are discontinuous, and the plurality of second sacrificial holes 1430 are also discontinuous. This arrangement can reduce the stress concentration phenomenon in the laminated structure 1100 after the first sacrificial holes 1220 and the second sacrificial holes 1430 are formed, and further reduce the phenomenon of tilting or collapse of the laminated structure 1100.

[0057] The difference between the first sacrificial hole 1220 and the second sacrificial hole 1430 is that the first sacrificial hole 1220 can be used to determine the position of the storage hole formed subsequently, and the second sacrificial hole 1430 can be used to determine the position of the gate line hole 1420 formed subsequently. In other words, the first sacrificial hole 1220 can be the initial hole of the storage hole formed subsequently, and the second sacrificial hole 1430 can be the initial hole of the gate line hole 1420 formed subsequently.

[0058] For example, Figure 4 As shown, sacrificial materials may be filled in the first sacrificial hole 1220 and the second sacrificial hole 1430 to form the first sacrificial structure 1210 and the second sacrificial structure 1410. For example, sacrificial materials may be filled in the first sacrificial hole 1220 and the second sacrificial hole 1430 by a thin film deposition process to form the first sacrificial structure 1210 and the second sacrificial structure 1410, respectively. The sacrificial material may include, but is not limited to, any one or combination of carbon (such as amorphous carbon, graphite, etc.), carbon-containing organic matter, polymers, photoresist, etc.

[0059] For example, the first sacrificial structure 1210 and the second sacrificial structure 1410 may support the stacked structure 1100, thereby reducing the risk of collapse or bending of the stacked structure 1100. Figures 4 to 8 As shown, the second sacrificial structure 1410 and the first sacrificial structure 1210 may be removed in sequence subsequently.

[0060] For example, Figure 6 As shown, the plurality of second sacrificial structures 1410 may be removed to form a gate line hole 1420. In other words, the gate line hole 1420 is formed by removing the sacrificial material (i.e., the second sacrificial structure 1410) in the second sacrificial hole 1430. Therefore, the gate line hole 1420 may be approximately understood as the second sacrificial hole 1430. Since the plurality of first sacrificial holes 1220 are discontinuous, the plurality of gate line holes 1420 are also discontinuous.

[0061] For example, Figure 5 As shown, removing the plurality of second sacrificial structures 1410 may include: forming a patterned mask 200 on the surface of the stacked structure 1100, and removing the plurality of second sacrificial structures 1410 by one or more dry etching and / or wet etching processes using the patterned mask 200 as a mask, to form a gate line hole 1420 ( Figure 6 The patterned mask 200 may cover the first sacrificial structure 1210 and expose the second sacrificial structure 1410 , so as to reduce the risk of the first sacrificial structure 1210 being removed during the process of removing the second sacrificial structure 1410 .

[0062] For example, Figure 7 As shown, the gate line holes 1420 may be etched back until the adjacent gate line holes 1420 along the first direction Y are connected to form gate line gaps 1310 extending along the first direction Y. Exemplarily, after the gate line gaps 1310 are formed, the patterned mask 200 may be removed.

[0063] In the present application, in order to reduce the stress concentration phenomenon in the stacked structure 1100, a plurality of first sacrificial holes 1220 and second sacrificial holes 1430 may be provided to have substantially the same shape and be evenly distributed in the stacked structure 1100. In addition, in order to subsequently divide the stacked structure 1100 into a plurality of storage blocks, a gate line gap structure 1300 ( Fig. 9 or Fig.10 ). In the present application, by back-etching the gate line hole 1420 (which can be roughly understood as the second sacrificial hole 1430) to penetrate the adjacent gate line hole 1420 along the first direction Y, the formed gate line gap 1310 can be extended along the first direction Y, and then the gate line gap structure 1300 subsequently formed in the gate line gap 1310 can be extended along the first direction Y, so as to achieve the purpose of the gate line gap structure 1300 dividing the stacked structure 1100 into multiple storage blocks.

[0064] In the exemplary embodiment of the present application, Figure 8 As shown, the first sacrificial structure 1210 may be removed to form a storage hole 1230. For example, the first sacrificial structure 1210 may be removed by one or more dry etching and / or wet etching processes.

[0065] In the exemplary embodiment of the present application, Fig. 9 and Fig.10 As shown, the gate line gap structure 1300 and the storage structure 1200 may be formed in the gate line gap 1310 and the storage hole 1230, respectively. For example, the gate line gap structure 1300 and the storage structure 1200 may be formed in the gate line gap 1310 and the storage hole 1230, respectively, by a thin film deposition process. Fig.10 As shown, the formed gate line gap structure 1300 may extend along the first direction Y, so as to achieve the purpose of the gate line gap structure 1300 dividing the stacked structure 1100 into a plurality of memory blocks.

[0066] In an exemplary embodiment of the present application, Fig.11 As shown, the gate line gap structure 1300 and the storage structure 1200 may include a capacitor dielectric layer 210, an inner electrode layer 220 and a filling dielectric layer 230 in sequence from the outside to the inside.

[0067] Specifically, forming the gate line gap structure 1300 and the storage structure 1200 may include: sequentially forming a capacitor dielectric layer 210 and an inner electrode layer 220 from outside to inside in the gate line gap 1310 and the storage hole 1230 to form the gate line gap structure 1300 and the storage structure 1200, respectively, wherein the capacitor dielectric layer 210 and the inner electrode layer 220 in the gate line gap structure 1300 extend along the first direction Y. Exemplarily, after forming the capacitor dielectric layer 210 and the inner electrode layer 220, a filling dielectric layer 230 may be used to fill the gate line gap 1310 and the storage hole 1230 to electrically insulate the adjacent inner electrode layers 220 in the gate line gap 1310 and the storage hole 1230. The filling dielectric layer 230 may include an oxidizing dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps may be formed in the filling dielectric layer 230 by controlling the filling process to reduce structural stress.

[0068] The inner electrode layer 220 can be made of a conductive material, for example, and the conductive material can include one or more conductive materials such as polysilicon, TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and Pt (platinum).

[0069] The capacitor dielectric layer 210 of the storage structure 1200 may have a storage function. Specifically, the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 corresponding to each first conductive layer 1120 may form an independent storage unit with the first conductive layer 1120. The portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210 constitutes an external electrode of the storage unit.

[0070] The number of the first conductive layer 1120 is multiple layers, and the portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210, and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a memory cell. Each memory cell can be controlled by the first conductive layer 1120. Charges are stored or released in the capacitor dielectric layer 210 corresponding to the first conductive layer 1120 to realize the function of a single memory cell. Exemplarily, the first conductive layer 1120 can be used as a part of a conduction circuit for transmitting a signal to a memory cell.

[0071] The material of the capacitor dielectric layer 210 can include multiple materials. In the actual process, the material of the capacitor dielectric layer 210 can be reasonably selected according to specific needs so that the capacitor dielectric layer 210 has a storage effect. This application does not limit this. For example, the material of the capacitor dielectric layer 210 can be a ferroelectric material, an antiferroelectric material, etc.

[0072] Exemplarily, when the material of the capacitor dielectric layer 210 is a ferroelectric material, the portion of the first conductive layer 1120 surrounding the capacitor dielectric layer 210 and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a ferroelectric capacitor, that is, the above-mentioned storage unit.

[0073] Ferroelectric materials have nonlinear properties. The dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer containing the ferroelectric material is flipped is very large. This makes ferroelectric capacitors smaller in size than other capacitors, and the volume of capacitors used to store charge is smaller, which is conducive to achieving high-density storage.

[0074] The ferroelectric material may be one or more of ferroelectric materials such as zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2, or other materials doped with other elements based on the materials. Antiferroelectric materials have good stability and can effectively avoid wake-up effect, imprinting effect and polarization fatigue. Applying antiferroelectric materials to storage structures can have good data retention characteristics.

[0075] In another exemplary embodiment of the present application, Fig.12 As shown, the gate line gap structure 1300 and the storage structure 1200 may include a first outer electrode layer 240 , a capacitor dielectric layer 210 , an inner electrode layer 220 and a filling dielectric layer 230 in sequence from the outside to the inside.

[0076] Specifically, forming the gate line gap structure 1300 and the storage structure 1200 may include: forming a first outer electrode layer 240, a capacitor dielectric layer 210 and an inner electrode layer 220 in the gate line gap 1310 and the storage hole 1230 from the outside to the inside in order to form the gate line gap structure 1300 and the storage structure 1200 respectively, wherein the first outer electrode layer 240, the capacitor dielectric layer 210 and the inner electrode layer 220 in the gate line gap structure 1300 extend along the first direction Y. Exemplarily, after forming the first outer electrode layer 240, the capacitor dielectric layer 210 and the inner electrode layer 220, a filling dielectric layer 230 may be used to fill the gate line gap 1310 and the storage hole 1230. The filling dielectric layer 230 may include an oxidizing dielectric layer, such as silicon oxide, etc. Further, during the filling process, a plurality of insulating gaps may be formed in the filling dielectric layer 230 by controlling the filling process to reduce structural stress. At this time, the first outer electrode layer 240 , the capacitor dielectric layer 210 , and the portion of the inner electrode layer 220 of the memory structure 1200 corresponding to each first conductive layer 1120 may form an independent memory cell.

[0077] In the exemplary embodiment of the present application, Fig.13As shown, a second dielectric layer 2110 and a second conductive layer 2120 may be stacked in sequence on the surface of the stacked structure 1100 to form a top selection gate structure 2100 ; and a transistor 2200 is formed along a stacking direction Z passing through the top selection gate structure 2100 and extending to the storage structure 1200 .

[0078] Exemplarily, the second dielectric layer 2110 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second conductive layer 2120 may be made of a conductive material, which may include at least one of poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and the like.

[0079] In an exemplary embodiment of the present application, Fig.14 As shown, the transistor 2200 may include a dielectric layer 310 and a channel layer 320 in sequence from the outside to the inside.

[0080] Specifically, forming a transistor 2200 that passes through the top selection gate structure 2100 along the stacking direction Z and extends to the storage structure 1200 may include: forming an opening that passes through the top selection gate structure 2100 along the stacking direction Z and extends to the storage structure 1200; and forming a dielectric layer 310 and a channel layer 320 in the opening from the outside to the inside, wherein the dielectric layer 310 is in direct contact with the second conductive layer 2120.

[0081] Exemplarily, the material of the dielectric layer 310 may include one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide) and Si3N4 (silicon nitride). The material of the channel layer 320 may include one or more semiconductor materials such as silicon and polycrystalline silicon. Exemplarily, the dielectric layer 310 and the channel layer 320 may be sequentially formed by a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or any combination thereof.

[0082] Exemplarily, the dielectric layer 310 may be located between the second conductive layer 2120 and the channel layer 320. The channel layer 320 may be a cylindrical structure, and the channel layer 320 may extend along the stacking direction Z. The dielectric layer 310, the channel layer 320, and the portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form a transistor 2200. The portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form a gate of the transistor 2200. The channel layer 320 is in contact with the inner electrode layer 220 of the storage structure 1200, and the portion of the channel layer 320 in contact with the inner electrode layer 220 of the storage structure 1200 may form a source or a drain of the transistor.

[0083] Exemplarily, the source of the transistor 2200 is electrically connected to the inner electrode layer 220 of the storage structure 1200. For another example, the drain of the transistor 2200 is electrically connected to the inner electrode layer 220 of the storage structure 1200. It should be noted that the drain or source of the transistor 2200 can be determined according to the direction of current flow.

[0084] In another exemplary embodiment of the present application, Fig.15 As shown, the transistor 2200 may include a second outer electrode layer 330 , a dielectric layer 310 , and a channel layer 320 in sequence from the outside to the inside.

[0085] Specifically, forming the transistor 2200 that passes through the top selection gate structure 2100 and extends to the memory structure 1200 along the stacking direction Z includes: forming an opening that passes through the top selection gate structure 2100 and extends to the memory structure 1200 along the stacking direction Z; and sequentially forming the second outer electrode layer 330, the dielectric layer 310, and the channel layer 320 from the outside to the inside in the opening. Exemplarily, the material of the second outer electrode layer 330 may include any suitable conductive material. At this time, the second outer electrode layer 330 may form the gate of the transistor 2200.

[0086] In the exemplary embodiment of the present application, Fig.13 As shown, a plurality of bit lines 2300 extending along the first direction Y and connected to the corresponding transistors 2200 may be formed. Exemplarily, forming a plurality of bit lines 2300 extending along the first direction Y and connected to the corresponding transistors 2200 may include: forming a plurality of bit line contacts 2310 penetrating the second dielectric layer 2110 and the second conductive layer 2120 and extending to the transistors 2200; and forming the bit lines 2300 extending along the first direction Y and connected to the bit line contacts 2310.

[0087] Exemplarily, the materials of the bit line contact 2310 and the bit line 2300 may include a conductive material, such as a metal material. The metal material may be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and other conductive materials. Of course, the materials of the bit line contact 2310 and the bit line 2300 may be the same or different, and the present application does not limit this. When the materials of the bit line contact 2310 and the bit line 2300 are the same, the bit line contact 2310 and the bit line 2300 may be formed by the same process, which is conducive to simplifying the process flow of preparing the semiconductor structure and reducing the cost of preparing the semiconductor structure.

[0088] Exemplarily, the gate of transistor 2200 is electrically connected to the second conductive layer 2120, the second electrode of transistor 2200 can be electrically connected to the bit line 2300, the first ends of multiple memory cells (for example, the inner electrode layer 220 of the memory structure 1200) can be electrically connected to the first electrode of transistor 2200, and the second end of each memory cell (for example, the outer electrode of the memory structure 1200) can be electrically connected to the first conductive layer 1120.

[0089] The second conductive layer 2120 can be used to receive a word line control signal to turn on the transistor 2200, and the bit line 2300 can be used to receive a bit line control signal. When the transistor 2200 is turned on under the control of the word line control signal transmitted by the second conductive layer 2120, the bit line control signal received by the bit line 2300 can pass through the transistor 2200 to precharge the voltage of the inner electrode layer 220 of the storage structure 1200.

[0090] In the exemplary embodiment of the present application, Fig.13 As shown, multiple contact structures 2400 extending to the second conductive layer 2120 may be formed along the stacking direction Z. Electrical signals provided by the multiple contact structures 2400 may be transmitted to the second conductive layer 2120, and then electrical signal transmission between the top selection gate structure 2100 and other circuits may be realized through the contact structures 2400.

[0091] Fig.13 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0092] The semiconductor structure may include a storage structure 1200 and a gate line gap structure 1300 .

[0093] The storage structure 1200 may penetrate the stacked structure 1100, wherein the stacked structure 1100 includes alternately stacked first dielectric layers 1110 and first conductive layers 1120. The gate line gap structure 1300 may penetrate the stacked structure 1100 and extend along the first direction Y. The gate line gap structure 1300 may divide the stacked structure 1100 into a plurality of storage blocks distributed along the second direction X, wherein the first direction Y, the second direction X, and the stacking direction Z are perpendicular to each other.

[0094] It should be understood that the number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 are not limited to Fig.13 With reference to the numbers and thicknesses shown in FIG, those skilled in the art may set any numbers and thicknesses of the first dielectric layer 1110 and the first conductive layer 1120 as needed without departing from the concept of the present application.

[0095] In addition, the materials of the first dielectric layer 1110 and the first conductive layer 1120 may be selected from suitable materials known in the art, for example, the material of the first dielectric layer 1110 may include an insulating material, and the material of the first conductive layer 1120 may include a conductive material. Exemplarily, the material of the first dielectric layer 1110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the first conductive layer 1120 may include at least one of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0096] In an exemplary embodiment of the present application, the storage structure 1200 and the gate line gap structure 1300 may include a capacitor dielectric layer 210 and an inner electrode layer 220 in sequence from the outside to the inside ( Fig.11 In addition, the storage structure 1200 and the gate line gap structure 1300 may further include a filling dielectric layer 230 located inside the inner electrode layer 220 to electrically insulate the gate line gap 1310 from the adjacent inner electrode layer 220 in the storage hole 1230. The filling dielectric layer 230 may include an oxidized dielectric layer, such as silicon oxide.

[0097] For example, the capacitor dielectric layer 210 , the inner electrode layer 220 and the filling dielectric layer 230 in the gate line gap structure 1300 may extend along the first direction Y to divide the stacked structure 1100 into a plurality of memory blocks distributed along the second direction X.

[0098] The inner electrode layer 220 can be made of a conductive material, for example, and the conductive material can include one or more conductive materials such as polysilicon, TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and Pt (platinum).

[0099] Exemplarily, the first conductive layer 1120 may be in direct contact with the capacitor dielectric layer 210. The capacitor dielectric layer 210 of the storage structure 1200 may have a storage function. Specifically, the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 corresponding to each first conductive layer 1120 may form an independent storage unit with the first conductive layer 1120. The portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210 constitutes an external electrode of the storage unit.

[0100] The number of the first conductive layer 1120 is multiple layers, and the portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210, and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a memory cell. Each memory cell can be controlled by the first conductive layer 1120. Charges are stored or released in the capacitor dielectric layer 210 corresponding to the first conductive layer 1120 to realize the function of a single memory cell. Exemplarily, the first conductive layer 1120 can be used as a part of a conduction circuit for transmitting a signal to a memory cell.

[0101] The material of the capacitor dielectric layer 210 can include multiple materials. In the actual process, the material of the capacitor dielectric layer 210 can be reasonably selected according to specific needs so that the capacitor dielectric layer 210 has a storage effect. This application does not limit this. For example, the material of the capacitor dielectric layer 210 can be a ferroelectric material, an antiferroelectric material, etc.

[0102] Exemplarily, when the material of the capacitor dielectric layer 210 is a ferroelectric material, the portion of the first conductive layer 1120 surrounding the capacitor dielectric layer 210 and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a ferroelectric capacitor, that is, the above-mentioned storage unit.

[0103] Ferroelectric materials have nonlinear properties. The dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer containing the ferroelectric material is flipped is very large. This makes ferroelectric capacitors smaller in size than other capacitors, and the volume of capacitors used to store charge is smaller, which is conducive to achieving high-density storage.

[0104] The ferroelectric material may be one or more of ferroelectric materials such as zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2, or other materials doped with other elements based on the materials. Antiferroelectric materials have good stability and can effectively avoid wake-up effect, imprinting effect and polarization fatigue. Applying antiferroelectric materials to storage structures can have good data retention characteristics.

[0105] In another exemplary embodiment of the present application, the gate line gap structure 1300 and the storage structure 1200 may include a first outer electrode layer 240, a capacitor dielectric layer 210 and an inner electrode layer 220 in sequence from the outside to the inside ( Fig.12 ). In addition, the storage structure 1200 and the gate line gap structure 1300 may further include a filling dielectric layer 230 located inside the inner electrode layer 220 to electrically insulate the gate line gap 1310 from the adjacent inner electrode layer 220 in the storage hole 1230. The filling dielectric layer 230 may include an oxidizing dielectric layer, such as silicon oxide. At this time, the first outer electrode layer 240, the capacitor dielectric layer 210, and the inner electrode layer 220 of the storage structure 1200 corresponding to each first conductive layer 1120 may form an independent storage unit.

[0106] In the exemplary embodiment of the present application, Fig.13 As shown, the semiconductor structure may further include a top selection gate structure 2100. The top selection gate structure 2100 may be located on a surface of the stacked structure 1100. The top selection gate structure 2100 may include a second dielectric layer 2110 and a second conductive layer 2120 stacked in sequence.

[0107] Exemplarily, the second dielectric layer 2110 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second conductive layer 2120 may be made of a conductive material, which may include at least one of poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and the like.

[0108] In the exemplary embodiment of the present application, Fig.13 As shown, the semiconductor structure may further include a transistor 2200. The transistor 2200 may pass through the top selection gate structure 2100 along the stacking direction Z and extend to the memory structure 1200.

[0109] In an exemplary embodiment of the present application, the transistor 2200 may include a dielectric layer 310 and a channel layer 320 ( Fig.14 ).

[0110] Exemplarily, the material of the dielectric layer 310 may include one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide) and Si3N4 (silicon nitride). The material of the channel layer 320 may include one or more semiconductor materials such as silicon and polycrystalline silicon. Exemplarily, the dielectric layer 310 and the channel layer 320 may be sequentially formed by a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or any combination thereof.

[0111] Exemplarily, the dielectric layer 310 may be located between the second conductive layer 2120 and the channel layer 320. The channel layer 320 may be a cylindrical structure, and the channel layer 320 may extend along the stacking direction Z. The dielectric layer 310, the channel layer 320, and the portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form a transistor 2200. The portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form a gate of the transistor 2200. The channel layer 320 is in contact with the inner electrode layer 220 of the storage structure 1200, and the portion of the channel layer 320 in contact with the inner electrode layer 220 of the storage structure 1200 may form a source or a drain of the transistor.

[0112] Exemplarily, the source of the transistor 2200 is electrically connected to the inner electrode layer 220 of the storage structure 1200. For another example, the drain of the transistor 2200 is electrically connected to the inner electrode layer 220 of the storage structure 1200. It should be noted that the drain or source of the transistor 2200 can be determined according to the direction of current flow.

[0113] In another exemplary embodiment of the present application, the transistor 2200 may include, from the outside to the inside, a second outer electrode layer 330, a dielectric layer 310, and a channel layer 320 ( Fig.15 ). Exemplarily, the material of the second outer electrode layer 330 may include any suitable conductive material. In this case, the second outer electrode layer 330 may form the gate of the transistor 2200.

[0114] In the exemplary embodiment of the present application, Fig.13 As shown, the semiconductor structure may further include a plurality of bit lines 2300. The plurality of bit lines 2300 extend along the first direction Y and are connected to the corresponding transistors 2200. Exemplarily, the semiconductor structure may further include a plurality of bit line contacts 2310 penetrating the second dielectric layer 2110 and the second conductive layer 2120 and extending to the transistors 2200, wherein the bit lines 2300 may be connected to the corresponding transistors 2200 via the bit line contacts 2310.

[0115] Exemplarily, the materials of the bit line contact 2310 and the bit line 2300 may include a conductive material, such as a metal material. The metal material may be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc. Of course, the materials of the bit line contact 2310 and the bit line 2300 may be the same or different, and the present application does not limit this.

[0116] Exemplarily, the gate of transistor 2200 is electrically connected to the second conductive layer 2120, the second electrode of transistor 2200 can be electrically connected to the bit line 2300, the first ends of multiple memory cells (for example, the inner electrode layer 220 of the memory structure 1200) can be electrically connected to the first electrode of transistor 2200, and the second end of each memory cell (for example, the outer electrode of the memory structure 1200) can be electrically connected to the first conductive layer 1120.

[0117] The second conductive layer 2120 can be used to receive a word line control signal to turn on the transistor 2200, and the bit line 2300 can be used to receive a bit line control signal. When the transistor 2200 is turned on under the control of the word line control signal transmitted by the second conductive layer 2120, the bit line control signal received by the bit line 2300 can pass through the transistor 2200 to precharge the voltage of the inner electrode layer 220 of the storage structure 1200.

[0118] In the exemplary embodiment of the present application, Fig.13 As shown, the semiconductor structure may further include a plurality of contact structures 2400. The contact structures 2400 may extend to the second conductive layer 2120 along the stacking direction Z. The electrical signals provided by the plurality of contact structures 2400 may be transmitted to the second conductive layer 2120, and then the electrical signal transmission between the top selection gate structure 2100 and other circuits may be realized through the contact structures 2400.

[0119] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0120] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0121] Fig.16 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0122] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.16 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0123] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0124] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.17AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.16 The host 18 in the memory card connector 24 is coupled. Fig. 17B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.16 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0125] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Forming a first sacrificial structure penetrating the stacked structure and a gate line gap penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; removing the first sacrificial structure to form a storage hole; as well as A gate line gap structure and a storage structure are formed in the gate line gap and the storage hole respectively.

2. The method according to claim 1, characterized in that Forming a first sacrificial structure penetrating a stacked structure and a gate line gap penetrating the stacked structure and extending along a first direction, comprising: forming a plurality of the first sacrificial structures and the second sacrificial structures penetrating the stacked structure, wherein the first sacrificial structures and the second sacrificial structures are adjacently distributed along a second direction, a plurality of the second sacrificial structures are arranged along the first direction, and the first direction, the second direction and the stacking direction are perpendicular to each other; removing a plurality of the second sacrificial structures to form gate line holes; and The gate line holes are back-etched until the gate line holes adjacent to each other along the first direction pass through to form gate line gaps extending along the first direction.

3. The method according to claim 2, characterized in that Forming a plurality of the first sacrificial structures and the second sacrificial structures that penetrate the stacked structure comprises: forming a plurality of first sacrificial holes and second sacrificial holes penetrating the stacked structure; and Sacrificial materials are filled in the first sacrificial hole and the second sacrificial hole to form the first sacrificial structure and the second sacrificial structure.

4. The method according to claim 1, characterized in that The method comprises: The first dielectric layers and the first conductive layers are alternately stacked to form a stacked structure.

5. The method according to claim 1 or 2, characterized in that: A gate line gap structure and a storage structure are formed in the gate line gap and the storage hole respectively, including: A capacitor dielectric layer and an inner electrode layer are sequentially formed in the gate line gap and the storage hole from outside to inside to form the gate line gap structure and the storage structure respectively, wherein the capacitor dielectric layer and the inner electrode layer in the gate line gap structure extend along the first direction.

6. The method according to claim 1 or 2, characterized in that: A gate line gap structure and a storage structure are formed in the gate line gap and the storage hole respectively, including: A first outer electrode layer, a capacitor dielectric layer and an inner electrode layer are sequentially formed from the outside to the inside in the gate line gap and the storage hole to form the gate line gap structure and the storage structure respectively, wherein the first outer electrode layer, the capacitor dielectric layer and the inner electrode layer in the gate line gap structure extend along the first direction.

7. The method according to claim 1, characterized in that The method further comprises: stacking a second dielectric layer and a second conductive layer in sequence on the surface of the stacked structure to form a top selection gate structure; and A transistor is formed along the stacking direction through the top select gate structure and extending to the memory structure.

8. The method according to claim 7, characterized in that Forming a transistor extending through the top select gate structure and to the storage structure along the stacking direction, comprising: forming an opening through the top selection gate structure and extending to the memory structure along the stacking direction; and A dielectric layer and a channel layer are sequentially formed in the opening from outside to inside, wherein the dielectric layer is in direct contact with the second conductive layer.

9. The method according to claim 7, characterized in that: Forming a transistor extending through the top select gate structure and to the storage structure along the stacking direction, comprising: forming an opening through the top selection gate structure and extending to the memory structure along the stacking direction; and A second outer electrode layer, a dielectric layer and a channel layer are sequentially formed in the opening from outside to inside.

10. The method according to any one of claims 7 to 9, characterized in that: The method further comprises: forming a plurality of bit lines extending along the first direction and connected to corresponding transistors; and A plurality of contact structures extending along the stacking direction to the second conductive layer are formed.

11. A semiconductor structure, characterized in that: include: A storage structure, which runs through the stacked structure, wherein the stacked structure includes a first dielectric layer and a first conductive layer which are alternately stacked; as well as The gate line gap structure penetrates the stacked structure and extends along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure. The storage structure and the gate line gap structure sequentially include a capacitor dielectric layer and an inner electrode layer from outside to inside.

12. The semiconductor structure according to claim 11, characterized in that: The capacitor dielectric layer and the inner electrode layer in the gate line gap structure extend along the first direction, and the gate line gap structure divides the stacked structure into a plurality of storage blocks distributed along a second direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

13. The semiconductor structure according to claim 11, characterized in that: The first conductive layer is in direct contact with the capacitor dielectric layer.

14. The semiconductor structure according to claim 11 or 12, characterized in that: The storage structure and the gate line gap structure further include: a first outer electrode layer located outside the capacitor dielectric layer.

15. The semiconductor structure according to claim 11, characterized in that The semiconductor structure further comprises: A top selection gate structure, located on a surface of the stacked structure, comprises a second dielectric layer and a second conductive layer stacked in sequence; a transistor, passing through the top selection gate structure along the stacking direction and extending to the storage structure; a plurality of bit lines extending along the first direction and connected to corresponding transistors; and A plurality of contact structures extend along the stacking direction to the second conductive layer.

16. The semiconductor structure according to claim 11, characterized in that The materials of the first conductive layer and the internal electrode layer include at least one conductive material selected from the group consisting of polysilicon, titanium nitride, metal tungsten, metal platinum, and tantalum nitride.

17. The semiconductor structure according to claim 11, characterized in that The material of the capacitor dielectric layer includes at least one of a ferroelectric material and an antiferroelectric material.

18. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 11 to 17; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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