Multifunctional protection device and manufacturing process thereof

Abstract

The invention discloses a multifunctional protection device and a manufacturing process thereof, and belongs to the technical field of protection devices. A silicon dioxide layer is grown on a P-type monocrystalline silicon wafer, a boron ion injection window is photoetched on the front surface of the P-type monocrystalline silicon wafer, a light boron layer is doped on the front surface of the P-type monocrystalline silicon wafer in an ion injection mode, and high-temperature diffusion is carried out, so that the boron ion injection window is formed; carrying out ion implantation on phosphorus layers on the front surface and the back surface of the P-type monocrystalline silicon wafer, carrying out high-temperature diffusion to distribute the phosphorus layers, carrying out photoetching on the front surface of the P-type monocrystalline silicon wafer to form a thick boron diffusion region window, and carrying out thick boron diffusion on the front surface; the method comprises the following steps: photoetching thick phosphorus layer diffusion windows on the front surface and the back surface of a P-type monocrystalline silicon wafer, carrying out thick phosphorus layer diffusion on double surfaces, photoetching a groove corrosion window on the front surface of the P-type monocrystalline silicon wafer, carrying out silicon corrosion, forming an inner groove mesa structure, and carrying out metallization treatment on the front surface and the back surface of the P-type monocrystalline silicon wafer to construct a metal layer.

Description

Technical Field

[0001] The invention relates to a protection device, in particular to a multifunctional protection device and a manufacturing process thereof, belonging to the technical field of protection devices. Background Art

[0002] The Zener diode is a surface-contact crystal diode made of silicon material, also known as the Zener diode. This diode is a semiconductor device with very high resistance until the critical reverse breakdown voltage. When the Zener diode breaks down in reverse, the terminal voltage remains almost unchanged within a certain current range, showing a voltage-stabilizing characteristic. Therefore, it is widely used in voltage-stabilized power supplies and limiting circuits.

[0003] A trigger diode is a special diode, also known as a trigger tube. Based on its special four-layer PNPN structure, it can conduct in both forward and reverse directions. The unidirectional trigger tube is improved on the basis of the bidirectional trigger tube. When working, it only uses one direction to trigger the voltage, and the chip manufacturing process is simpler than the bidirectional trigger tube. This device has a wide range of applications, such as power switches, AC dimming, motor control, negative ion generators, pulse igniters and other fields. It plays an important role.

[0004] As common discrete devices, the two diodes are independently manufactured in chip manufacturing and finished product packaging. However, in actual use, they are often used in combination in some circuits. With the trend of miniaturization of integrated circuit packaging and the requirement of cost reduction, various circuit board manufacturers are trying to reduce the volume of the package and the area of ​​the circuit board. However, the two devices as independent devices cannot be reduced any further and have reached the design limit. Therefore, a multifunctional protection device and its manufacturing process are designed to solve the above problems. Summary of the invention

[0005] The main purpose of the present invention is to provide a multifunctional protection device and a manufacturing process thereof.

[0006] The purpose of the present invention can be achieved by adopting the following technical solutions: A multifunctional protection device manufacturing process comprises the following steps: Step 1: growing a silicon dioxide layer on the front and back sides of a P-type single crystal silicon wafer by thermal oxidation; Step 2: Photolithography a boron ion implantation window on the front side of the P-type single crystal silicon wafer; Step 3: A light boron layer is doped on the front side of the P-type single crystal silicon wafer by ion implantation, and the light boron layer is redistributed by high-temperature diffusion. At the same time, a silicon dioxide layer is grown on the surface as a masking layer for subsequent diffusion. Step 4: Photolithography of light phosphorus injection windows on the front and back of the P-type single crystal silicon wafer; Step 5: Ion implantation of phosphorus layer is performed on the front and back of the P-type single crystal silicon wafer, and the phosphorus layer is distributed through high temperature diffusion. At the same time, a layer of silicon dioxide is grown on the surface as a masking layer for subsequent diffusion; Step 6: Photolithography a window of concentrated boron diffusion region on the front side of the P-type single crystal silicon wafer; Step 7: Diffuse a concentrated boron layer on the front side of the P-type single crystal silicon wafer, and simultaneously grow a layer of silicon dioxide on the surface as a masking layer for subsequent diffusion; Step 8: Photolithography of phosphorus-rich windows on the front and back of the P-type single crystal silicon wafer; Step 9: Diffuse a concentrated phosphorus layer on the front and back of the P-type single crystal silicon wafer, and grow a layer of silicon dioxide on the surface as a subsequent masking layer; Step 10: Photolithography a trench etching window on the front side of the P-type single crystal silicon wafer; Step 11: Perform silicon etching at the trench etching window on the front side of the P-type single crystal silicon wafer to form an inner trench mesa structure; Step 12: Fill a layer of glass into the inner groove table formed on the front side of the P-type single crystal silicon wafer as a PN junction protection passivation layer; Step 13: Depositing a layer of silicon dioxide on the front side of the P-type single crystal silicon wafer by LPCVD; Step 14: Photolithography the lead windows of the trigger tube and the voltage regulator tube on the front and back of the P-type single crystal silicon wafer, and at the same time, open the scribe grooves on the edge; Step 15: Perform metallization treatment on the front and back of the P-type single crystal silicon wafer to construct a metal layer; Step 16: Photolithography of the electrode lead welding area on the front side of the P-type single crystal silicon wafer; Step 17: Alloying is performed under vacuum to allow the metal layer to form an ohmic contact with silicon, thereby completing the manufacturing of the protective device.

[0007] Preferably, in step 1, the resistivity of the P-type single crystal silicon wafer is 20-100 Ω.cm.

[0008] Preferably, the ion implantation energy of the light boron layer doped by ion implantation in step 3 is E=60~110KeV, and the dose DOSE=1E13 / cm 2 ~8E14 / cm 2 ; The temperature of the light boron layer diffusion is: 1260℃~1280℃, the time is: 80~120h, and the final x j =60~100µm.

[0009] Preferably, in step 5, the ion implantation energy of the phosphorus layer doped by ion implantation is E=60~110KeV, and the dose DOSE=5E14 / cm 2 ~2E15 / cm 2 ; The temperature of phosphorus layer re-diffusion is: 1230℃~1260℃, time: 20~50h, and the final x j =15~35µm.

[0010] Preferably, the temperature of the concentrated boron layer pre-diffusion in step seven is: 1000°C~1100°C, the time is: 60min~300min, and the surface concentration R=2~15Ω / □; The temperature of the concentrated boron layer re-diffusion is: 1150℃~1250℃, time: 5~10h, and the final x j =10~30µm.

[0011] Preferably, the pre-diffusion temperature of the concentrated phosphorus layer in step nine is: 960°C~1100°C, the time is: 60min~120min, R=0.8~5Ω / □; The temperature of the concentrated phosphorus layer re-diffusion is: 1000℃~1150℃, time: 4~8h, and the final x j =8~20µm.

[0012] Preferably, the depth of the inner groove terrace in step 11 is 40-80 μm.

[0013] Preferably, the glass passivation temperature in step twelve is 460°C to 750°C.

[0014] Preferably, in step fifteen, the front side of the metal layer on the front and back sides of the P-type single crystal silicon wafer is an aluminum layer with a thickness of 4 to 6 µm, and the back side of the metal layer is a titanium nickel silver layer with a thickness of 1 to 3 µm.

[0015] A multifunctional protection device comprises a P-type single crystal silicon wafer, wherein a phosphorus layer is arranged on the back side of the P-type single crystal silicon wafer and near the middle of the front side of the P-type single crystal silicon wafer; A concentrated phosphorus layer is provided in the phosphorus layer on the front side of the P-type single crystal silicon wafer, and a concentrated phosphorus layer is laid on the phosphorus layer on the back side of the P-type single crystal silicon wafer; A light boron layer is provided on the front side of the P-type single crystal silicon wafer and below the phosphorus layer on the front side of the P-type single crystal silicon wafer; A concentrated boron layer is also provided in the phosphorus layer on the front side of the P-type single crystal silicon wafer.

[0016] Beneficial technical effects of the present invention: The present invention provides a multifunctional protection device and its manufacturing process. The product of this patent can achieve the purpose of replacing two different types of chips with one chip. One chip realizes two functions. The chip manufacturing is applicable to the same process platform, which greatly saves the chip manufacturing cost and cycle; The trigger voltage of the trigger tube can be adjusted arbitrarily between 70-300V. Based on the same chip, only fine-tuning of the process is required to meet the voltage requirements of different application fields. There is no need to design and develop chips separately, and the two chips will not affect each other. A three-terminal package shape can replace the original two two-terminal package shapes, saving the package cost and reducing the space occupied by the circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A chip cross-sectional view of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention; Figure 2 A front plan view of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention; Figure 3 A circuit diagram of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention; Figure 4-Figure 18 A schematic diagram is made for each step of a preferred embodiment of a multifunctional protection device and a manufacturing process thereof according to the present invention.

[0018] In the figure: 1. P-type single crystal silicon wafer, 2. Silicon dioxide layer, 3. Boron ion implantation window, 4. Light boron layer, 5. Light phosphorus implantation window, 6. First phosphorus layer, 7. Titanium nickel silver layer, 8. Concentrated boron diffusion zone window, 9. Concentrated boron layer, 10. Concentrated phosphorus zone window; 11. Concentrated phosphorus layer, 12. Groove corrosion window, 13. Inner groove terrace, 14. PN junction protection passivation layer, 15. Lead window, 16. Aluminum layer, 17. Electrode lead welding area. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0020] like Figure 1-2 A multifunctional protection device chip is shown, and its manufacturing process includes the following steps: Step 1) A silicon dioxide layer 2 is grown on a P-type single crystal silicon wafer 1 having a resistivity of 20 to 100 Ω.cm by thermal oxidation. Figure 4 ; Step 2) Photolithography of the boron ion implantation window 3 on the front side, see Figure 5 ; Step 3) The light boron layer 4 is doped on the front side by ion implantation, and the light boron layer 4 is redistributed by high temperature diffusion. At the same time, a layer of silicon dioxide layer 2 is grown on the surface as a masking layer for subsequent diffusion. The ion implantation energy E=60~110KeV and the dose DOSE=1E13 / cm 2 ~8E14 / cm 2 ; Boron re-diffusion temperature: 1260℃~1280℃, time: 80~120h, final x j =60~100µm, see Figure 6 ; Step 4) Double-sided photolithography to form a light phosphorus injection window 5, see Figure 7 ; Step 5) Phosphorus layer 6 is ion-implanted on both sides of the chip, and the phosphorus layer 6 is distributed through high-temperature diffusion. At the same time, a silicon dioxide layer 2 is grown on the surface as a masking layer for subsequent diffusion. The ion implantation method dopes a layer of light phosphorus with an ion implantation energy of E=60~110KeV and a dose of DOSE=5E14 / cm 2 ~2E15 / cm 2 ; Phosphorus re-diffusion temperature: 1230℃~1260℃, time: 20~50h, final x j =15~35µm, see Figure 8 ; Step 6) Photolithography of the concentrated boron diffusion area window 8 on the front side, see Fig. 9 ; Step 7) Diffuse the concentrated boron layer 9 on the front side, and grow a silicon dioxide layer 2 on the surface as a masking layer for subsequent diffusion. The pre-diffusion temperature of the concentrated boron layer 9 is 1000°C to 1100°C, and the time is 60min to 300min. R=2~15Ω / □; the temperature of the concentrated boron layer 9 for re-diffusion is: 1150℃~1250℃, time: 5~10h, and the final x j =10~30µm, see Fig.10 ; Step 8) Double-sided photolithography to form phosphorus-rich window 10, see Fig.11 ; Step 9) Diffuse the concentrated phosphorus layer 11 on both sides, and grow a silicon dioxide layer 2 on the surface as a subsequent masking layer. The pre-diffusion temperature of the concentrated phosphorus layer 11 is 960°C to 1100°C, and the time is 60min to 120min. R = 0.8 ~ 5Ω / □; the temperature of the concentrated phosphorus layer 11 is: 1000 ℃ ~ 1150 ℃, time: 4 ~ 8h, the final xj = 8 ~ 20µm, see Fig.12 ; Step 10) Photolithography a groove etching window 12 on the front side, see Fig.13 ; Step 11) Silicon etching is performed at the front trench etching window 12 to form an inner trench terrace 13 structure, and the depth of the trench is 40~80μm, see Fig.14 ; Step 12) Fill a layer of glass in the front inner groove as the final PN junction protection passivation layer 14. The glass passivation temperature is: 460℃~750℃, see Fig.15 ; Step 13) depositing a silicon dioxide layer 2 on the surface by LPCVD, wherein the thickness of the silicon dioxide layer 2 is 0.1-0.5 µm; Step 14) Photolithography the lead windows 15 of the trigger tube and the voltage regulator tube on the front and back sides, and at the same time, make a scribe groove on the edge. Fig.16 ; Step 15) Metallization on the front and back sides, the front side of the metal layer is an aluminum layer 16 with a thickness of 4~6µm, and the back side is a titanium nickel silver layer 7 with a thickness of 1~3µm, see Fig.17 ; Step 16) Photolithography the welding area of ​​the electrode lead and remove the metal in the unnecessary area. Fig.18 ; Step 17) Alloying is performed in a vacuum at a temperature of 300-500°C to allow the metal to form a good ohmic contact with silicon, thereby completing chip production. Fig.18 . Example

[0021] The P-type resistivity in step 1 is 20~30Ω.cm; the ion implantation energy of the light boron layer 4 in step 3 is E=70KeV, and the dose DOSE=2.9E14 / cm 2 The temperature of the light boron layer 4 for re-diffusion is 1270°C and the time is 100h; the ion implantation energy of the phosphorus layer 6 in step 5 is E=70KeV and the dose DOSE=9E14 / cm 2 , the temperature of phosphorus layer 6 re-diffusion is 1240℃, the time is 38h; the temperature of concentrated boron layer 9 pre-diffusion in step 7 is: 1050℃, the time is: 120min, the temperature of concentrated boron layer 9 re-diffusion is 1180℃, the time is 5h. The final chip parameters are: trigger tube V DRM :105~110V、I H : 10~50mA; V of the voltage regulator tube BR : 400~420V. Example

[0022] The P-type resistivity in step 1 is 40~60Ω.cm; the ion implantation energy of the light boron layer 4 in step 3 is E=70KeV, and the dose DOSE=1.35E14 / cm 2The temperature of the light boron layer 4 for re-diffusion is 1270°C and the time is 102h; the ion implantation energy of the phosphorus layer 6 in step 5 is E=70KeV and the dose DOSE=8.5E14 / cm 2 , the temperature of phosphorus layer 6 re-diffusion is 1240℃, the time is 40h; the temperature of concentrated boron layer 9 pre-diffusion in step 7 is: 1060℃, the time is: 150min, the temperature of concentrated boron layer 9 re-diffusion is 1200℃, the time is 5h. The final chip parameters are: trigger tube V DRM : 145~155V, IH: 10~50mA; VBR of Zener diode: 600~700V.

[0023] The above description is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which belong to the protection scope of the present invention.

Claims

1. A multifunctional protection device manufacturing process, characterized in that: The steps include: Step 1: growing a silicon dioxide layer (2) on the front and back sides of the P-type single crystal silicon wafer (1) by thermal oxidation; Step 2: photolithography a boron ion implantation window (3) on the front side of the P-type single crystal silicon wafer (1); Step 3: doping a light boron layer (4) on the front side of the P-type single crystal silicon wafer (1) by ion implantation, and redistributing the light boron layer (4) by high temperature diffusion, while growing a silicon dioxide layer (2) on the surface as a masking layer for subsequent diffusion; Step 4: Photolithography a light phosphorus injection window (5) on the front and back sides of the P-type single crystal silicon wafer (1); Step 5: ion implant the phosphorus layer (6) on the front and back sides of the P-type single crystal silicon wafer (1), and distribute the phosphorus layer (6) through high temperature diffusion, while growing a silicon dioxide layer (2) on the surface as a masking layer for subsequent diffusion; Step 6: Photolithography a concentrated boron diffusion region window (8) on the front side of the P-type single crystal silicon wafer (1); Step 7: Diffusing a concentrated boron layer (9) on the front side of the P-type single crystal silicon wafer (1), and growing a silicon dioxide layer (2) on the surface as a masking layer for subsequent diffusion; Step 8: Photolithography of phosphorus-rich area windows (10) on the front and back sides of the P-type single crystal silicon wafer (1); Step nine: a concentrated phosphorus layer (11) is diffused on the front and back sides of the P-type single crystal silicon wafer (1), and a silicon dioxide layer (2) is grown on the surface as a subsequent masking layer; Step 10: Photolithography a trench etching window (12) on the front side of the P-type single crystal silicon wafer (1); Step 11: performing silicon etching at the front trench etching window of the P-type single crystal silicon wafer (1) to form an inner trench terrace (13) structure; Step 12: Filling a layer of glass as a PN junction protection passivation layer (14) in the inner groove terrace (13) formed on the front side of the P-type single crystal silicon wafer (1); Step 13: depositing a silicon dioxide layer (2) on the front side of the P-type single crystal silicon wafer (1) by LPCVD; Step 14: photolithography the lead windows (15) of the trigger tube and the voltage regulator tube on the front and back sides of the P-type single crystal silicon wafer (1), and at the same time, opening a scribe groove on the edge; Step 15: Performing metallization treatment on the front and back sides of the P-type single crystal silicon wafer (1) to construct a metal layer; Step 16: Photolithography an electrode lead welding area (17) on the front side of the P-type single crystal silicon wafer (1); Step 17: Alloying is performed under vacuum to allow the metal layer to form an ohmic contact with silicon, thereby completing the manufacturing of the protective device.

2. A multifunctional protection device manufacturing process according to claim 1, characterized in that: In step 1, the resistivity of the P-type single crystal silicon wafer (1) is 20-100 Ω.cm.

3. A multifunctional protection device manufacturing process according to claim 2, characterized in that: In step 3, the ion implantation energy of the light boron layer (4) doped by ion implantation is E=60~110KeV, and the dose DOSE=1E13 / cm2~8E14 / cm2; The diffusion temperature of the light boron layer (4) is: 1260℃~1280℃, the time is: 80~120h, and the final xj=60~100µm.

4. A multifunctional protection device manufacturing process according to claim 3, characterized in that: In step 5, the ion implantation energy of the phosphorus layer (6) is 60-110 KeV, and the dose DOSE is 5E14 / cm2-2E15 / cm2; The re-diffusion temperature of the phosphorus layer (6) is: 1230℃~1260℃, the time is: 20~50h, and the final xj=15~35µm.

5. A process for manufacturing a multifunctional protection device according to claim 4, characterized in that: The pre-diffusion temperature of the concentrated boron layer (9) in step 7 is: 1000°C~1100°C, the time is: 60min~300min, and the surface concentration R=2~15Ω / □; The temperature of the re-diffusion of the concentrated boron layer (9) is: 1150℃~1250℃, time: 5~10h, and the final xj=10~30µm.

6. A process for manufacturing a multifunctional protection device according to claim 5, characterized in that: In step nine, the pre-diffusion temperature of the concentrated phosphorus layer (11) is: 960°C~1100°C, the time is: 60min~120min, R=0.8~5Ω / □; The re-diffusion temperature of the concentrated phosphorus layer (11) is: 1000℃~1150℃, time: 4~8h, and the final xj=8~20µm.

7. A process for manufacturing a multifunctional protection device according to claim 6, characterized in that: The depth of the inner groove terrace (13) in step 11 is 40-80 µm.

8. A multifunctional protection device and its manufacturing process according to claim 7, characterized in that: In step 12, the glass passivation temperature is 460°C to 750°C.

9. A process for manufacturing a multifunctional protection device according to claim 8, characterized in that: In step 15, the metal layers on the front and back sides of the P-type single crystal silicon wafer (1) are aluminum layers (16) on the front side with a thickness of 4-6 µm, and titanium-nickel-silver layers (7) on the back side with a thickness of 1-3 µm.

10. A multifunctional protection device, prepared based on the multifunctional protection device manufacturing process according to claim 9, characterized in that: It comprises a P-type single crystal silicon wafer (1), wherein a phosphorus layer (6) is provided on the back side of the P-type single crystal silicon wafer (1) and near the middle of the front side of the P-type single crystal silicon wafer (1); A concentrated phosphorus layer (11) is provided in the phosphorus layer (6) on the front side of the P-type single crystal silicon wafer (1), and a concentrated phosphorus layer (11) is laid on the phosphorus layer (6) on the back side of the P-type single crystal silicon wafer (1); A light boron layer (4) is provided on the front side of the P-type single crystal silicon wafer (1) and below the phosphorus layer (6) on the front side of the P-type single crystal silicon wafer (1); A concentrated boron layer (9) is also provided in the phosphorus layer (6) on the front side of the P-type single crystal silicon wafer (1).

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