Semiconductor device and preparation method thereof
By alternately stacking sacrificial layers and horizontal channels in GAA devices and selectively removing false gates and sacrificial layers to form residual sacrificial layers and vertical channels, the problem of limited driving capabilities of existing GAA devices is solved, and a higher level of Drive capability and better balance capability of N-type and P-type transistors.
Patent Information
- Application Number
- CN202411593444.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-21
AI Technical Summary
When preparing SiGe/Si superlattice stacks, the SiGe sacrificial layer is usually completely removed, resulting in limited device driving capabilities, especially the driving capabilities of PMOS are greatly affected by crystal direction.
By preparing a stack formed by alternate stacking of sacrificial layers and horizontal channels on the substrate, and selectively removing the false gate and sacrificial layers without increasing the number of stacks, forming residual sacrificial layers and vertical channels, In turn, the gate material is filled to form the gate.
Without increasing the number of stacked layers, the driving capability of semiconductor devices, especially the driving capability of PMOS, is improved, which is conducive to improving the balance capability of N-type and P-type transistors.
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Figure CN119497407A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art
[0002] As complementary metal oxide semiconductor (CMOS) devices continue to shrink along Moore's Law, mass production has entered the 5nm or even 3nm technology node. The use of all-around gate (GAA) devices can effectively suppress the short channel effect.
[0003] At present, when mainstream GAA devices use epitaxial method to prepare SiGe / Si superlattice stacking, SiGe is generally completely removed as a sacrificial layer, leaving only Si material as a conductive channel. In order to avoid excessive stacking layers to increase parasitic effects, the number of stacking layers of existing GAA devices is usually three, resulting in limited device driving capabilities, especially the driving capability of PMOS is greatly affected by the crystal orientation.
[0004] In view of this, the present invention is proposed. Summary of the invention
[0005] The object of the present invention is to provide a semiconductor device and a method for preparing the same, which can improve the driving capability of the semiconductor device without increasing the number of stacked layers.
[0006] The present invention provides a method for preparing a semiconductor device, comprising the following steps:
[0007] S1: preparing a stack formed by alternately stacking sacrificial layers and horizontal channels on a substrate, preparing a dummy gate on the stack, preparing a sidewall on the sidewalls of the sacrificial layers and the dummy gate, and preparing a source and a drain on both sides of the stack;
[0008] S2: removing the dummy gate, selectively removing the sacrificial layer, and forming a residual sacrificial layer in the vertical direction;
[0009] S3: forming a protective layer on one side of the stack, performing selective epitaxy on the other side of the stack, and forming a vertical channel on the sidewall of the remaining sacrificial layer;
[0010] S4: removing the protective layer and the remaining sacrificial layer to form a channel structure, and filling the gate material to form a gate.
[0011] In step S1, preparing the stack includes: forming an active area groove on the substrate, alternately stacking a sacrificial layer and a horizontal channel in the active area groove to form a stack; there is no strict restriction on the number and size of the horizontal channels, which can be reasonably set according to actual needs, and the horizontal channels can be set to three layers, for example. In addition, the material of the sacrificial layer can be SiGe, etc., and the material of the horizontal channel can be polysilicon, etc.; in particular, the material of the sacrificial layer and the horizontal channel is preferably capable of forming a vertical channel and a horizontal channel of the same single crystal material during selective epitaxy.
[0012] The preparation of the dummy gate and the sidewall includes: forming a dummy gate dielectric layer and a dummy gate above the stack, and forming a sidewall on the sacrificial layer, the dummy gate dielectric layer and the sidewall of the dummy gate; wherein the material of the dummy gate dielectric layer can be SiO2, etc., and the material of the dummy gate can be polysilicon, etc.
[0013] The preparation of the source and drain includes: forming a source trench and a drain trench on a substrate, epitaxially growing a source crystal structure and a drain crystal structure in the source trench and the drain trench, and filling a dielectric material to form the source and the drain; wherein the material of the source crystal structure and the drain crystal structure can be SiGe or the like.
[0014] In step S2, removing the dummy gate includes: first removing the natural oxide layer on the surface of the dummy gate, then removing the dummy gate material, and then removing the dummy gate dielectric layer. The specific removal method is not strictly limited, for example, diluted hydrogen fluoride (HF) can be used to remove the natural oxide layer, the dilution ratio of hydrogen fluoride is, for example, 100:1, and the time is 5-60s, for example, 5-12s; tetramethylammonium hydroxide (TMAH) can be used to remove the dummy gate material; DHF (dilute hydrofluoric acid) or buffered oxide etchant (BOE) can be used to remove the dummy gate dielectric layer, and the dilution ratio of DHF is, for example, 100:1.
[0015] In addition, a remote plasma source (RPS source) etching method and / or a pure gas etching method is used to selectively remove the sacrificial layer, thereby forming a residual sacrificial layer in the vertical direction; preferably, remote plasma source etching is first used to ensure a higher etching accuracy; and then pure gas etching is used to reduce interface damage. The etching amount of pure gas etching can be 0.2-3nm, preferably 1-3nm.
[0016] More specifically, the remote plasma source etching includes a cyclic processing step and an etching step, the temperature of the RPS source is 0-250°C, preferably 110-200°C; the power of the RPS source is 100-1500w, preferably 200-900w, and further preferably 500-900w; the processing step gas adopts a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 1:1:5 to 5:5:1, and the etching step gas adopts a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 1:1:2 to 2:1:1. The remote plasma source etching process is regulated according to the equipment process performance, and the processing step and the etching step are cyclically performed until the etching amount reaches the expected value. The gas used for pure gaseous etching is a mixed gas of ClF3, F2 and Ar, the volume ratio of ClF3, F2 and Ar in the mixed gas is 1:0:0 to 0:1:100, and the temperature is -100°C to 250°C, preferably -20°C to 60°C, and further preferably -20°C to 20°C.
[0017] After the sacrificial layer is selectively removed, the thickness of the residual sacrificial layer formed in the vertical direction is controlled to be 1-10 nm, preferably 1-7 nm, more preferably 1-5 nm, and even more preferably 5 nm.
[0018] In step S3, forming a protective layer includes: using a protective material to perform photolithography patterning on the stack to protect one side of the stack, and the protective material may be amorphous carbon (SOC).
[0019] Selective epitaxy includes: using a mixed gas of SiH4 and HCl to perform reduced pressure vapor deposition (RPCVD) on the stacked layers; wherein the temperature during reduced pressure vapor deposition is 500-800°C, and the volume ratio of SiH4 to HCl in the mixed gas is 1:5 to 5:1. In addition, before selective epitaxy, H2 can be used to remove the natural oxide layer.
[0020] When the vertical channel is formed by selective epitaxy, the thickness of the vertical channel can be controlled to be 1-10 nm, preferably 2-5 nm, more preferably 3-5 nm, and more preferably 3 nm. In particular, the vertical channel and the horizontal channel are made of the same single crystal material, such as single crystal silicon.
[0021] In step S4, the protective layer can be removed by O2 plasma, and the residual sacrificial layer can be removed by remote plasma etching and / or pure gas etching. In addition, before filling the gate material, a high-K material can be grown on the surface of the channel structure to form a gate dielectric layer, and the thickness of the gate dielectric layer is 0.5-3nm, for example, 2-2.5nm. After the gate is formed, the lead-out structures connected to the source, gate and drain are prepared in a conventional manner.
[0022] The present invention also provides a semiconductor device, which is manufactured according to the above manufacturing method.
[0023] The preparation method of the present invention increases channels in different directions by selectively removing sacrificial layers and selectively performing epitaxy, which can improve the driving capability of semiconductor devices, especially the driving capability of PMOS, without increasing the number of stacked layers, and is beneficial to improving the balance capability of N-type and P-type transistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 A schematic diagram of the front structure after forming the stack, dummy gate, sidewall, source and drain;
[0026] Figure 2 This is a schematic diagram of the front structure after removing the false grille;
[0027] Figure 3 A schematic diagram of the side structure after the residual sacrificial layer is formed;
[0028] Figure 4 A schematic diagram of the front structure after the protective layer is formed;
[0029] Figure 5 A schematic diagram of the side structure after the protective layer is formed;
[0030] Figure 6 It is a schematic diagram of the side structure after selective epitaxy;
[0031] Figure 7 A schematic diagram of the side structure after the channel structure is formed;
[0032] Figure 8 It is a schematic diagram of the side structure after filling the gate material;
[0033] Fig. 9 This is a schematic diagram of the front structure after the lead-out structure is prepared.
[0034] Description of reference numerals:
[0035] 1: substrate; 2: sacrificial layer; 3: horizontal channel; 4: dummy gate dielectric layer; 5: dummy gate; 6: sidewall; 7: source crystal structure; 8: drain crystal structure; 9: dielectric material; 10: residual sacrificial layer; 11: protective layer; 12: vertical channel; 13: channel structure; 14: gate material; 15: source lead structure; 16: gate lead structure; 17: drain lead structure. DETAILED DESCRIPTION
[0036] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.
[0037] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this description, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0038] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0039] Example 1
[0040] The method for preparing a semiconductor device of this embodiment comprises the following steps:
[0041] S1: Preparation of stacking, false gate, sidewall, source, drain
[0042] Combination Figure 1 As shown, an active region trench, a source trench and a drain trench are formed on a substrate 1 , and the source trench and the drain trench are located at two sides of the active region trench.
[0043] Three sacrificial layers 2 and three horizontal channels 3 are alternately stacked in the active area grooves to form a stack, the sacrificial layer 2 is made of SiGe, and the horizontal channel 3 is made of polysilicon; a dummy gate dielectric layer 4 is formed above the stack, and the material of the dummy gate dielectric layer 4 is SiO2; a dummy gate 5 is formed above the dummy gate dielectric layer 4, and the material of the dummy gate 5 is polysilicon; and a sidewall 6 is formed on the sidewalls of the sacrificial layer 2, the dummy gate dielectric layer 4 and the dummy gate 5.
[0044] A source crystal structure 7 and a drain crystal structure 8 are epitaxially grown in the source trench and the drain trench, and the material of the source crystal structure 7 and the drain crystal structure 8 is SiGe; and a dielectric material 9 is filled to form a source and a drain.
[0045] S2: Selective removal of sacrificial layer
[0046] Combination Figure 2 As shown, HF diluted 100:1 is used to remove the natural oxide layer on the surface of the dummy gate 5 for 5-10 seconds; TMAH is used to remove the dummy gate 5; and DHF diluted 100:1 is used to remove the dummy gate dielectric layer 4.
[0047] Combination Figure 3 As shown, the sacrificial layer 2 is first selectively removed by RPS source etching. The RPS source etching includes a cyclic processing step and an etching step. The temperature of the RPS source is 200°C, the power of the RPS source is 900w, the processing step gas uses a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 1:1:5. The etching step gas uses a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 1:1:2. The processing step and the etching step are cyclically performed until the etching amount reaches the expected value.
[0048] Then, pure gas etching is used to selectively remove the sacrificial layer 2, wherein the gas used in the pure gas etching is ClF3, the temperature is 20° C., and the etching amount of the pure gas etching is 2 nm. After the pure gas etching, a residual sacrificial layer 10 is formed in the vertical direction, and the thickness of the residual sacrificial layer 10 is 5 nm.
[0049] S3: Selective Epitaxy
[0050] Combination Figure 4 , Figure 5 As shown, SOC is spin-coated on one side of the stack and a protective portion is patterned by photolithography to form a protective layer 11; subsequently, H2 is used to remove the natural oxide layer on the other side of the stack.
[0051] Combination Figure 6 As shown, a mixed gas of SiH4 and HCl is used to perform reduced pressure vapor deposition on the other side of the stack. The temperature during the reduced pressure vapor deposition is 650°C, and the volume ratio of SiH4 to HCl in the mixed gas is 1:5. An epitaxial layer is formed on the surface of the horizontal channel 3, and a vertical channel 12 is formed on the side wall of the residual sacrificial layer 10. The thickness of the vertical channel 12 is 3nm, and the material of the vertical channel 12 is single crystal silicon.
[0052] S4: Preparation of channel structure, gate and lead structure
[0053] Combination Figure 7As shown, the protective layer 11 is removed by O2 plasma, and the residual sacrificial layer 10 is removed by remote plasma source etching and pure gas etching in sequence, so as to form a channel structure 13 composed of a horizontal channel and a vertical channel 12.
[0054] A high-K material is grown on the surface of the channel structure 13 to form a gate dielectric layer, the thickness of the gate dielectric layer is 2.5 nm; Figure 8 As shown, a gate material 14 is filled to form a gate.
[0055] Combination Fig. 9 As shown, a source lead-out structure 15, a gate lead-out structure 16 and a drain lead-out structure 17 respectively connected to the source, the gate and the drain are prepared in a conventional manner, that is, a semiconductor device is obtained; after testing, the subthreshold swing of the semiconductor device is 61mV / dec.
[0056] Example 2
[0057] The method for preparing a semiconductor device of this embodiment comprises the following steps:
[0058] S1: Preparation of stacking, false gate, sidewall, source, drain
[0059] Combination Figure 1 As shown, an active region trench, a source trench and a drain trench are formed on a substrate 1 , and the source trench and the drain trench are located at two sides of the active region trench.
[0060] Three sacrificial layers 2 and three horizontal channels 3 are alternately stacked in the active area grooves to form a stack, the sacrificial layer 2 is made of SiGe, and the horizontal channel 3 is made of polysilicon; a dummy gate dielectric layer 4 is formed above the stack, and the material of the dummy gate dielectric layer 4 is SiO2; a dummy gate 5 is formed above the dummy gate dielectric layer 4, and the material of the dummy gate 5 is polysilicon; and a sidewall 6 is formed on the sidewalls of the sacrificial layer 2, the dummy gate dielectric layer 4 and the dummy gate 5.
[0061] A source crystal structure 7 and a drain crystal structure 8 are epitaxially grown in the source trench and the drain trench, and the material of the source crystal structure 7 and the drain crystal structure 8 is SiGe; and a dielectric material 9 is filled to form a source and a drain.
[0062] S2: Selective removal of sacrificial layer
[0063] Combination Figure 2 As shown, HF diluted 100:1 is used to remove the natural oxide layer on the surface of the dummy gate 5 for 12 seconds; TMAH is used to remove the dummy gate 5; and BOE is used to remove the dummy gate dielectric layer 4.
[0064] Combination Figure 3As shown, the sacrificial layer 2 is first selectively removed by RPS source etching. The RPS source etching includes a cyclic processing step and an etching step. The temperature of the RPS source is 110°C, the power of the RPS source is 500w, the processing step gas uses a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 5:5:1. The etching step gas uses a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 2:1:1. The processing step and the etching step are cyclically performed until the etching amount reaches the expected value.
[0065] Then, the sacrificial layer 2 is selectively removed by pure gas etching, wherein the gas used in the pure gas etching is a mixed gas of F2 and Ar, wherein the volume ratio of F2 to Ar in the mixed gas is 1:100, the temperature is -20°C, and the etching amount of the pure gas etching is 3nm. After the pure gas etching, a residual sacrificial layer 10 is formed in the vertical direction, and the thickness of the residual sacrificial layer 10 is 3nm.
[0066] S3: Selective Epitaxy
[0067] Combination Figure 4 , Figure 5 As shown, SOC is spin-coated on one side of the stack and a protective portion is patterned by photolithography to form a protective layer 11; subsequently, H2 is used to remove the natural oxide layer on the other side of the stack.
[0068] Combination Figure 6 As shown, a mixed gas of SiH4 and HCl is used to perform reduced pressure vapor deposition on the other side of the stack. The temperature during the reduced pressure vapor deposition is 800°C, and the volume ratio of SiH4 to HCl in the mixed gas is 5:1. An epitaxial layer is formed on the surface of the horizontal channel 3, and a vertical channel 12 is formed on the side wall of the residual sacrificial layer 10. The thickness of the vertical channel 12 is 3nm, and the material of the vertical channel 12 is single crystal silicon.
[0069] S4: Preparation of channel structure, gate and lead structure
[0070] Combination Figure 7 As shown, the protective layer 11 is removed by O2 plasma, and the residual sacrificial layer 10 is removed by remote plasma source etching and pure gas etching in sequence, so as to form a channel structure 13 composed of a horizontal channel and a vertical channel 12.
[0071] A high-K material is grown on the surface of the channel structure 13 to form a gate dielectric layer, and the thickness of the gate dielectric layer is 2 nm; Figure 8 As shown, a gate material 14 is filled to form a gate.
[0072] Combination Fig. 9As shown, a source lead-out structure 15, a gate lead-out structure 16 and a drain lead-out structure 17 respectively connected to the source, the gate and the drain are prepared in a conventional manner, that is, a semiconductor device is obtained; after testing, the subthreshold swing of the semiconductor device is 60.5mV / dec.
[0073] Example 3
[0074] The method for preparing a semiconductor device of this embodiment comprises the following steps:
[0075] S1: Preparation of stacking, false gate, sidewall, source, drain
[0076] Combination Figure 1 As shown, an active region trench, a source trench and a drain trench are formed on a substrate 1 , and the source trench and the drain trench are located at two sides of the active region trench.
[0077] Three sacrificial layers 2 and three horizontal channels 3 are alternately stacked in the active area grooves to form a stack, the sacrificial layer 2 is made of SiGe, and the horizontal channel 3 is made of polysilicon; a dummy gate dielectric layer 4 is formed above the stack, and the material of the dummy gate dielectric layer 4 is SiO2; a dummy gate 5 is formed above the dummy gate dielectric layer 4, and the material of the dummy gate 5 is polysilicon; and a sidewall 6 is formed on the sidewalls of the sacrificial layer 2, the dummy gate dielectric layer 4 and the dummy gate 5.
[0078] A source crystal structure 7 and a drain crystal structure 8 are epitaxially grown in the source trench and the drain trench, and the material of the source crystal structure 7 and the drain crystal structure 8 is SiGe; and a dielectric material 9 is filled to form a source and a drain.
[0079] S2: Selective removal of sacrificial layer
[0080] Combination Figure 2 As shown, HF diluted 100:1 is used to remove the natural oxide layer on the surface of the dummy gate 5 for 8 seconds; TMAH is used to remove the dummy gate 5; and DHF diluted 100:1 is used to remove the dummy gate dielectric layer 4.
[0081] Combination Figure 3 As shown, the sacrificial layer 2 is first selectively removed by RPS source etching. The RPS source etching includes a cyclic processing step and an etching step. The temperature of the RPS source is 150°C, the power of the RPS source is 200w, the processing step gas uses a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 1:1:1. The etching step gas uses a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 1:1:1. The processing step and the etching step are cyclically performed until the etching amount reaches the expected value.
[0082] Then, pure gas etching is used to selectively remove the sacrificial layer 2, wherein the gas used in the pure gas etching is ClF3, the temperature is 0°C, and the etching amount of the pure gas etching is 1 nm. After the pure gas etching, a residual sacrificial layer 10 is formed in the vertical direction, and the thickness of the residual sacrificial layer 10 is 1 nm.
[0083] S3: Selective Epitaxy
[0084] Combination Figure 4 , Figure 5 As shown, SOC is spin-coated on one side of the stack and a protective portion is patterned by photolithography to form a protective layer 11; subsequently, H2 is used to remove the natural oxide layer on the other side of the stack.
[0085] Combination Figure 6 As shown, a mixed gas of SiH4 and HCl is used to perform reduced pressure vapor deposition on the other side of the stack. The temperature during the reduced pressure vapor deposition is 500°C, and the volume ratio of SiH4 to HCl in the mixed gas is 1:1. An epitaxial layer is formed on the surface of the horizontal channel 3, and a vertical channel 12 is formed on the side wall of the residual sacrificial layer 10. The thickness of the vertical channel 12 is 5nm, and the material of the vertical channel 12 is single crystal silicon.
[0086] S4: Preparation of channel structure, gate and lead structure
[0087] Combination Figure 7 As shown, the protective layer 11 is removed by O2 plasma, and the residual sacrificial layer 10 is removed by remote plasma source etching and pure gas etching in sequence, so as to form a channel structure 13 composed of a horizontal channel and a vertical channel 12.
[0088] A high-K material is grown on the surface of the channel structure 13 to form a gate dielectric layer, the thickness of the gate dielectric layer is 2.5 nm; Figure 8 As shown, a gate material 14 is filled to form a gate.
[0089] Combination Fig. 9 As shown, a source lead-out structure 15, a gate lead-out structure 16 and a drain lead-out structure 17 respectively connected to the source, the gate and the drain are prepared in a conventional manner, that is, a semiconductor device is obtained; after testing, the subthreshold swing of the semiconductor device is 70mV / dec.
[0090] Comparative Example 1
[0091] The method for preparing the semiconductor device of this comparative example comprises the following steps:
[0092] S1: Preparation of stacking, false gate, sidewall, source, drain
[0093] The steps of preparing the stack, dummy gate, sidewall, source and drain are the same as those in Example 1.
[0094] S2: Removal of sacrificial layer
[0095] The natural oxide layer on the surface of the dummy gate was removed by using HF diluted 100:1 for 5 seconds. The dummy gate was removed by using TMAH. The dummy gate dielectric layer was removed by using DHF diluted 100:1.
[0096] First, the sacrificial layer is selectively removed by RPS source etching. The RPS source etching includes a cyclic processing step and an etching step. The temperature of the RPS source is 100°C, the power of the RPS source is 100w, the processing step gas uses a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 1:1:5. The etching step gas uses a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 1:1:2. The processing step and the etching step are cyclically performed until the etching amount reaches the expected value.
[0097] Then, the sacrificial layer is completely removed by pure gas etching, wherein the gas used in the pure gas etching is ClF3 and the temperature is -10°C. After the sacrificial layer is completely removed, a channel structure containing only horizontal channels is formed.
[0098] S3: Preparation of gate and lead structures
[0099] A high-K material is grown on the surface of the channel structure to form a gate dielectric layer, the thickness of the gate dielectric layer is 2.5 nm; and a gate material is filled to form a gate.
[0100] A source lead-out structure, a gate lead-out structure and a drain lead-out structure respectively connected to the source, the gate and the drain are prepared in a conventional manner, so as to obtain a semiconductor device; after testing, the subthreshold swing amplitude of the semiconductor device is 100mV / dec.
[0101] Comparative Example 2
[0102] The method for preparing the semiconductor device of this comparative example comprises the following steps:
[0103] S1: Preparation of stacking, false gate, sidewall, source, drain
[0104] The steps of preparing the stack, dummy gate, sidewall, source and drain are the same as those in Example 1.
[0105] S2: Selective removal of sacrificial layer
[0106] The natural oxide layer on the surface of the dummy gate was removed by using HF diluted 100:1 for 7 seconds. The dummy gate was removed by using TMAH. The dummy gate dielectric layer was removed by using DHF diluted 100:1.
[0107] First, the sacrificial layer is selectively removed by RPS source etching. The RPS source etching includes a cyclic processing step and an etching step. The temperature of the RPS source is 120°C, the power of the RPS source is 600w, the processing step gas uses a mixed gas of O2, N2 and He, and the volume ratio of O2, N2 and He in the mixed gas is 1:1:5. The etching step gas uses a mixed gas of NF3, NH3 and O2, and the volume ratio of NF3, NH3 and O2 in the mixed gas is 1:1:2. The processing step and the etching step are cyclically performed until the etching amount reaches the expected value.
[0108] Then, the sacrificial layer is selectively removed by pure gas etching. The gas used for pure gas etching is ClF3, the temperature is 20°C, and the etching amount of pure gas etching is 3nm. After pure gas etching, a residual sacrificial layer is formed in the vertical direction as a vertical channel with a thickness of 3nm, forming a channel structure composed of a horizontal channel and a vertical channel (i.e., a residual sacrificial layer).
[0109] S3: Preparation of gate and lead structures
[0110] A high-K material is grown on the surface of the channel structure to form a gate dielectric layer, the thickness of the gate dielectric layer is 2.5 nm; and a gate material is filled to form a gate.
[0111] A source lead-out structure, a gate lead-out structure and a drain lead-out structure respectively connected to the source, the gate and the drain are prepared in a conventional manner, so as to obtain a semiconductor device; after testing, the subthreshold swing of the semiconductor device is 75mV / dec.
[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a semiconductor device, characterized in that: The steps include: S1: preparing a stack formed by alternately stacking sacrificial layers and horizontal channels on a substrate, preparing a dummy gate on the stack, preparing a sidewall on the sidewalls of the sacrificial layers and the dummy gate, and preparing a source and a drain on both sides of the stack; S2: removing the dummy gate, selectively removing the sacrificial layer, and forming a residual sacrificial layer in the vertical direction; S3: forming a protective layer on one side of the stack, performing selective epitaxy on the other side of the stack, and forming a vertical channel on the sidewall of the remaining sacrificial layer; S4: removing the protective layer and the remaining sacrificial layer to form a channel structure, and filling the gate material to form a gate.
2. The preparation method according to claim 1, characterized in that: In step S1, preparing the source and the drain includes: forming a source trench and a drain trench on a substrate, epitaxially growing a source crystal structure and a drain crystal structure in the source trench and the drain trench, and filling a dielectric material to form the source and the drain.
3. The preparation method according to claim 1, characterized in that: In step S2, the sacrificial layer is selectively removed by using a remote plasma source etching method and / or a pure gas etching method.
4. The preparation method according to claim 1 or 3, characterized in that: In step S2, the thickness of the remaining sacrificial layer is controlled to be 1-10 nm.
5. The preparation method according to claim 1, characterized in that: In step S3, the selective epitaxy includes: performing reduced pressure vapor deposition on the stack using a mixed gas of SiH4 and HCl; wherein the temperature during the reduced pressure vapor deposition is 500-800°C, and the volume ratio of SiH4 to HCl in the mixed gas is 1:5 to 5:
1.
6. The preparation method according to claim 1 or 5, characterized in that: In step S3, the thickness of the vertical channel is controlled to be 1-10 nm.
7. The preparation method according to claim 1, characterized in that: In step S3, the vertical channel and the horizontal channel are made of the same single crystal material.
8. The preparation method according to claim 1, characterized in that: In step S4, before filling the gate material, a high-K material is first grown on the surface of the channel structure to form a gate dielectric layer.
9. The preparation method according to claim 1, characterized in that: In step S4, after forming the gate electrode, lead-out structures respectively connected to the source electrode, the gate electrode and the drain electrode are prepared.
10. A semiconductor device, characterized in that: Prepared according to any one of the preparation methods of claims 1-9.