High-voltage LDMOS device and forming method thereof

Abstract

The invention provides a high-voltage LDMOS device and a forming method thereof.The forming method of the high-voltage LDMOS device comprises the steps that an etching process is executed firstly, high-voltage well regions between adjacent drift regions are etched, and grooves are formed in the high-voltage well regions; then, an HTO process is executed, a gate oxide layer is formed, and the gate oxide layer fills the groove and covers the hard mask layer; removing the gate oxide layer on the hard mask layer by adopting a chemical mechanical polishing process; and finally, removing the hard mask layer by adopting a wet etching process, wherein the gate oxide layer in the groove forms the gate oxide layer of the high-voltage device region. According to the invention, the gate oxide layer is formed in the trench of the high-voltage device region, so that the problem that the overall height of the polysilicon gate is high due to the fact that the thickness of the gate oxide layer of the high-voltage device region is large is solved; the problem of boron loss in the substrate and the problem of beak effect of the gate oxide layer are avoided, and the process window of the whole process platform is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-voltage LDMOS device and a forming method thereof. Background Art

[0002] The process of HV LDMOS (High Voltage Lateral Double-diffused MOSFET) is relatively complex, especially GOX (Gate Oxide). Currently, most implementations use the LOCOS (Local Oxidation of Silicon) process. LOCOS process design often brings some problems. In the LOCOS process, due to the high solid solubility of boron, the boron in the substrate is absorbed into the LOCOS, resulting in a decrease in the boron concentration of the substrate, which causes the loss of boron in the substrate (B Loss) and makes it difficult to control the boron doping in the substrate (substrate B doping control). In the LOCOS process, oxygen and water vapor can not only drill downward but also laterally under the silicon nitride to react with the substrate silicon to form silicon oxide, causing the bird peak effect. The bird's beak effect of LOCOS causes the edge of the gate oxide layer to be uneven, which in turn affects the height and position of the polysilicon gate. In addition, the thickness of the gate oxide layer in the high-voltage device area is thick, which causes the overall height of the subsequent polysilicon gate to be high and difficult to control. The height of the polysilicon gate is crucial to the subsequent 28nm HV process integration. Summary of the invention

[0003] The object of the present invention is to provide a high voltage LDMOS device and a method for forming the same, so as to solve at least one of the problems of affecting the height of the polysilicon gate, causing boron loss in the substrate and the bird's beak effect when forming a gate oxide layer using a LOCOS process.

[0004] In order to solve the above technical problems, the present invention provides a method for forming a high-voltage LDMOS device, comprising:

[0005] A substrate is provided, the substrate comprising a high-voltage device region, a high-voltage well region is formed in the high-voltage device region of the substrate, at least two drift regions are formed in the high-voltage well region, a hard mask layer is formed on the substrate, and an opening is formed in the hard mask layer;

[0006] Performing an etching process to etch the high-voltage well region between adjacent drift regions to form a trench in the high-voltage well region, wherein the trench is an extension of the opening in the hard mask layer in the high-voltage well region;

[0007] Performing a HTO process to form a gate oxide layer, wherein the gate oxide layer fills the trench and covers the hard mask layer;

[0008] Removing the gate oxide layer on the hard mask layer by using a chemical mechanical polishing process;

[0009] The hard mask layer is removed by a wet etching process, and the gate oxide layer in the trench constitutes the gate oxide layer of the high-voltage device region.

[0010] Optionally, a top surface of the gate oxide layer in the trench is higher than an upper surface of the substrate and lower than a top surface of the hard mask layer.

[0011] Optionally, the thickness of the gate oxide layer in the trench is 1000 angstroms to 1300 angstroms.

[0012] Optionally, the hard mask layer has a thickness of 200 angstroms to 250 angstroms.

[0013] Optionally, the material of the hard mask layer is silicon nitride.

[0014] Optionally, the solution of the wet etching process is phosphoric acid.

[0015] Optionally, a high-voltage N-well region and a high-voltage P-well region are formed in the high-voltage device region of the substrate, at least two P-type drift regions are formed in the high-voltage N-well region, and at least two N-type drift regions are formed in the high-voltage P-well region;

[0016] In the etching process, the high-voltage N-well region between adjacent P-type drift regions is etched to form a first trench, and the high-voltage P-well region between adjacent N-type drift regions is etched to form a second trench.

[0017] Optionally, the substrate further includes a low voltage device area and a medium voltage device area.

[0018] Optionally, the substrate includes a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure is used to isolate the adjacent high-voltage device area, the medium-voltage device area, and the low-voltage device area, and to isolate the adjacent N-type drift area and P-type drift area in the high-voltage device area, and the second shallow trench isolation structure is located in the N-type drift area and the P-type drift area of ​​the high-voltage device area and in the medium-voltage device area and the low-voltage device area.

[0019] Based on the same inventive concept, the present invention further provides a high-voltage LDMOS device, which is manufactured using any of the above-mentioned methods for forming a high-voltage LDMOS device.

[0020] In the method for forming a high-voltage LDMOS device provided by the present invention, an etching process is first performed to etch the high-voltage well region between adjacent drift regions to form a groove in the high-voltage well region; then an HTO process is performed to form a gate oxide layer, the gate oxide layer fills the groove and covers the hard mask layer; then a chemical mechanical polishing process is used to remove the gate oxide layer on the hard mask layer; finally, a wet etching process is used to remove the hard mask layer, and the gate oxide layer in the groove constitutes the gate oxide layer of the high-voltage device region. In the method for forming a high-voltage LDMOS device provided by the present invention, the formation of a gate oxide layer in the groove of the high-voltage device region solves the problem that the thickness of the gate oxide layer in the high-voltage device region is relatively thick, thereby causing the overall height of the polysilicon gate to be relatively high, and the gate oxide layer in the high-voltage device region formed by the HTO process will not have the problem of boron loss in the substrate and the bird's beak effect of the gate oxide layer, thereby improving the process window of the overall process platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0022] Figure 1 It is a flow chart of a method for forming a high-voltage LDMOS device according to an embodiment of the present invention.

[0023] Figure 2 It is a schematic diagram of the structure of the hard mask layer after patterning according to an embodiment of the present invention.

[0024] Figure 3 It is a schematic diagram of the structure after a trench is formed in the well region of the high voltage device region in an embodiment of the present invention.

[0025] Figure 4 It is a schematic diagram of the structure after a gate oxide layer is formed in the high voltage device region of an embodiment of the present invention.

[0026] Figure 5 It is a schematic diagram of the structure after the gate oxide layer on the hard mask layer is removed according to an embodiment of the present invention.

[0027] Figure 6 It is a schematic diagram of the structure after the hard mask layer is removed according to an embodiment of the present invention.

[0028] In the attached figure:

[0029] 10-substrate; 10a-high-voltage device region; 10b-low-voltage device region; 10c-medium-voltage device region; 11-pad oxide layer; 12a-first shallow trench isolation structure; 12b-second shallow trench isolation structure; 13a-high-voltage N-well region; 13b-high-voltage P-well region; 13c-low-voltage N-well region; 13d-medium-voltage N-well region; 14a-P-type drift region; 14b-N-type drift region; 15-hard mask layer; 16-opening; 17a-first trench; 17b-second trench; 18-gate oxide layer. DETAILED DESCRIPTION

[0030] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0031] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] Figure 1 FIG. 1 is a flow chart of a method for forming a high voltage LDMOS device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a high-voltage LDMOS device, including:

[0033] Step S10, providing a substrate, the substrate comprising a high-voltage device region, a high-voltage well region formed in the high-voltage device region of the substrate, at least two drift regions formed in the high-voltage well region, a hard mask layer formed on the substrate, and an opening formed in the hard mask layer;

[0034] Step S20, performing an etching process to etch the high-voltage well region between adjacent drift regions to form a trench in the high-voltage well region, wherein the trench is an extension of the opening in the hard mask layer in the high-voltage well region;

[0035] Step S30, performing a HTO process to form a gate oxide layer, wherein the gate oxide layer fills the trench and covers the hard mask layer;

[0036] Step S40, removing the gate oxide layer on the hard mask layer by using a chemical mechanical polishing process;

[0037] Step S50, removing the hard mask layer by a wet etching process, and the gate oxide layer in the trench constitutes the gate oxide layer of the high-voltage device region.

[0038] Figure 2 It is a schematic diagram of the structure of the hard mask layer after patterning according to an embodiment of the present invention. Figure 3 It is a schematic diagram of the structure after a trench is formed in the well region of the high voltage device region in an embodiment of the present invention. Figure 4 It is a schematic diagram of the structure after a gate oxide layer is formed in the high voltage device region of an embodiment of the present invention. Figure 5 It is a schematic diagram of the structure after the gate oxide layer on the hard mask layer is removed according to an embodiment of the present invention. Figure 6 1 is a schematic diagram of the structure of an embodiment of the present invention after the hard mask layer is removed. Figures 2 to 6 The specific embodiments of the present invention are described in detail.

[0039] like Figure 2 As shown, a substrate 10 is provided. The substrate 10 can provide an operating platform for subsequent processes. It can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate. The doping type of the substrate 10 is a first type, and the first type is, for example, a P type.

[0040] Please continue to refer to Figure 2The substrate 10 includes a high-voltage device region 10a, a low-voltage device region 10b and a medium-voltage device region 10c. A high-voltage well region is formed in the high-voltage device region 10a of the substrate. The high-voltage well region includes a high-voltage N-well region 13a and a high-voltage P-well region 13b. The high-voltage N-well region 13a is used to form a high-voltage PMOS device, and the high-voltage P-well region 13b is used to form a high-voltage NMOS device. At least two drift regions are formed in the high-voltage well region. Two P-type drift regions 14a are formed in the high-voltage N-well region 13a, and two N-type drift regions 14b are formed in the high-voltage P-well region 13b. A low-voltage N-well region 13c is formed in the low-voltage device region 10b, and the low-voltage N-well region 13c is used to form a low-voltage PMOS device. A medium-voltage N-well region 13d is formed in the medium-voltage device region 10c, and the medium-voltage N-well region 13d is used to form a medium-voltage PMOS device. A pad oxide layer 11 and a hard mask layer 15 are sequentially formed on the substrate 10, and the thickness of the hard mask layer 15 is, for example, 200 angstroms to 250 angstroms. The material of the hard mask layer 15 is, for example, silicon nitride. A first shallow trench isolation structure 12a and a second shallow trench isolation structure 12b are also formed in the substrate 10. The first shallow trench isolation structure 12a is used to isolate the adjacent high-voltage device area 10a, the medium-voltage device area 10c, the low-voltage device area 10b, and the adjacent N-type drift area 14b and P-type drift area 14a in the high-voltage device area 10a. The second shallow trench isolation structure 14b is located in the N-type drift area 14b, the P-type drift area 14a, or in the medium-voltage device area 10c and the low-voltage device area 10b. An opening 16 is formed in the hard mask layer 15 , and the opening 16 penetrates the hard mask layer 15 and exposes the pad oxide layer 11 between adjacent N-type drift regions 14 b and the pad oxide layer 11 between adjacent P-type drift regions 14 a in the high voltage device region.

[0041] like Figure 3 As shown, an etching process is performed, using the hard mask layer 15 as a mask to etch the high-voltage well region between adjacent drift regions to form a groove in the high-voltage well region, wherein the groove is an extension of the opening in the hard mask layer in the high-voltage well region. Specifically, the high-voltage P well 13b between adjacent N-type drift regions 14b is etched to form a second groove 17b in the high-voltage P well 13b. The high-voltage N well 13a between adjacent P-type drift regions 14a is etched to form a first groove 17a in the high-voltage N well 13a. In this embodiment, the etching process is, for example, a dry etching process.

[0042] like Figure 4As shown, an HTO process is performed to form a gate oxide layer 18, and the gate oxide layer 18 fills the first trench 17a and the second trench 17b and covers the hard mask layer 15. The top surface of the gate oxide layer 18 in the first trench 17a and the second trench 17b is higher than the upper surface of the substrate 10 and lower than the top surface of the hard mask layer 15. The thickness of the gate oxide layer in the first trench 17a and the second trench 17b is, for example, 1000 angstroms to 1300 angstroms. This embodiment uses the gate oxide layer of the high-voltage device area formed by the HTO (High Temperature Oxidation) process, which avoids the problems of boron loss and bird's beak effect in the substrate caused by the LOCOS process, and improves the process window of the overall process platform.

[0043] like Figure 5 As shown, the gate oxide layer 18 on the hard mask layer 15 is removed by a chemical mechanical polishing process.

[0044] like Figure 6 As shown, a wet etching process is used to remove the hard mask layer 15, and the gate oxide layer 18 in the first trench 17a and the second trench 17b constitutes the gate oxide layer of the high-voltage device area. Since the hard mask layer 15 is silicon nitride, the solution of the wet etching process is phosphoric acid. The etching selectivity of phosphoric acid to silicon nitride is much greater than the etching selectivity of phosphoric acid to silicon oxide. Therefore, the phosphoric acid solution will not affect the thickness of the gate oxide layer 18 of the high-voltage device area when removing the hard mask layer 15. In this embodiment, the gate oxide layer of the high-voltage device area is formed in the groove in the high-voltage well area, which solves the problem that the gate oxide layer thickness of the high-voltage device area is thick, which leads to a higher overall height of the polysilicon gate.

[0045] like Figure 6As shown, the present invention also provides a high-voltage LDMOS device, which is manufactured by any of the above-mentioned methods for forming a high-voltage LDMOS device, and includes a substrate 10, wherein the substrate 10 includes a high-voltage device region 10a, a low-voltage device region 10b, and a medium-voltage device region 10c. A high-voltage well region is formed in the high-voltage device region 10a of the substrate. The high-voltage well region includes a high-voltage N-well region 13a and a high-voltage P-well region 13b, wherein the high-voltage N-well region 13a is used to form a high-voltage PMOS device, and the high-voltage P-well region 13b is used to form a high-voltage NMOS device. At least two drift regions are formed in the high-voltage well region. Two P-type drift regions 14a are formed in the high-voltage N-well region 13a, and two N-type drift regions 14b are formed in the high-voltage P-well region 13b. A low-voltage N-well region 13c is formed in the low-voltage device region 10b, and the low-voltage N-well region 13c is used to form a low-voltage PMOS device. A medium voltage N well region 13d is formed in the medium voltage device region 10c, and the medium voltage N well region 13d is used to form a medium voltage PMOS device. A pad oxide layer 11 is formed on the substrate 10. A first shallow trench isolation structure 12a and a second shallow trench isolation structure 12b are also formed in the substrate 10. The first shallow trench isolation structure 12a is used to isolate the adjacent high voltage device region 10a, the medium voltage device region 10c, the low voltage device region 10b, and the adjacent N-type drift region 14b and P-type drift region 14a in the high voltage device region 10a. The second shallow trench isolation structure 14b is located in the N-type drift region 14b, the P-type drift region 14a, or in the medium voltage device region 10c and the low voltage device region 10b. A gate oxide layer 18 of a high voltage device region is formed between adjacent N-type drift regions 14b, and a gate oxide layer 18 of a high voltage device region is formed between adjacent P-type drift regions 14a, and the top surface of the gate oxide layer 18 is slightly higher than the top surface of the pad oxide layer 11. In this embodiment, by forming a first trench 17a and a second trench 17b in the high voltage well region, and using an HTO process to form a gate oxide layer 18 in the first trench 17a and the second trench 17b, instead of forming a gate oxide layer by a LOCOS process, the problem of boron loss in the substrate and bird's beak effect and the problem of controlling the height of the polysilicon gate in the LOCOS process are avoided, thereby improving the process window of the overall process platform.

[0046] From the above, it can be seen that in the method for forming a high-voltage LDMOS device provided by an embodiment of the present invention, an etching process is first performed to etch the high-voltage well region between adjacent drift regions to form a groove in the high-voltage well region; then an HTO process is performed to form a gate oxide layer, the gate oxide layer fills the groove and covers the hard mask layer; then a chemical mechanical polishing process is used to remove the gate oxide layer on the hard mask layer; finally, a wet etching process is used to remove the hard mask layer, and the gate oxide layer in the groove constitutes the gate oxide layer of the high-voltage device region. In the method for forming a high-voltage LDMOS device provided by the present invention, the formation of a gate oxide layer in the groove of the high-voltage device region solves the problem that the thickness of the gate oxide layer in the high-voltage device region is relatively thick, which leads to a relatively high overall height of the polysilicon gate, and the gate oxide layer in the high-voltage device region formed by the HTO process will not have the problem of boron loss in the substrate and the bird's beak effect of the gate oxide layer, thereby improving the process window of the overall process platform.

[0047] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a high voltage LDMOS device, characterized in that: include: A substrate is provided, the substrate comprising a high-voltage device region, a high-voltage well region is formed in the high-voltage device region of the substrate, at least two drift regions are formed in the high-voltage well region, a hard mask layer is formed on the substrate, and an opening is formed in the hard mask layer; Performing an etching process to etch the high-voltage well region between adjacent drift regions to form a trench in the high-voltage well region, wherein the trench is an extension of the opening in the hard mask layer in the high-voltage well region; Performing a HTO process to form a gate oxide layer, wherein the gate oxide layer fills the trench and covers the hard mask layer; Removing the gate oxide layer on the hard mask layer by using a chemical mechanical polishing process; The hard mask layer is removed by a wet etching process, and the gate oxide layer in the trench constitutes the gate oxide layer of the high-voltage device region.

2. The method for forming a high-voltage LDMOS device according to claim 1, characterized in that: A top surface of the gate oxide layer in the trench is higher than an upper surface of the substrate and lower than a top surface of the hard mask layer.

3. The method for forming a high-voltage LDMOS device according to claim 1, characterized in that: The thickness of the gate oxide layer in the trench is 1000 angstroms to 1300 angstroms.

4. The method for forming a high-voltage LDMOS device according to claim 1, characterized in that: The hard mask layer has a thickness of 200 angstroms to 250 angstroms.

5. The method for forming a high-voltage LDMOS device according to claim 1, characterized in that: The material of the hard mask layer is silicon nitride.

6. The method for forming a high-voltage LDMOS device according to claim 1 or 5, characterized in that: The solution of the wet etching process is phosphoric acid.

7. The method for forming a high-voltage LDMOS device according to claim 1, characterized in that: A high-voltage N-well region and a high-voltage P-well region are formed in the high-voltage device region of the substrate, at least two P-type drift regions are formed in the high-voltage N-well region, and at least two N-type drift regions are formed in the high-voltage P-well region; In the etching process, the high-voltage N-well region between adjacent P-type drift regions is etched to form a first trench, and the high-voltage P-well region between adjacent N-type drift regions is etched to form a second trench.

8. The method for forming a high-voltage LDMOS device according to claim 7, characterized in that: The substrate also includes a low voltage device area and a medium voltage device area.

9. The method for forming a high-voltage LDMOS device according to claim 8, characterized in that: The substrate includes a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure is used to isolate the adjacent high-voltage device area, the medium-voltage device area, and the low-voltage device area, and to isolate the adjacent N-type drift area and P-type drift area in the high-voltage device area, and the second shallow trench isolation structure is located in the N-type drift area and the P-type drift area of ​​the high-voltage device area and the medium-voltage device area and the low-voltage device area.

10. A high voltage LDMOS device, characterized in that: The high-voltage LDMOS device is manufactured by the method for forming the high-voltage LDMOS device according to any one of claims 1 to 9.

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