Light emitting diode chip and preparation method thereof

Abstract

The invention provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises an epitaxial layer and a composite electrode; the composite electrode is located on one side of the epitaxial layer and comprises at least one titanium laminated layer, and the titanium laminated layer is far away from the epitaxial layer. According to the invention, the bonding wire reliability of the light-emitting diode chip can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a method for preparing the same. Background Art

[0002] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0003] In the related art, the LED chip is the main component of the LED, and the LED chip includes an epitaxial layer and an electrode. Due to the material of the electrode, the electrode itself is not transparent, so it will cause a certain degree of shading to the light emitted by the epitaxial layer. In order to reduce the shading of the electrode to the light, the size of the electrode is designed to be as small as possible.

[0004] However, due to the small size of the electrode, the structural stability of the electrode itself will be affected, resulting in reduced reliability of the welding wire. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode chip and a method for manufacturing the same, which can effectively improve the reliability of the bonding wire of the light emitting diode chip. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a light-emitting diode chip, comprising an epitaxial layer and a composite electrode;

[0007] The composite electrode is located on one side of the epitaxial layer. The composite electrode includes at least one titanium-gold stack. The titanium-gold stack is far away from the epitaxial layer.

[0008] In another implementation of the present disclosure, the light-emitting diode chip includes a titanium-gold laminate;

[0009] The titanium-gold stack includes a first titanium layer and a third gold layer stacked together.

[0010] In another implementation of the present disclosure, the thickness of the first titanium layer is The thickness of the third gold layer is

[0011] In yet another implementation of the present disclosure, the light-emitting diode chip includes two layers of titanium-gold stack;

[0012] The titanium-gold stack comprises a second titanium layer, a fourth gold layer, a first titanium layer, and a third gold layer which are stacked in sequence.

[0013] In another implementation of the present disclosure, the thickness of the second titanium layer is The thickness of the fourth gold layer is The thickness of the first titanium layer is The thickness of the third gold layer is

[0014] In another implementation of the present disclosure, the composite electrode further includes a first gold layer, a gold-germanium-nickel layer, a second gold layer, and a platinum layer stacked in sequence;

[0015] The first gold layer, the gold-germanium-nickel layer, the second gold layer, and the platinum layer are located between the epitaxial layer and the titanium-gold stack.

[0016] In another implementation of the present disclosure, the thickness of the first gold layer is The thickness of the gold-germanium-nickel layer is The thickness of the second gold layer is The thickness of the platinum layer is

[0017] In yet another implementation of the present disclosure, the epitaxial layer includes a stacked first ohmic contact layer, a first semiconductor layer, an active layer, a second semiconductor layer, and a second ohmic contact layer;

[0018] The first gold layer covers the first ohmic contact layer.

[0019] In yet another implementation of the present disclosure, the light emitting diode chip further includes a protective layer;

[0020] The protective layer covers the outside of the epitaxial layer, and the protective layer covers the interface between the epitaxial layer and the composite electrode.

[0021] On the other hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode chip, which is applicable to the light-emitting diode chip described in the above aspect, and comprises:

[0022] preparing an epitaxial layer;

[0023] A composite electrode is prepared on one side of the epitaxial layer. The composite electrode includes at least one titanium-gold stack, and the titanium-gold stack is far away from the epitaxial layer.

[0024] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0025] The light-emitting diode chip provided by the embodiment of the present disclosure includes an epitaxial layer and a composite electrode, and the composite electrode is used to guide the current to the epitaxial layer so that the epitaxial layer can generate electricity and emit light. Since the composite electrode includes at least one layer of titanium-gold laminate, the titanium-gold laminate is far away from the epitaxial layer and is used to bear the pressure during the wire bonding process. Since the structural strength of the titanium-gold laminate is relatively high, the use of the titanium-gold laminate can effectively improve the structural stability of the composite electrode, thereby improving the reliability of the wire bonding.

[0026] That is to say, the light-emitting diode provided in the embodiment of the present disclosure can effectively ensure the structural stability of the composite electrode by arranging a titanium-gold stack away from the epitaxial layer in the composite electrode, thereby improving the reliability of the bonding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic structural diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0029] Figure 2 is a schematic diagram of the structure of a composite electrode provided by an embodiment of the present disclosure;

[0030] Figure 3 is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0031] Figure 4 is a flow chart of another method for preparing a light emitting diode chip provided by an embodiment of the present disclosure;

[0032] Figure 5 is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0033] Figure 6 is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0036] Fig. 9 is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0037] Fig.10 It is a schematic diagram of the preparation process of the light-emitting diode chip provided in the embodiment of the present disclosure.

[0038] The symbols in the figure mean the following:

[0039] 1. Epitaxial layer;

[0040] 11. first ohmic contact layer; 12. first semiconductor layer; 121. roughened region; 13. active layer; 14. second semiconductor layer; 15. second ohmic contact layer; 17. cut-off layer; 18. dielectric layer; 19. mirror reflection layer; 110. bonding layer;

[0041] 2. Composite electrode;

[0042] 21, first gold layer; 22, gold-germanium-nickel layer; 23, second gold layer; 24, platinum layer; 25, titanium-gold stack; 251, first titanium layer; 252, third gold layer; 253, second titanium layer; 254, fourth gold layer;

[0043] 4. Protective layer;

[0044] 5. Substrate;

[0045] 6. Substrate;

[0046] 7. Back electrode.

[0047] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0049] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0050] In the related art, the light-emitting diode chip is the main component of the light-emitting diode, and the light-emitting diode chip includes an epitaxial layer and an electrode. The brightness of the light-emitting diode chip is an important indicator to measure whether the light-emitting diode is excellent. In order to improve the brightness of the light-emitting diode chip, the epitaxial layer is usually optimized. However, with the advancement of technology, the optimization of the epitaxial layer has reached a bottleneck, and a large cost is required to achieve a small improvement. For the electrode, due to the material of the electrode, the electrode itself is not light-transmissive, so it will cause a certain degree of obstruction to the light emitted by the epitaxial layer, resulting in the brightness of the light-emitting diode chip being affected. In order to reduce the blocking of light by the electrode, the size of the electrode will be designed to be as small as possible.

[0051] However, due to the small size of the electrode, the structural stability of the electrode itself will be affected, resulting in reduced reliability of the welding wire.

[0052] In order to solve the above problems, the present disclosure provides a light emitting diode chip. Figure 1 A schematic diagram of the structure of a light emitting diode chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 The light emitting diode chip includes: an epitaxial layer 1 and a composite electrode 2 , wherein the composite electrode 2 is located on one side of the epitaxial layer 1 .

[0053] Figure 2 is a schematic diagram of the structure of the composite electrode 2, combined with Figure 2 In this embodiment, the composite electrode 2 includes at least one titanium-gold laminate 25 .

[0054] The light-emitting diode chip provided in the embodiment of the present disclosure includes an epitaxial layer 1 and a composite electrode 2, and the composite electrode 2 is used to guide the current to the epitaxial layer 1 so that the epitaxial layer 1 can be electrically luminous. Since the composite electrode 2 includes at least one layer of titanium-gold laminate 25, the titanium-gold laminate 25 is away from the epitaxial layer 1 and is used to bear the pressure during the wire bonding process. Since the structural strength of the titanium-gold laminate 25 is relatively high, the use of the titanium-gold laminate 25 can effectively improve the structural stability of the composite electrode 2, thereby improving the reliability of the wire bonding.

[0055] That is to say, the light-emitting diode provided in the embodiment of the present disclosure can effectively ensure the structural stability of the composite electrode 2 by disposing the titanium-gold stack 25 away from the epitaxial layer 1 in the composite electrode 2, thereby improving the reliability of the bonding wire.

[0056] In this embodiment, the number of the titanium-gold stack 25 can be one layer or two layers, which will be described below respectively.

[0057] In some examples, the light emitting diode chip includes a titanium-gold stack 25. The titanium-gold stack 25 includes a first titanium layer 251 and a third gold layer 252 stacked together. The thickness of the first titanium layer 251 is The thickness of the third gold layer 252 is

[0058] In the above implementation, since the light-emitting diode chip includes only one layer of titanium-gold laminate 25, the material cost of the light-emitting diode chip is low and the manufacturing efficiency is also high. In addition, since the thickness of the third gold layer 252 is large, the overall structural stability of the composite electrode 2 can be effectively improved, thereby improving the reliability of the bonding wire.

[0059] In this embodiment, when the light emitting diode chip includes a titanium-gold laminate 25, the thickness of the first titanium layer 251 of the titanium-gold laminate 25 is The thickness of the third gold layer 252 of the titanium-gold stack 25 is Of course, in other embodiments, the thickness of the first titanium layer 251 and the third gold layer 252 can also be selected from other values ​​within the above value range according to actual needs, and the present disclosure does not limit this.

[0060] In some other examples, the light emitting diode chip includes two layers of titanium-gold stack 25. The titanium-gold stack 25 includes a second titanium layer 253, a fourth gold layer 254, a first titanium layer 251, and a third gold layer 252 stacked in sequence. The thickness of the second titanium layer 253 is The thickness of the fourth gold layer 254 is The thickness of the first titanium layer 251 is The thickness of the third gold layer 252 is

[0061] In the above implementation, since the light-emitting diode chip includes two layers of titanium-gold laminate 25, the overall structural stability of the composite electrode 2 can be further improved, thereby improving the reliability of the wire bonding. In addition, since the second titanium layer 253 and the fourth gold layer 254 do not directly bear the pressure during wire bonding, the thickness of the second titanium layer 253 and the fourth gold layer 254 is less than the thickness of the first titanium layer 251 and the third gold layer 252. Such a design can also reduce the material cost of the light-emitting diode chip to a certain extent and improve the preparation efficiency.

[0062] In this embodiment, when the light emitting diode chip includes two layers of titanium-gold laminate 25, the thickness of the second titanium layer 253 of the titanium-gold laminate 25 is The thickness of the fourth gold layer 254 of the titanium-gold stack 25 is The thickness of the first titanium layer 251 of the titanium-gold stack 25 is The thickness of the third gold layer 252 of the titanium-gold stack 25 is Of course, in other embodiments, the thickness of the second titanium layer 253, the fourth gold layer 254, the first titanium layer 251, and the third gold layer 252 can also be selected from other values ​​within the above value range according to actual needs, and the present disclosure does not limit this.

[0063] The light-emitting diode chips in the related technology were used as the first experimental group, the light-emitting diode chips in the embodiment of the present invention (having one layer of titanium-gold laminate 25) were used as the second experimental group, and the light-emitting diode chips in the embodiment of the present invention (having two layers of titanium-gold laminate 25) were used as the third experimental group. Wire bonding comparison experiments were carried out respectively, and the test results shown in Table 1 were obtained.

[0064]

[0065] Table 1

[0066] From the data shown in Table 1, it can be seen that the abnormality ratio of the bonding wire of the LED chip in the embodiment of the present disclosure is significantly lower than that of the LED chip in the related art. In addition, the abnormality ratio of the bonding wire of the LED chip with two layers of titanium-gold laminate 25 is significantly lower than that of the LED chip with one layer of titanium-gold laminate 25.

[0067] See again Figure 1 In this embodiment, the composite electrode 2 further includes a first gold layer 21, a gold-germanium-nickel layer 22, a second gold layer 23, and a platinum layer 24 stacked in sequence. The first gold layer 21, the gold-germanium-nickel layer 22, the second gold layer 23, and the platinum layer 24 are located between the epitaxial layer 1 and the titanium-gold stack 25.

[0068] In the above implementation, by sequentially stacking the first gold layer 21, the gold-germanium-nickel layer 22, the second gold layer 23, and the platinum layer 24, the composite electrode 2 can be guaranteed to have good electrical conductivity to ensure the light efficiency of the light-emitting diode chip.

[0069] Exemplarily, the thickness of the first gold layer 21 is The thickness of the gold-germanium-nickel layer 22 is The thickness of the second gold layer 23 is The thickness of the platinum layer 24 is

[0070] In the above implementation, the thickness of the first gold layer 21, the gold-germanium-nickel layer 22, the second gold layer 23, and the platinum layer 24 are designed in this way. On the one hand, the functionality of the first gold layer 21, the gold-germanium-nickel layer 22, the second gold layer 23, and the platinum layer 24, that is, the conductive performance and structural stability, can be ensured, and on the other hand, material waste can be avoided and preparation efficiency can be ensured.

[0071] In this embodiment, the thickness of the first gold layer 21 is The thickness of the gold-germanium-nickel layer 22 is The thickness of the second gold layer 23 is The thickness of the platinum layer 24 is Of course, in other embodiments, the thicknesses of the first gold layer 21, the gold-germanium-nickel layer 22, the second gold layer 23, and the platinum layer 24 can also be selected from other values ​​within the above range according to actual needs, and the present disclosure does not limit this.

[0072] See again Figure 1 In this embodiment, the epitaxial layer 1 includes a stacked first ohmic contact layer 11 , a first semiconductor layer 12 , an active layer 13 , a second semiconductor layer 14 , and a second ohmic contact layer 15 . The first gold layer 21 covers the first ohmic contact layer 11 .

[0073] In the above implementation, the first semiconductor layer 12 has a first conductivity type, and the second semiconductor layer 14 has a second conductivity type different from the first conductivity type. Energy transition occurs between the first semiconductor layer 12 and the second semiconductor layer 14, so that the active layer 13 emits light. The first ohmic contact layer 11 is located on the side of the first semiconductor layer 12 facing away from the active layer 13, and is used to achieve ohmic contact of the first semiconductor layer 12. The second ohmic contact layer 15 is located on the side of the second semiconductor layer 14 facing away from the active layer 13, and is used to achieve ohmic contact of the second semiconductor layer 14. The first gold layer 21 covers the outside of the first ohmic contact layer 11, which can effectively ensure the ohmic contact reliability between the first gold layer 21 and the first ohmic contact layer 11, that is, to ensure the ohmic contact reliability between the composite electrode 2 and the epitaxial layer.

[0074] Exemplarily, the first semiconductor layer 12 is an N-type aluminum gallium indium phosphide roughening layer, the active layer 13 is a quantum well layer, and the second semiconductor layer 14 is a P-type gallium phosphide current spreading layer.

[0075] In this embodiment, a surface of the first semiconductor layer 12 facing away from the active layer 13 has a roughened region 121 .

[0076] In the above implementation, the surface of the first semiconductor layer 12 facing away from the active layer 13 is roughened so that the active layer 13 can reduce the total reflection of light at the first semiconductor layer 12 after emitting light, thereby increasing the brightness of the LED chip.

[0077] Exemplarily, the first semiconductor layer 12 in the roughened region 121 has a regular or irregular uneven structure, thereby reducing the total reflection of light in the first semiconductor layer 12 .

[0078] In this embodiment, the light emitting diode chip further includes a protective layer 4 , which covers the outside of the epitaxial layer 1 , and the protective layer 4 covers the interface between the epitaxial layer 1 and the composite electrode 2 .

[0079] In the above implementation, a protective layer 4 is covered on the epitaxial layer 1, and the epitaxial layer 1 can be protected, especially insulated, by the protective layer 4. In addition, since the protective layer 4 covers the junction between the epitaxial layer 1 and the composite electrode 2, the protective layer 4 can play a certain supporting role on the connection between the composite electrode 2 and the epitaxial layer 1, which is beneficial to improve the stability of the composite electrode 2.

[0080] Exemplarily, the protection layer 4 is a silicon nitride layer.

[0081] Continue to see Figure 1 In this embodiment, the light emitting diode chip further includes a dielectric layer 18 , a mirror reflection layer 19 , a bonding layer 110 , a substrate 6 and a back electrode 7 .

[0082] The dielectric layer 18 is a silicon oxide layer, and is located on the side of the second ohmic contact layer 15 that is opposite to the second semiconductor layer 14. The mirror reflection layer 19 is a gold-zinc alloy layer, and is located on the side of the dielectric layer 18 that is opposite to the second ohmic layer. The bonding layer 110 is a gold layer, and is located on the side of the mirror reflection layer 19 that is opposite to the dielectric layer 18. The substrate 6 is a silicon wafer, and is located on the side of the bonding layer 110 that is opposite to the mirror reflection layer 19. The back electrode 7 is located on the side of the substrate 6 that is opposite to the bonding layer 110.

[0083] Exemplarily, a conductive hole pattern is provided on the dielectric layer 18 , and the mirror reflection layer 19 penetrates the conductive hole of the dielectric layer 18 and is electrically connected to the second ohmic contact layer 15 .

[0084] Figure 3 A flowchart of a method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 3 In this embodiment, the preparation method includes:

[0085] Step 301: Prepare an epitaxial layer 1.

[0086] Step 302 : preparing a composite electrode 2 on one side of the epitaxial layer 1 , wherein the composite electrode 2 includes at least one titanium-gold stack 25 , and the titanium-gold stack 25 is far away from the epitaxial layer 1 .

[0087] The preparation method provided by the embodiment of the present disclosure is used to prepare a light-emitting diode chip, including an epitaxial layer 1 and a composite electrode 2. Since the composite electrode 2 includes at least one layer of titanium-gold laminate 25, the titanium-gold laminate 25 is away from the epitaxial layer 1 and is used to bear the pressure during the wire bonding process. Since the titanium-gold laminate 25 has a high structural strength, the use of the titanium-gold laminate 25 can effectively improve the structural stability of the composite electrode 2, thereby improving the reliability of the wire bonding.

[0088] That is to say, by preparing the titanium-gold laminate 25 in the composite electrode 2 and the titanium-gold laminate 25 being far away from the epitaxial layer 1 , the structural stability of the composite electrode 2 can be effectively ensured, thereby improving the reliability of the bonding wire.

[0089] Figure 4 A flowchart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 4 In this embodiment, the preparation method includes:

[0090] Step 401: Provide a substrate 5.

[0091] Exemplarily, the substrate 5 is a gallium arsenide substrate, and the substrate 5 provides a growth foundation for the subsequent growth of the epitaxial layer 1 .

[0092] Step 402 : growing an epitaxial layer 1 on one side of the substrate 5 .

[0093] Exemplarily, in step 402, a cut-off layer 17, a first ohmic contact layer 11, a first semiconductor layer 12, an active layer 13, a second semiconductor layer 14, a second ohmic contact layer 15 are sequentially grown on one side of the substrate 5 (see Figure 5 ).

[0094] Exemplarily, a metal-organic chemical vapor deposition (MOCVD) technique is used to sequentially grow a cutoff layer 17, a first ohmic contact layer 11, a first semiconductor layer 12, an active layer 13, a second semiconductor layer 14, and a second ohmic contact layer 15. The first semiconductor layer 12 has a first conductivity type, and the second semiconductor layer 14 has a second conductivity type different from the first conductivity type. Energy transition occurs between the first semiconductor layer 12 and the second semiconductor layer 14, and the active layer 13 emits light.

[0095] Exemplarily, the first semiconductor layer 12 is an N-type aluminum gallium indium phosphide roughening layer, the active layer 13 is a quantum well layer, and the second semiconductor layer 14 is a P-type gallium phosphide current spreading layer.

[0096] Step 403: Deposit a dielectric layer 18 on the side of the second ohmic contact layer 15 facing away from the second semiconductor layer 14, and form a conductive hole pattern by photolithography (see Figure 6 ).

[0097] Exemplarily, the dielectric layer 18 is silicon oxide, and a conductive hole pattern is fabricated on the dielectric layer 18 by wet etching using BOE (Buffered Oxide Etch).

[0098] Step 404: evaporate a mirror reflection layer 19 on the side of the dielectric layer 18 facing away from the second ohmic contact layer 15, and anneal.

[0099] Exemplarily, the mirror reflection layer 19 is a gold-zinc alloy layer. Through step 404 , ohmic contact can be achieved between the mirror reflection layer 19 and the second semiconductor layer 14 through the second ohmic contact layer 15 .

[0100] Step 405 : evaporating a bonding layer 110 on the side of the mirror reflection layer 19 facing away from the dielectric layer 18 .

[0101] Exemplarily, the bonding layer 110 is a gold layer, which is used for bonding with the substrate 6 in step 406 .

[0102] Step 406: Provide a substrate 6, bond the bonding layer 110 on the substrate 6 to the bonding layer 110 on the mirror reflection layer 19, and remove the substrate 5 and the cut-off layer 17, so that the first ohmic contact layer 11 is exposed (see Figure 7 ).

[0103] Exemplarily, the substrate 6 is a silicon wafer, and one side of the substrate 6 has a bonding layer 110 made of the same material as the bonding layer 110 on the mirror reflection layer 19 , thereby achieving bonding between the two bonding layers 110 .

[0104] Step 407: Etch the first ohmic contact layer 11 so that the first semiconductor layer 12 is exposed (see Figure 8 ).

[0105] Step 408: On one side of the epitaxial layer 1, a first gold layer 21, a gold-germanium-nickel layer 22, a second gold layer 23, a platinum layer 24 and at least one titanium-gold stack 25 are sequentially prepared to obtain a composite electrode 2 (see Figure 8 ).

[0106] Exemplarily, step 408 includes:

[0107] First, a gold evaporation source, a gold-germanium-nickel evaporation source, a platinum evaporation source, and a titanium evaporation source are placed in the evaporation machine.

[0108] Next, evacuate the vapor deposition machine to 3*10 -4 Pa.

[0109] Then, a first gold layer 21 , a gold-germanium-nickel layer 22 , a second gold layer 23 , a platinum layer 24 and at least one titanium-gold stack 25 are obtained by sequential evaporation.

[0110] Step 409: Set the temperature of the annealing furnace to 380° C. and perform annealing in a N 2 atmosphere for 12 minutes.

[0111] In the above implementation, annealing is performed so that a good ohmic contact can be formed between the first metal layer and the first ohmic contact layer 11 to ensure the reliability of the light emitting diode chip.

[0112] Step 410: Making cutting paths.

[0113] Exemplarily, the epitaxial layer 1 is channel-cut by photolithography and ICP (Inductively Coupled Plasm) processes, so as to form a plurality of relatively independent core particles, and the second semiconductor layer 14 of each core particle is separated.

[0114] Step 411: Roughen the surface of the first semiconductor layer 12 facing away from the active layer 13 to form a roughened region 121 (see Fig. 9 ).

[0115] Exemplarily, by roughening the surface of the first semiconductor layer 12 facing away from the active layer 13 through photolithography and wet etching processes, the total reflection of light at the first semiconductor layer 12 can be reduced, thereby increasing the brightness of the light emitting diode chip.

[0116] Step 412: Prepare a protective layer 4 (see Fig.10 ).

[0117] Exemplarily, the protective layer 4 is deposited on the side of the first semiconductor layer 12 facing away from the active layer 13 and in the channel by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

[0118] Exemplarily, the protection layer 4 is a silicon nitride layer.

[0119] Step 413: Form a back electrode 7 by evaporation on the side of the substrate 6 facing away from the bonding layer 110 (see Figure 1 ).

[0120] Exemplarily, after the back electrode 7 is formed by evaporation, it is placed in an annealing furnace chamber at 380° C. and annealed in a N 2 atmosphere for 10 minutes, so that a reliable ohmic contact is formed between the back electrode 7 and the substrate 6 .

[0121] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0122] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: It comprises an epitaxial layer (1) and a composite electrode (2); The composite electrode (2) is located on one side of the epitaxial layer (1), and the composite electrode (2) comprises at least one layer of titanium-gold stack (25), and the titanium-gold stack (25) is far away from the epitaxial layer (1).

2. The light emitting diode chip according to claim 1, characterized in that: The light-emitting diode chip comprises a titanium-gold laminate (25); The titanium-gold stack (25) comprises a first titanium layer (251) and a third gold layer (252) stacked together.

3. The light emitting diode chip according to claim 2, characterized in that: The thickness of the first titanium layer (251) is The thickness of the third gold layer (252) is 4. The light emitting diode chip according to claim 1, characterized in that: The light-emitting diode chip comprises two layers of titanium-gold stacking (25); The titanium-gold stack (25) comprises a second titanium layer (253), a fourth gold layer (254), a first titanium layer (251), and a third gold layer (252) which are stacked in sequence.

5. The light emitting diode chip according to claim 4, characterized in that: The thickness of the second titanium layer (253) is The thickness of the fourth gold layer (254) is The thickness of the first titanium layer (251) is The thickness of the third gold layer (252) is 6. The light emitting diode chip according to claim 1, characterized in that: The composite electrode (2) further comprises a first gold layer (21), a gold-germanium-nickel layer (22), a second gold layer (23), and a platinum layer (24) which are stacked in sequence; The first gold layer (21), the gold-germanium-nickel layer (22), the second gold layer (23), and the platinum layer (24) are located between the epitaxial layer (1) and the titanium-gold stack (25).

7. The light emitting diode chip according to claim 6, characterized in that: The thickness of the first gold layer (21) is The thickness of the gold-germanium-nickel layer (22) is The thickness of the second gold layer (23) is The thickness of the platinum layer (24) is 8. The light emitting diode chip according to claim 6, characterized in that: The epitaxial layer (1) comprises a first ohmic contact layer (11), a first semiconductor layer (12), an active layer (13), a second semiconductor layer (14) and a second ohmic contact layer (15) which are stacked; The first gold layer (21) covers the outside of the first ohmic contact layer (11).

9. The light emitting diode chip according to claim 1, characterized in that: The light-emitting diode chip further comprises a protective layer (4); The protective layer (4) covers the outside of the epitaxial layer (1), and the protective layer (4) covers the interface between the epitaxial layer (1) and the composite electrode (2).

10. A method for preparing a light emitting diode chip, characterized in that: The preparation method is applicable to preparing the light-emitting diode chip according to claim 1, and the preparation method comprises: Preparing an epitaxial layer (1); A composite electrode (2) is prepared on one side of the epitaxial layer (1), wherein the composite electrode (2) comprises at least one layer of titanium-gold laminate (25), and the titanium-gold laminate (25) is far away from the epitaxial layer (1).

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