Processing method for final polishing process and polished wafer

Abstract

The invention relates to a processing method for a final polishing process and a polished wafer. The treatment method for the final polishing process comprises the following steps: carrying out first polishing on a wafer by using a first polishing solution; carrying out second polishing on the wafer subjected to the first polishing by using a second polishing solution; and a third polishing solution is used for conducting third polishing on the wafer subjected to second polishing, the first polishing solution and the second polishing solution are both added with the alkaline additive, and the third polishing solution is not added with the alkaline additive. Through the treatment method for the final polishing process, formation of differential interference contrast defects can be reduced while preorder process damage removal and mirror surface repair are carried out on the surface of the wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a processing method for a final polishing process and a polished wafer. Background Art

[0002] In the production of wafers, usually, a crystal rod is first pulled out using a crystal pulling furnace, and then the crystal rod is cut into multiple ingots. Each ingot is then cut into thin slices of initial wafers by methods such as multi-wire cutting. The initial wafers are then subjected to polishing, epitaxy and other processes to obtain finished wafers.

[0003] In the wafer polishing process, usually, the process is carried out in the order of double-sided polishing, primary cleaning, edge polishing, secondary cleaning, and final polishing. Final polishing is a key step in wafer surface treatment. Its purpose is to remove the damage layer and surface unevenness that may be introduced in the previous process, and ensure that the wafer surface reaches a high standard of flatness and cleanliness. The quality of the wafer surface after the final polishing process directly determines the quality of the wafer.

[0004] However, the final polishing process mainly removes material by applying physical pressure to the wafer surface using abrasive particles in the polishing pad and polishing liquid. This material removal method has a low rate and is prone to cause defects on the wafer surface, which will adversely affect the surface quality and performance of the wafer. Summary of the invention

[0005] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0006] The purpose of the present disclosure is to provide a processing method for a final polishing process, which can reduce defects caused on the wafer surface while removing damage from previous processes and performing mirror-finish repair on the wafer surface.

[0007] In order to achieve the above object, according to a first aspect of the present disclosure, a processing method for a final polishing process is provided, comprising: Performing a first polishing on the wafer using a first polishing liquid; Performing a second polishing on the first-polished wafer using a second polishing liquid; and The wafer that has undergone the second polishing is subjected to a third polishing using a third polishing liquid, The first polishing liquid and the second polishing liquid both include alkaline additives, and the third polishing liquid does not include alkaline additives.

[0008] In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing liquid may be greater than the volume ratio of the alkaline additive to the solvent in the second polishing liquid.

[0009] In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing liquid may be in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing liquid may be in the range of 1:5000 to 1:2500.

[0010] In some embodiments, the basic additive may be an inorganic base or an organic base.

[0011] In some embodiments, the alkaline additive may include KOH, NaOH, or NH 4 OH.

[0012] In some embodiments, the first polishing may be performed at a first target removal thickness, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

[0013] In some embodiments, the ratio of the first target removal thickness, the second target removal thickness, and the third target removal thickness may be 6:3:1.

[0014] In some embodiments, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness may be greater than 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

[0015] According to a second aspect of the present disclosure, a polished wafer is provided, which is obtained according to the processing method for a final polishing process according to the first aspect of the present disclosure, and the number of DIC defects with a size of more than 5 nm on the polished wafer is less than 5.

[0016] In some embodiments, the number of DIC defects with a size of 5 nm or more on the polished wafer may be less than 3.

[0017] According to the above technical solution, the removal of the previous process damaged layer and mirror repair of the wafer surface can be gradually completed by three polishing steps. In addition, the first polishing step and the second polishing step remove the wafer surface material at an increased material removal rate by combining chemical corrosion and physical grinding, which effectively shortens the time for clearing the crystal defect area on the wafer surface, helps to avoid the gradual enlargement of the defect area and the tiny defects in the defect area due to physical grinding, thereby reducing the risk of forming DIC defects and reducing the formation of DIC defects on the wafer surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The features and advantages of the embodiments of the present disclosure will become more easily understood through the following description with reference to the accompanying drawings. The drawings are not drawn to scale and some features may be enlarged or reduced to show details of specific components. In the drawings: Figure 1 It is a schematic diagram of a final polishing device according to the related art.

[0019] Figure 2 is a schematic cross-sectional view of a polished wafer obtained by using a processing method for a final polishing process according to the related art.

[0020] Figure 3 The schematic morphological features of a single DIC defect formed on a polished wafer are shown as an example.

[0021] Figure 4 is a flow chart of a processing method for a final polishing process according to an embodiment of the present disclosure.

[0022] Figure 5 The figure is a comparison diagram of DIC defect test results of a series of polished wafers obtained by using the processing method for the final polishing process of the related art and a series of polished wafers obtained by using the processing method for the final polishing process according to the embodiment of the present disclosure.

[0023] Figure 6 Another comparison diagram of DIC defect test results of a series of polished wafers obtained by using the processing method for the final polishing process of the related art and a series of polished wafers obtained by using the processing method for the final polishing process according to an embodiment of the present disclosure.

[0024] Figure 7 FIG. 1 is a schematic diagram showing the distribution of DIC defects on the surface of a polished wafer obtained by using a treatment method for a final polishing process in the related art.

[0025] Figure 8 FIG. 1 is a schematic diagram showing the distribution of DIC defects on the surface of a polished wafer obtained by using the treatment method for a final polishing process according to an embodiment of the present disclosure.

[0026] Fig. 9 is a schematic diagram of an exemplary final polishing apparatus for performing a processing method for a final polishing process according to an embodiment of the present disclosure.

[0027] In the drawings, the same or corresponding technical features or components are represented by the same or corresponding reference numerals. DETAILED DESCRIPTION

[0028] The present disclosure is described in detail below with reference to the accompanying drawings by means of exemplary embodiments. It should be noted that the following detailed description of the present disclosure is only for illustrative purposes and is by no means a limitation of the present disclosure.

[0029] As mentioned earlier, before obtaining the finished wafer, it generally needs to go through manufacturing processes such as cutting, slicing, edge grinding, corrosive etching, double-side grinding, double-side polishing, edge polishing and final polishing.

[0030] Among the various polishing processes in the above-mentioned manufacturing process, the double-sided polishing process is usually carried out at an earlier stage in the order of implementation. Its purpose is to remove the damage layer formed in the previous processes such as cutting and double-sided grinding, and to improve the overall geometric properties of the wafer, such as flatness and thickness uniformity, mainly to make the wafer meet the basic physical properties.

[0031] The double-sided polishing process is performed using a double-sided polishing device. The double-sided polishing device generally includes an upper platen and a lower platen that are arranged relatively to each other, and a carrier plate disposed between the upper platen and the lower platen. The carrier plate is used to carry the wafer to be polished. The upper platen and the lower platen include an upper polishing pad and a lower polishing pad, respectively. In the double-sided polishing process, the upper platen and the lower platen simultaneously apply pressure to the wafer carried in the carrier plate, so that the upper polishing pad and the lower polishing pad are in contact with the front and back sides of the wafer, respectively, so as to complete the double-sided polishing of the wafer through the movement of the carrier plate relative to the upper platen and the lower platen.

[0032] The edge polishing process is mainly performed on the edge of the wafer, which is usually located after the double-sided polishing process. The purpose is to improve the flatness of the wafer edge and remove edge defects such as protrusions and micro cracks.

[0033] The edge polishing process is performed using an edge polishing device. Generally, the edge polishing device includes a rotatable support plate and an edge polishing head. The support plate is used to carry the wafer to be edge polished and can drive the wafer to rotate about its central axis. During the edge polishing process, the edge polishing head can contact the edge of the rotating wafer to achieve polishing of the wafer edge.

[0034] At the final stage of various polishing processes in the above manufacturing process, the wafer that has undergone the above polishing processes such as double-sided polishing process and edge polishing process will finally undergo the final polishing process. The final polishing process is usually performed on the front side of the wafer to remove the damage formed in the previous processes including the previous polishing process and to achieve global flatness of the wafer surface. It is a fine processing to make the wafer surface meet the quality standards required for subsequent device manufacturing (such as photolithography process).

[0035] The final polishing process must be performed with the aid of final polishing equipment capable of performing this fine processing.

[0036] Figure 1 An exemplary final polishing device 1 according to the related art is shown. Figure 1As shown, the final polishing device 1 includes a polishing head 2, a polishing table 3, and a polishing liquid supply pipeline 4. The polishing head 2 holds a wafer to be polished at its lower portion. The polishing table 3 is provided with a polishing pad 5 on its upper surface. The polishing liquid supply pipeline 4 is used to provide the polishing liquid to the polishing pad 5. During the polishing process, the wafer held by the polishing head 2 is pressed against the polishing pad 5 to achieve the final polishing of the wafer by means of the relative rotation of the polishing pad 5 and the wafer.

[0037] Generally, the final polishing process includes a rough polishing process and a fine polishing process. In the rough polishing process, a polishing liquid with a larger abrasive particle size is used to remove micro-damages of the front layer. In the fine polishing process, a polishing liquid with a smaller abrasive particle size is used to clean and mirror the wafer surface to achieve the required flatness and smoothness of the wafer surface.

[0038] In the final polishing process of the related art, the polishing liquid used for final polishing only removes the pre-damaged layer on the wafer surface by means of physical grinding of abrasive particles. In this case, as mentioned above, different degrees of surface polishing effects are generally obtained by selecting abrasive particles of appropriate sizes. However, this pure physical grinding polishing process is prone to cause defects on the wafer surface.

[0039] In particular, for heavily doped wafers, the wafer has a higher hardness due to its high oxygen content. At the same time, the center of the wafer may be filled with larger crystal-origin particles (COPs). Figure 2 The polished wafer W shown in FIG is indicated by A. Therefore, after the wafer is processed by double-side grinding, low temperature oxidation (LTO) and other previous processes, the area where COPs are gathered appears as a crystal defect area.

[0040] The inventors noticed that due to the high surface hardness of heavily doped wafers, and the low material removal rate on the wafer surface during surface polishing using physical grinding, it takes a considerable amount of time to remove the crystal defect area. This physical grinding process will gradually enlarge the defect area, causing the small crystal defects in the defect area to be enlarged, thereby forming differential interference contrast (DIC) defects. Figure 2 The polished wafer W shown in FIG. is indicated by B. It is understood that Figure 2 The drawings are not to scale, and for ease of understanding, the COP and DIC defects on the polished wafer W are schematically enlarged.

[0041] It should be understood that, in the present disclosure, a DIC defect refers to a step-shaped defect observed by a differential interference contrast technique, such as a differential interference contrast microscope. Figure 3 The schematic morphological features of a single DIC defect are shown as an example. As shown in the figure, from the overall morphology, the DIC defect is generally a raised step-shaped defect or a sunken pit-shaped defect. In addition, Figure 3 The horizontal span and the vertical span of the DIC defect are shown, wherein the horizontal direction refers to the direction extending along the plane where the wafer surface is located, and the vertical direction is the direction perpendicular to the plane where the wafer surface is located.

[0042] Reference Figure 3 , the span of the DIC defect in the vertical direction, i.e., the maximum height difference H, is used to characterize the size of the DIC defect. That is, in the present disclosure, the size of the DIC defect refers to the height difference between the highest point and the lowest point of the DIC defect. In other words, the size of the DIC defect is the height difference or height difference between the highest point and the lowest point on the wafer surface where the DIC defect is located, and its unit is nm.

[0043] It should be noted that Figure 3 The DIC defect in the figure is exemplary and is only used to schematically illustrate the basic morphological characteristics of the DIC defect. It does not mean that the DIC defect is related to Figure 3 The morphology shown in is completely consistent.

[0044] DIC defects are an important indicator that affects wafer quality and device performance. Too many DIC defects will not only reduce the yield and reliability of wafer products, but also limit the application of wafer products in high-end technology fields.

[0045] Therefore, it is desirable to propose a processing method for a final polishing process, which can reduce the formation of DIC defects while removing the damage of the previous process and repairing the mirror surface of the wafer surface.

[0046] Reference Figure 4 According to an embodiment of the present disclosure, a processing method for a final polishing process is provided, comprising: S100: performing a first polishing on the wafer using a first polishing liquid; S200: performing a second polishing on the wafer that has undergone the first polishing using a second polishing liquid; and S300: performing a third polishing on the wafer that has undergone the second polishing using a third polishing liquid, The first polishing liquid and the second polishing liquid are both added with alkaline additives, and the third polishing liquid is not added with alkaline additives.

[0047] It is understood that the first polishing liquid, the second polishing liquid and the third polishing liquid are all solid-liquid mixtures containing abrasive particles. The abrasive particles are used to physically grind the surface of the wafer to remove surface materials. In addition, the first polishing liquid, the second polishing liquid and the third polishing liquid all contain solvents for dispersing or dissolving the abrasive particles and other additives such as chemical additives.

[0048] The above steps are described in detail below.

[0049] Step S100 is also called a first polishing step, and is used to remove a previous process damaged layer on the surface of the wafer.

[0050] Here, the previous process damaged layer on the surface of the wafer refers to the area where damage introduced by the previous processing process (such as double-side grinding, etc.) before the wafer starts to undergo the first polishing, such as mechanical damage such as micro scratches or cracks.

[0051] In the case where an alkaline additive is added to the first polishing liquid, the first polishing liquid is alkaline, so that the first polishing can combine the physical grinding action of the abrasive particles and the OH - The chemical etching effect generated provides a very large material removal rate, thereby quickly reducing the thickness of the damaged layer of the previous process, shortening the time for the defects in the defective area to be enlarged into DIC defects, thereby reducing the risk of forming DIC defects.

[0052] In particular, in the first polishing step, the tip stress principle of chemical etching can also be used to quickly remove severe damage. - The wafer can be etched quickly along the crystal lattice, thereby further reducing the risk of enlarging tiny crystal defects into DIC defects.

[0053] Step S200 is also called the second polishing step, which is used to remove the damage on the surface of the wafer caused by physical grinding and chemical corrosion in the first polishing step. Alkaline additives are added to the second polishing liquid to obtain a relatively high material removal rate through the combination of material grinding and chemical corrosion.

[0054] Step S300 is also called the third polishing step, which is used to repair the damage on the surface of the wafer caused by the physical grinding and chemical corrosion in the second polishing, so as to make the surface of the wafer mirror-finished and obtain a highly flat and smooth surface.

[0055] The third polishing liquid does not include alkaline additives to avoid excessive chemical corrosion on the wafer surface, thereby avoiding deterioration of the flatness of the wafer surface and ensuring the final quality of the wafer surface.

[0056] Through the above scheme, the removal of the previous process damaged layer and mirror repair of the wafer surface are gradually completed by three polishing steps. In addition, the first polishing step and the second polishing step thin the wafer at an increased material removal rate by combining chemical corrosion and physical grinding, effectively shortening the time to remove the crystal defect area on the wafer surface, helping to avoid the gradual enlargement of the defect area and the tiny defects in the defect area due to long grinding time, thereby reducing the risk of forming DIC defects.

[0057] Through the above scheme, the formation of DIC defects can be reduced while removing the damage caused by the previous process and repairing the mirror surface on the wafer surface, which is conducive to obtaining a polished wafer with a surface damage layer, high mirror surface and reduced DIC defects.

[0058] According to an embodiment of the present disclosure, a polished wafer is also provided, which is obtained according to the processing method for the final polishing process of the embodiment of the present disclosure. The processing method for the final polishing process according to the embodiment of the present disclosure includes the processing method for the final polishing process according to any of the above-mentioned embodiments, and it can be understood that it also includes the processing method for the final polishing process of any of the embodiments mentioned below.

[0059] The number of DIC defects having a size of 5 nm or more (ie, greater than or equal to 5 nm) on the polished wafer thus obtained is less than 5.

[0060] Furthermore, the number of DIC defects with a size of 5 nm or more on the polished wafer thus obtained may be less than 3.

[0061] Specifically, the polished wafer is obtained by performing a first polish on the wafer using a first polishing liquid, performing a second polish on the wafer that has undergone the first polishing using a second polishing liquid, and performing a third polish on the wafer that has undergone the second polishing using a third polishing liquid, wherein both the first polishing liquid and the second polishing liquid are added with alkaline additives, and the third polishing liquid is not added with alkaline additives.

[0062] A treatment method for a final polishing process according to the related art is used as comparative example A, and a treatment method for a final polishing process according to an embodiment of the present disclosure is used as example B. Figure 5 The statistical results of DIC defects of a series of polished wafers obtained in the case of comparative example A and a series of polished wafers obtained in the case of embodiment B are shown in a box plot, wherein the vertical axis is the number of DIC defects with a size of more than 5 nm measured on a single polished wafer.

[0063] Here, the polished wafer refers in particular to a wafer having a diameter of 300 mm or a 12-inch wafer.

[0064] like Figure 5 As shown, the average number of DIC defects with a size of more than 5 nm on the polished wafer obtained by Comparative Example A is 2806.92, and the average number of DIC defects with a size of more than 5 nm on the polished wafer obtained by Example B is 0.166667. It can be seen that the treatment method for the final polishing process according to the embodiment of the present disclosure can effectively reduce the DIC defects on the polished wafer obtained thereby.

[0065] Figure 6 The number of DIC defects with a size of 5 nm or more for each of a series of polished wafers obtained in the case of Comparative Example A and a series of polished wafers obtained in the case of Example B is shown. Figure 6 It can be seen that the number of DIC defects fluctuates over a series of polished wafers.

[0066] Depend on Figure 6 It can be seen that the number of DIC defects in a series of polished wafers obtained in Example B is generally low and basically maintained at a consistent level, which shows that the processing method for the final polishing process according to the embodiment of the present disclosure has high reliability and stability in reducing DIC defects.

[0067] In addition, if Figure 7 As shown in FIG. 1 , the number of DIC defects with a size of 5 nm or more on the surface of the polished wafer obtained from Comparative Example A is quite large and densely distributed. Figure 8 As shown in , the number of DIC defects with a size of 5 nm or more on the surface of the polished wafer obtained by Example B is extremely small. It can be seen that the surface quality of the polished wafer obtained by the treatment method for the final polishing process according to the embodiment of the present disclosure is higher.

[0068] In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing liquid may be greater than the volume ratio of the alkaline additive to the solvent in the second polishing liquid, so that the OH in the first polishing liquid - The concentration of OH in the second polishing liquid is higher than - concentration.

[0069] In this case, the first polishing step has a stronger alkali corrosion effect to achieve a relatively stronger polishing ability and a faster polishing rate, so that the thickness of the damaged layer formed by the physical effect of this step can be reduced while the damaged layer of the previous step can be quickly removed.

[0070] The corrosion effect of the second polishing step is weaker than that of the first polishing step, so that the polishing rate is relatively reduced. In order to remove the damage caused by the chemical corrosion in the first polishing step and the damage to the current layer, it is possible to avoid the deterioration of parameters such as wafer flatness caused by excessive chemical action, thereby achieving a relatively finer polishing effect than the first polishing step.

[0071] It is understood that the initial concentration of the alkaline additive added to the first polishing liquid and the initial concentration of the alkaline additive added to the second polishing liquid may be the same, for example, the initial concentration of the alkaline additive may both be 50 wt %.

[0072] For alkaline additives having the same initial concentration, the amount of the alkaline additive added to the solvent of the first polishing liquid may be greater than the amount of the alkaline additive added to the solvent of the second polishing liquid.

[0073] In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing liquid may be in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing liquid may be in the range of 1:5000 to 1:2500.

[0074] If the volume ratio of the alkaline additive to the solvent in the first polishing liquid is higher than 1:1500, the chemical reaction is too strong, which may easily lead to deterioration of wafer flatness and other qualities.

[0075] If the volume ratio of the alkaline additive to the solvent in the first polishing liquid is lower than 1:2500, the polishing rate of the first polishing process is low, which is not conducive to suppressing the generation of DIC defects and is not conducive to equipment capacity matching.

[0076] If the volume ratio of the alkaline additive to the solvent in the second polishing liquid is lower than 1:5000, the pH value of the second polishing liquid changes too little, the chemical action is insufficient, and it cannot effectively help reduce the formation of DIC defects.

[0077] In some embodiments, the basic additive may be an inorganic base.

[0078] For example, the alkaline additive may include KOH, NaOH, or NH4OH.

[0079] In some embodiments, the alkaline additive may be an organic base, such as aminomethyl propanol, quaternary ammonium salt, and the like.

[0080] In some embodiments, the first polishing may be performed at a first target removal thickness, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

[0081] In this case, the wafer surface material can be removed in a stepwise manner with a target removal amount. This not only helps to further reduce the probability of DIC defects, but also the amount to be removed in each step can be matched or adapted to the material removal rate of each polishing step, for example, a larger material removal rate matches a larger amount to be removed, thereby optimizing the polishing process and improving the overall efficiency of the final polishing process.

[0082] In some embodiments, the ratio of the first target removal thickness, the second target removal thickness, and the third target removal thickness may be 6:3:1 to better match the desired material removal rates of the three steps.

[0083] In addition, in order to ensure the stability of the process and ensure sufficient removal of damage from the previous process, in some embodiments, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness is greater than 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

[0084] It should be understood that the thickness of the front damaged layer is calculated according to the mean value, and the front layer damage will fluctuate due to process fluctuations and spare parts replacement. In actual production, the fluctuation of the front layer damage can be controlled within 20%. Based on this fluctuation range, the maximum value of the actual damage layer thickness will reach 120% of the thickness of the front damaged layer calculated according to the mean value. Combining statistical principles and the 1.5 offset sigma management habit in quality management, the maximum value of the actual damage layer thickness may reach about 150% of the thickness of the front damaged layer calculated according to the mean value. Therefore, by ensuring that the sum of the target removal thickness is greater than the possible maximum value of the actual damage layer thickness, the complete removal of the previous process damage can be ensured.

[0085] It should be noted that the damaged layer here refers to the damaged layer existing on the surface of the wafer when the wafer is to be polished or is about to undergo the first polishing. The damaged layer is the area where damage is introduced on the surface of the wafer due to the previous process before the first polishing, such as double-sided polishing.

[0086] It is understandable that the thickness of the damaged layer can be measured by selecting a suitable measurement method according to the material, processing technology and equipment conditions of the wafer, and no limitation is made here.

[0087] Fig. 9 An exemplary final polishing apparatus 10 for performing a polishing process according to an embodiment of the present disclosure is shown. Fig. 9As shown, the final polishing device 10 includes a polishing head 20, a polishing table 30, and a polishing liquid supply pipeline 40. The polishing head 20 holds the wafer to be polished with its lower surface. A polishing pad 31 for contacting the wafer is provided on the upper surface of the polishing table 30. The polishing liquid supply pipeline 40 is used to provide the polishing liquid to the polishing pad 31 so that the wafer is polished by the contact between the polishing pad 31 and the wafer.

[0088] The final polishing device 10 may include a first holding tank 50 for storing the first polishing liquid, a second holding tank 60 for storing the second polishing liquid, and a third holding tank 70 for storing the third polishing liquid. By configuring independent holding tanks, it is convenient to adjust the use order and amount of each polishing liquid according to the corresponding polishing steps, thereby improving the flexibility and adaptability of the process.

[0089] Next, a process of performing a treatment method for a final polishing process according to an embodiment of the present disclosure using the final polishing apparatus 10 will be described.

[0090] When the final polishing device 10 is used to perform final polishing on the wafer, while the wafer is adsorbed and held by the polishing head 20, first, a certain flow rate of first polishing liquid is supplied from the first holding tank 50 to the polishing pad 31 via the polishing liquid supply pipeline 40. After the polishing liquid is supplied to the polishing pad 31 and contacts the wafer, the polishing head 20 and the polishing table 30 are driven by their corresponding driving shafts to rotate relative to each other, and pressure is applied to the wafer through the polishing head 20 to complete the first polishing of the wafer.

[0091] Subsequently, similarly, a certain flow rate of the second polishing liquid is supplied from the second holding tank 60 to the polishing pad 31 via the polishing liquid supply pipeline 40 to perform the second polishing. Finally, a certain flow rate of the third polishing liquid is supplied from the third holding tank 70 to the polishing pad 31 via the polishing liquid supply pipeline 40 to perform the third polishing, thereby finally obtaining a polished wafer with the surface damage layer removed, the surface mirror-finished, and the number of DIC defects reduced.

[0092] Unless otherwise defined, technical or scientific terms used in the present disclosure shall have the common meanings understood by those skilled in the art to which the present disclosure belongs. The terms "include" and "comprising" are open ended, i.e., systems, devices, articles, compositions, preparations or methods that include elements other than those listed after such terms in a claim are still considered to fall within the scope of the claim.

[0093] Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that the present disclosure is not limited to the specific embodiments described and shown in detail herein. Various changes may be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of the present disclosure.

[0094] The features mentioned and / or shown in the above description of the exemplary embodiments of the present disclosure may be combined in the same or similar manner into one or more other embodiments, combined with features in other embodiments or substituted for corresponding features in other embodiments. The technical solutions obtained by these combinations or substitutions shall also be deemed to be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A processing method for a final polishing process, characterized in that: include: Performing a first polishing on the wafer using a first polishing liquid; Performing a second polishing on the wafer after the first polishing using a second polishing liquid; as well as Performing a third polishing on the wafer after the second polishing using a third polishing liquid, Wherein, the first polishing liquid and the second polishing liquid both include alkaline additives, and the third polishing liquid does not include alkaline additives.

2. The method for final polishing according to claim 1, characterized in that: A volume ratio of the alkaline additive to the solvent in the first polishing liquid is greater than a volume ratio of the alkaline additive to the solvent in the second polishing liquid.

3. The processing method for the final polishing process according to claim 1, characterized in that: The volume ratio of the alkaline additive to the solvent in the first polishing liquid is in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing liquid is in the range of 1:5000 to 1:2500.

4. The method for final polishing according to claim 1, characterized in that: The alkaline additive is an inorganic base or an organic base.

5. The processing method for the final polishing process according to claim 1, characterized in that: The alkaline additive includes KOH, NaOH or NH4OH.

6. The method for final polishing according to claim 1, characterized in that: The first polishing is performed at a first target removal thickness, the second polishing is performed at a second target removal thickness, and the third polishing is performed at a third target removal thickness, wherein the first target removal thickness is greater than the second target removal thickness, and the second target removal thickness is greater than the third target removal thickness.

7. The method for final polishing according to claim 6, characterized in that: The ratio of the first target removal thickness, the second target removal thickness and the third target removal thickness is 6:3:

1.

8. The method for final polishing according to claim 6, characterized in that: A sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness is greater than 150% of a thickness of a damaged layer of the wafer to be subjected to the first polishing.

9. A polished wafer, characterized in that: The polished wafer is obtained according to the processing method for the final polishing process according to any one of claims 1 to 8, and the number of DIC defects with a size of more than 5 nm on the polished wafer is less than 5.

10. The polished wafer according to claim 9, characterized in that: The number of DIC defects with a size of 5 nm or more on the polished wafer is less than 3.

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