Zero cross detection circuit and method

Abstract

The embodiment of the invention provides a zero-cross detection circuit and method, and the circuit comprises a logic driving module which enables a sampling and holding module when an upper power tube in a power output stage module is closed, and provides a first sampling clock and a second sampling clock for the sampling and holding module; the sampling and holding module is used for sampling a voltage signal of a switch node at a first sampling clock to obtain a first sampling voltage signal and obtaining a second sampling voltage signal at a second sampling clock; the self-adaptive offset comparator is used for obtaining an advanced closing amount of the lower power tube according to the second sampling voltage signal and the first sampling voltage signal, and obtaining a zero-cross detection signal according to a voltage signal of the switch node, the advanced closing amount and a power ground signal; the logic driving module closes the lower power tube based on the effective zero-cross detection signal; the power output stage module obtains output voltage through the switching process of the upper power tube and the lower power tube.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a zero-crossing detection circuit and method. Background Art

[0002] When the synchronous rectifier works in DCM (Discontinuous Conduction Mode), if the synchronous rectifier tube cannot be turned off in time when the inductor current crosses zero, it will cause current backflow. Figure 1 The figure shows the current backflow path of the synchronous BUCK circuit. Figure 2 The figure is a schematic diagram of the inductor current backflow waveform. The output capacitor will discharge to the ground through the rectifier tube, resulting in unstable output voltage, reduced chip efficiency and increased risk of damage to the rectifier tube. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a zero-crossing detection circuit and method, which acquires the voltage signal of the switch node at two sampling clocks to obtain a zero-crossing detection signal for controlling the power tube to be turned off, thereby realizing a high-precision zero-crossing detection function in different output voltage and inductance application scenarios, while improving the conversion efficiency of the chip when working in DCM and reducing the ringing of the switch node.

[0004] In order to achieve the above-mentioned purpose, the first aspect of the embodiment of the present disclosure provides a zero-crossing detection circuit, including: a logic driving module, a sampling and holding module, an adaptive offset comparator and a power output stage module. Wherein, the logic driving module is configured to enable the sampling and holding module when the upper power tube in the power output stage module is turned off, and provide the first sampling clock and the second sampling clock to the sampling and holding module; the sampling and holding module is configured to sample the voltage signal of the switch node in the power output stage module at the first sampling clock to obtain the first sampling voltage signal, and sample the voltage signal of the switch node at the second sampling clock to obtain the second sampling voltage signal; the adaptive offset comparator is configured to obtain the early closing amount of the lower power tube in the power output stage module according to the second sampling voltage signal and the first sampling voltage signal, and obtain the zero-crossing detection signal according to the voltage signal of the switch node, the early closing amount and the power ground signal in the power output stage module; the logic driving module is also configured to turn off the lower power tube in the power output stage module based on the effective zero-crossing detection signal; the power output stage module is configured to obtain the output voltage through the switching process of the upper power tube and the lower power tube.

[0005] In some embodiments of the present disclosure, the logic driving module includes: a driving circuit, an enabling circuit and a sampling clock circuit, wherein the driving circuit is configured to control the switching of the upper power tube and the lower power tube; the enabling circuit is configured to provide an enabling signal to the sampling and holding module when the upper power tube is turned off; and the sampling clock circuit is configured to provide the first sampling clock and the second sampling clock to the sampling and holding module based on the start-up signal of the lower power tube.

[0006] In some embodiments of the present disclosure, the logic driving module further includes: a noise reduction circuit, wherein the noise reduction circuit is configured to provide the voltage signal of the switch node to the adaptive offset comparator based on the shutdown signal of the upper power tube.

[0007] In some embodiments of the present disclosure, the sampling clock circuit includes: seven stages of end-to-end connected CMOS inverters, a first current source, a second current source, a third current source, a third capacitor, a fourth capacitor, a fifth capacitor, a first AND gate, and a second AND gate. Wherein, each CMOS inverter is coupled to the input end of the lower CMOS inverter through its output end, the input end of the first CMOS inverter is coupled to the input end of the start signal of the lower power tube, the first CMOS inverter includes a first transistor and a second transistor, the control electrode of the first transistor and the control electrode of the second transistor are coupled to the input end of the first CMOS inverter, and the second electrode of the first transistor and the second electrode of the second transistor are coupled to the output end of the first CMOS inverter; the second CMOS inverter includes a third transistor and a fourth transistor, the control electrode of the third transistor and the control electrode of the fourth transistor are coupled to the input end of the second CMOS inverter, and the second electrode of the third transistor and the second electrode of the fourth transistor are coupled to the output end of the second CMOS inverter; the third CMOS inverter includes a fifth transistor and a sixth transistor, the control electrode of the fifth transistor and the control electrode of the sixth transistor are coupled to the input end of the third CMOS inverter, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are coupled to the output end of the third CMOS inverter; the fourth CMOS inverter includes a seventh transistor and an eighth transistor, the control electrode of the third transistor and the control electrode of the fourth transistor are coupled to the input end of the third CMOS inverter, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are coupled to the output end of the third CMOS inverter; The control electrode of the seventh transistor and the control electrode of the eighth transistor are coupled to the input terminal of the fourth-stage CMOS inverter, and the second electrode of the seventh transistor and the second electrode of the eighth transistor are coupled to the output terminal of the fourth-stage CMOS inverter; the fifth-stage CMOS inverter includes a ninth transistor and a tenth transistor, the control electrode of the ninth transistor and the control electrode of the tenth transistor are coupled to the input terminal of the fifth-stage CMOS inverter, and the second electrode of the ninth transistor and the second electrode of the tenth transistor are coupled to the output terminal of the fifth-stage CMOS inverter; the sixth-stage CMOS inverter includes an eleventh transistor and a twelfth transistor, the control electrode of the eleventh transistor and the control electrode of the twelfth transistor are coupled to the input terminal of the sixth-stage CMOS inverter, and the second electrode of the eleventh transistor and the second electrode of the twelfth transistor are coupled to the output terminal of the sixth-stage CMOS inverter; the seventh-stage CMOS inverter includes a thirteenth transistor and a fourteenth transistor, the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor are coupled to the input terminal of the seventh-stage CMOS inverter, and the second electrode of the thirteenth transistor and the second electrode of the fourteenth transistor are coupled to the output terminal of the seventh-stage CMOS inverter;The first electrodes of the first transistor, the fifth transistor, the ninth transistor and the thirteenth transistor are all coupled to the first voltage terminal, and the first electrodes of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, the tenth transistor, the twelfth transistor and the fourteenth transistor are all coupled to the second voltage terminal; the first end of the first current source is coupled to the first voltage terminal, and the second end of the first current source is coupled to the first electrode of the third transistor; the first end of the second current source is coupled to the first voltage terminal, and the second end of the second current source is coupled to the first electrode of the seventh transistor; the first end of the third current source is coupled to the first voltage terminal, and the second end of the third current source is coupled to the first electrode of the eleventh transistor; the first end of the third capacitor is coupled between the output terminal of the second-stage CMOS inverter and the input terminal of the third-stage CMOS inverter, and the second end of the third capacitor is coupled to the second voltage terminal; The first end of the capacitor is coupled between the output end of the fourth-stage CMOS inverter and the input end of the fifth-stage CMOS inverter, and the second end of the fourth capacitor is coupled to the second voltage end; the first end of the fifth capacitor is coupled between the output end of the sixth-stage CMOS inverter and the input end of the seventh-stage CMOS inverter, and the second end of the fifth capacitor is coupled to the second voltage end; the first input end of the first AND gate is coupled to the input end of the start signal of the lower power tube, the second input end of the first AND gate is coupled to the output end of the fifth-stage CMOS inverter, and the output end of the first AND gate is coupled to the output end of the first sampling clock; the first input end of the second AND gate is coupled to the input end of the third-stage CMOS inverter, the second input end of the second AND gate is coupled to the output end of the seventh-stage CMOS inverter, and the output end of the second AND gate is coupled to the output end of the second sampling clock. ;

[0008] In some embodiments of the present disclosure, the noise reduction circuit includes: a first inverter, a first buffer, and a first switch. The input end of the first inverter is coupled to the output end of the shutdown signal of the upper power tube, the output end of the first inverter is coupled to the input end of the first buffer; the output end of the first buffer is coupled to the control end of the first switch; the input end of the first switch is coupled to the output end of the voltage signal of the switch node, and the output end of the first switch is coupled to the second non-inverting input end of the adaptive offset comparator.

[0009] In some embodiments of the present disclosure, the sampling and holding module includes: a second switch, a third switch, a first capacitor and a second capacitor. The control end of the second switch is coupled to the output end of the first sampling clock, the input end of the second switch is coupled to the output end of the voltage signal of the switch node, and the output end of the second switch is coupled to the first end of the first capacitor and the first sampling voltage signal end; the control end of the third switch is coupled to the output end of the second sampling clock, the input end of the third switch is coupled to the output end of the voltage signal of the switch node, and the output end of the third switch is coupled to the first end of the second capacitor and the second sampling voltage signal end; the second end of the first capacitor is coupled to the second voltage end; and the second end of the second capacitor is coupled to the second voltage end.

[0010] In some embodiments of the present disclosure, the first non-inverting input terminal of the adaptive offset comparator is coupled to the second sampling voltage signal terminal, the first inverting input terminal of the adaptive offset comparator is coupled to the first sampling voltage signal terminal, the second non-inverting input terminal of the adaptive offset comparator is coupled to the output terminal of the voltage signal of the switching node, the second inverting input terminal of the adaptive offset comparator is coupled to the output terminal of the power ground signal in the power output stage module, and the output terminal of the adaptive offset comparator is coupled to the zero-crossing detection signal output terminal.

[0011] In some embodiments of the present disclosure, the adaptive offset comparator includes: a fifteenth transistor to a twenty-sixth transistor, a fourth current source, a fifth current source, a second inverter, and a third inverter. Among them, the control electrode of the fifteenth transistor is coupled to the second sampling voltage signal terminal, the first electrode of the fifteenth transistor is coupled to the first end of the fourth current source and the first electrode of the sixteenth transistor, and the second electrode of the fifteenth transistor is coupled to the second electrode of the seventeenth transistor, the first electrode of the twenty-third transistor, and the second electrode of the twenty-fifth transistor; the control electrode of the sixteenth transistor is coupled to the first sampling voltage signal terminal, the second electrode of the sixteenth transistor is coupled to the second electrode of the eighteenth transistor, the first electrode of the twenty-fourth transistor, and the second electrode of the twenty-sixth transistor; the control electrode of the seventeenth transistor is coupled to the output terminal of the voltage signal of the switch node, the first electrode of the seventeenth transistor is coupled to the first end of the fifth current source and the first electrode of the eighteenth transistor; the control electrode of the eighteenth transistor is coupled to the output terminal of the power ground signal in the power output stage module; the control electrode of the nineteenth transistor is coupled to the second electrode of the nineteenth transistor, the first electrode of the twenty-first transistor, and the control electrode of the twentieth transistor, and the control electrode of the nineteenth transistor is coupled to the output terminal of the power ground signal in the power output stage module; The first electrode is coupled to the first voltage terminal; the first electrode of the 20th transistor is coupled to the first voltage terminal, and the second electrode of the 20th transistor is coupled to the first electrode of the 22nd transistor; the control electrode of the 21st transistor is coupled to the control electrode of the 22nd transistor and the third voltage terminal, and the second electrode of the 21st transistor is coupled to the second electrode of the 23rd transistor; the second electrode of the 22nd transistor is coupled to the second electrode of the 24th transistor and the input terminal of the second inverter; the control electrode of the 23rd transistor is coupled to the control electrode of the 24th transistor and the fourth voltage terminal; the control electrode of the 25th transistor is coupled to the control electrode of the 26th transistor and the fifth voltage terminal, and the first electrode of the 25th transistor is coupled to the first electrode of the 26th transistor and the second voltage terminal; the second terminal of the fourth current source is coupled to the first voltage terminal; the second terminal of the fifth current source is coupled to the first voltage terminal; the output terminal of the second inverter is coupled to the input terminal of the third inverter; and the output terminal of the third inverter is coupled to the zero-crossing detection signal output terminal.

[0012] In some embodiments of the present disclosure, the adaptive offset comparator is further configured to obtain the zero-crossing detection signal as a valid signal when the sum of the voltage signal of the switch node and the early shutdown amount is equal to the power ground signal in the power output stage module.

[0013] A second aspect of an embodiment of the present disclosure provides a zero-crossing detection method. According to the zero-crossing detection circuit described in the first aspect, the method includes: when the upper power tube is turned off, sampling the voltage signal of the switch node at the first sampling clock and the second sampling clock to obtain a first sampled voltage signal and a second sampled voltage signal respectively; obtaining an early shutdown amount for controlling the lower power tube according to the second sampled voltage signal and the first sampled voltage signal; obtaining a zero-crossing detection signal according to the voltage signal of the switch node, the early shutdown amount and the power ground signal; and turning off the lower power tube based on the effective zero-crossing detection signal.

[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the accompanying drawings: Figure 1 This is a schematic diagram of the current backflow path of the synchronous BUCK circuit; Figure 2 It is a schematic diagram of the inductor current backflow waveform; Figure 3 It is a schematic diagram of a zero-crossing detection circuit; Figure 4 This is a waveform diagram of the power tube being closed in advance; Figure 5 It is a waveform diagram of the power tube under delayed shutdown; Figure 6 is a schematic block diagram of a zero-crossing detection circuit according to an embodiment of the present disclosure; Figure 7 is a schematic block diagram of a logic driver module according to an embodiment of the present disclosure; Figure 8 is an exemplary circuit diagram of a sampling clock circuit according to an embodiment of the present disclosure; Fig. 9 is an exemplary circuit diagram of a noise reduction circuit according to an embodiment of the present disclosure; Fig.10 is an exemplary circuit diagram of an adaptive offset comparator according to an embodiment of the present disclosure; Fig.11 is an equivalent exemplary circuit diagram of an adaptive offset comparator according to an embodiment of the present disclosure; Fig.12 is a waveform diagram of a zero-crossing detection circuit according to an embodiment of the present disclosure.

[0016] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0018] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0019] To avoid Figure 1 In order to prevent the current backflow situation shown in the figure from happening, it is necessary to design a zero-crossing detection circuit. The zero-crossing detection circuit can detect the state of the inductor current. When it is detected that the inductor current is zero, it will output a control signal to quickly turn off the rectifier tube. Due to the existence of the on-resistance of the power tube, when the lower power tube LS is freewheeling, the potential of the switch node SW will decrease linearly with the decrease of the inductor current. Therefore, when the inductor current drops to 0, the potential of the switch node SW also decreases to 0. The existing commonly used zero-crossing detection circuits all detect the potential of the switch node SW to detect the inductor current, such as Figure 3 As shown, it is mainly composed of a comparator and a logic drive part. When the upper power tube HS is turned off, the shutdown signal of the upper power tube is delayed by the inverter INV1 and the buffer BUFFER1 to close the switch S1. The switch node SW voltage and the power ground signal PGND are sampled to the comparator COMP's in-phase input and the reverse input for comparison to monitor the inductor current state. In order to offset the non-ideal delay of the comparator COMP and the logic drive part, an artificial resistor R1 and a current source I are set. B The actual potential of the switch node SW is V when the comparator COMP starts to flip. PGND +I B R1, the inductor current IL is greater than 0. When the comparator offset is set appropriately, even if the zero-crossing detection signal requires a long delay to enable, the lower power tube can be turned off before the inductor current crosses zero. In addition, in order to increase the robustness of the circuit design, Figure 3A correction module is added to adjust the comparator offset parameters. When the inductor test engineer performs zero-crossing detection module performance test on the actual chip, he will first enter the chip test mode, at which time the upper power tube of the control chip is turned off and the lower power tube is turned on. Then the inductor test engineer will use external excitation on the test board to slowly reduce the current flowing through the lower power tube LS to the power ground signal PGND to obtain the actual inductor current value when zero-crossing detection is enabled, and use this to adjust the current source I B Correction is made and finally the lower power tube is turned off just when the inductor current IL is 0.

[0020] However, the above zero-crossing detection circuit can only achieve high zero-crossing detection accuracy under a fixed inductor current slope di / dt. When the chip is corrected, the corresponding comparator offset is also fixed. From the current slope calculation formula di / dt=-V_OUT / L during inductor freewheeling, it can be seen that when the chip is in different applications requiring different inductors L and output voltages VOUT, the inductor current slope di / dt will change, causing the lower power tube LS to close ahead or behind, resulting in non-ideal conditions. Figure 4 The waveform diagram of the lower power tube is turned off in advance, so that the body diode D2 of the lower power tube LS is turned on, which increases the number of unbalanced minority carriers stored in the body diode D2, resulting in an increase in the reverse recovery current, and Figure 5 It is a waveform diagram of the delayed shutdown of the lower power tube, which makes the body diode D1 of the upper power tube HS turned on, increasing the number of unbalanced minority carriers stored in the body diode D1 and causing the reverse recovery current to increase. Figure 4 and Figure 5 Both will cause more residual current in the inductor to generate greater ringing at the switch node SW, thereby greatly reducing the chip efficiency.

[0021] In order to solve the above problems, Figure 6 FIG. 4 shows a schematic block diagram of a zero-crossing detection circuit 600 according to an embodiment of the present disclosure. Figure 6 As shown, the zero-crossing detection circuit 600 includes: a logic driving module 610 , a sampling and holding module 620 , an adaptive offset comparator 630 and a power output stage module 640 .

[0022] The logic driving module 610 is configured to enable the sampling and holding module 620 and provide the first sampling clock S1 and the second sampling clock S2 to the sampling and holding module 620 when the upper power tube in the power output stage module 640 is turned off.

[0023] The sampling and holding module 620 is configured to sample the voltage signal of the switch node SW in the power output stage module 640 at the first sampling clock S1 to obtain a first sampled voltage signal VL1 , and to sample the voltage signal of the switch node SW at the second sampling clock S2 to obtain a second sampled voltage signal VL2 .

[0024] The adaptive offset comparator 630 is configured to obtain the early shutdown amount VOS of the lower power tube in the power output stage module 640 according to the second sampled voltage signal VL2 and the first sampled voltage signal VL1, and obtain the zero-crossing detection signal ZCD according to the voltage signal of the switch node SW, the early shutdown amount VOS and the power ground signal VPGND in the power output stage module.

[0025] The logic driving module 610 is further configured to shut down the lower power tube in the power output stage module 640 based on the effective zero-crossing detection signal ZCD. For example, when the zero-crossing detection signal ZCD is at a high level, it is a valid signal.

[0026] The power output stage module 640 is configured to obtain an output voltage through a switching process of an upper power tube and a lower power tube.

[0027] Among them, Figure 7 As shown, the logic driving module 610 includes: a driving circuit 611, an enabling circuit 612 and a sampling clock circuit 613. The driving circuit 611 is configured to control the switches of the upper power tube and the lower power tube. The specific circuit structure is not limited in the embodiment of the present disclosure, and can be specifically adaptively adjusted according to the power output stage module 640. The enabling circuit 612 is configured to provide an enabling signal EN to the sampling and holding module 620 when the upper power tube is turned off. The specific circuit structure is not limited in the embodiment of the present disclosure, as long as it can provide an enabling signal to the sampling and holding module 620. The sampling clock circuit 613 is configured to provide the first sampling clock S1 and the second sampling clock S2 to the sampling and holding module based on the start signal LS ON of the lower power tube.

[0028] like Figure 8As shown, the sampling clock circuit 613 may include: seven stages of CMOS inverters connected end to end, a first current source I1, a second current source I2, a third current source I3, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first AND gate G1, and a second AND gate G2. The output of each stage of CMOS inverter is coupled to the input of the lower stage CMOS inverter, the input of the first stage CMOS inverter is coupled to the input of the start signal LS ON of the lower power tube, the first stage CMOS inverter includes a first transistor M1 and a second transistor M2, the control electrode of the first transistor M1 and the control electrode of the second transistor M2 are coupled to the input of the first stage CMOS inverter, and the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are coupled to the output of the first stage CMOS inverter. The second-stage CMOS inverter includes a third transistor M3 and a fourth transistor M4, wherein the control electrode of the third transistor M3 and the control electrode of the fourth transistor M4 are coupled to the input terminal of the second-stage CMOS inverter, and the second electrode of the third transistor M3 and the second electrode of the fourth transistor M4 are coupled to the output terminal of the second-stage CMOS inverter. The third-stage CMOS inverter includes a fifth transistor M5 and a sixth transistor M6, wherein the control electrode of the fifth transistor M5 and the control electrode of the sixth transistor M6 are coupled to the input terminal of the third-stage CMOS inverter, and the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are coupled to the output terminal of the third-stage CMOS inverter. The fourth-stage CMOS inverter includes a seventh transistor M7 and an eighth transistor M8, wherein the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 are coupled to the input terminal of the fourth-stage CMOS inverter, and the second electrode of the seventh transistor M7 and the second electrode of the eighth transistor M8 are coupled to the output terminal of the fourth-stage CMOS inverter. The fifth-stage CMOS inverter includes a ninth transistor M9 and a tenth transistor M10, wherein the control electrode of the ninth transistor M9 and the control electrode of the tenth transistor M10 are coupled as the input terminal of the fifth-stage CMOS inverter, and the second electrode of the ninth transistor M9 and the second electrode of the tenth transistor M10 are coupled as the output terminal of the fifth-stage CMOS inverter. The sixth-stage CMOS inverter includes an eleventh transistor M11 and a twelfth transistor M12, wherein the control electrode of the eleventh transistor M11 and the control electrode of the twelfth transistor M12 are coupled as the input terminal of the sixth-stage CMOS inverter, and the second electrode of the eleventh transistor M11 and the second electrode of the twelfth transistor M12 are coupled as the output terminal of the sixth-stage CMOS inverter.The seventh-stage CMOS inverter includes a thirteenth transistor M13 and a fourteenth transistor M14, wherein the control electrode of the thirteenth transistor M13 and the control electrode of the fourteenth transistor M14 are coupled to the input terminal of the seventh-stage CMOS inverter, and the second electrode of the thirteenth transistor M13 and the second electrode of the fourteenth transistor M14 are coupled to the output terminal of the seventh-stage CMOS inverter. The first electrodes of the first transistor M1, the fifth transistor M5, the ninth transistor M9 and the thirteenth transistor M13 are all coupled to the first voltage terminal V1, and the first electrodes of the second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12 and the fourteenth transistor M12 are all coupled to the second voltage terminal V2. The first terminal of the first current source I1 is coupled to the first voltage terminal V1, and the second terminal of the first current source I1 is coupled to the first electrode of the third transistor M3. The first terminal of the second current source I2 is coupled to the first voltage terminal V1, and the second terminal of the second current source I2 is coupled to the first electrode of the seventh transistor M7. The first end of the third current source I3 is coupled to the first voltage terminal V1, and the second end of the third current source I3 is coupled to the first electrode of the eleventh transistor M11. The first end of the third capacitor C3 is coupled between the output end of the second-stage CMOS inverter and the input end of the third-stage CMOS inverter, and the second end of the third capacitor C3 is coupled to the second voltage terminal V2. The first end of the fourth capacitor C4 is coupled between the output end of the fourth-stage CMOS inverter and the input end of the fifth-stage CMOS inverter, and the second end of the fourth capacitor C4 is coupled to the second voltage terminal V2. The first end of the fifth capacitor C5 is coupled between the output end of the sixth-stage CMOS inverter and the input end of the seventh-stage CMOS inverter, and the second end of the fifth capacitor C5 is coupled to the second voltage terminal V2. The first input end of the first AND gate G1 is coupled to the input end of the start signal LS ON of the lower power tube, the second input end of the first AND gate G1 is coupled to the output end of the fifth-stage CMOS inverter, and the output end of the first AND gate G1 is coupled to the output end of the first sampling clock S1. A first input terminal of the second AND gate G2 is coupled to the input terminal of the third-stage CMOS inverter, a second input terminal of the second AND gate G2 is coupled to the output terminal of the seventh-stage CMOS inverter, and an output terminal of the second AND gate G2 is coupled to the output terminal of the second sampling clock S2.

[0029] In addition, in order to prevent the sampling of the switch node SW from being interfered by the noise when the power stage switch is switched, the logic driving module 610 may further include: a noise reduction circuit 614. The noise reduction circuit 614 is configured to provide the voltage signal of the switch node SW to the adaptive offset comparator 630 based on the shutdown signal HS OFF of the upper power tube.

[0030] Specifically, Fig. 9 As shown, the noise reduction circuit 614 may include: a first inverter INV1, a first buffer BUFFER1, and a first switch k1. The input end of the first inverter INV1 is coupled to the output end of the shutdown signal HS OFF of the upper power tube, and the output end of the first inverter INV1 is coupled to the input end of the first buffer BUFFER1. The output end of the first buffer BUFFER1 is coupled to the control end of the first switch k1. The input end of the first switch k1 is coupled to the voltage signal end of the switch node SW, and the output end of the first switch k1 is coupled to the second non-inverting input end of the adaptive offset comparator 630.

[0031] like Figure 6 As shown, the sampling and holding module includes: a second switch k2, a third switch k3, a first capacitor C1 and a second capacitor C2. The control end of the second switch k2 is coupled to the output end of the first sampling clock S1, the input end of the second switch k2 is coupled to the voltage signal end of the switch node SW, and the output end of the second switch k2 is coupled to the first end of the first capacitor C1 and the first sampling voltage signal end VL1. The control end of the third switch k3 is coupled to the output end of the second sampling clock S2, the input end of the third switch k3 is coupled to the voltage signal end of the switch node SW, and the output end of the third switch k3 is coupled to the first end of the second capacitor C2 and the second sampling voltage signal end VL2. The second end of the first capacitor C1 is coupled to the second voltage end V2. The second end of the second capacitor C2 is coupled to the second voltage end V2.

[0032] The first non-inverting input terminal of the adaptive offset comparator 630 is coupled to the second sampling voltage signal terminal VL2, the first inverting input terminal of the adaptive offset comparator 630 is coupled to the first sampling voltage signal terminal VL1, the second non-inverting input terminal of the adaptive offset comparator 630 is coupled to the voltage signal terminal of the switch node SW, the second inverting input terminal of the adaptive offset comparator 630 is coupled to the output terminal PGND of the power ground signal in the power output stage module 640, and the output terminal of the adaptive offset comparator 630 is coupled to the zero-crossing detection signal ZCD output terminal.

[0033] Specifically, Fig.10As shown, the adaptive offset comparator 630 may include: a fifteenth transistor M15 to a twenty-sixth transistor M26, a fourth current source I4, a fifth current source I5, a second inverter D2, and a third inverter D3. The control electrode of the fifteenth transistor M15 is coupled to the second sampling voltage signal terminal VL2, the first electrode of the fifteenth transistor M15 is coupled to the first terminal of the fourth current source I4 and the first electrode of the sixteenth transistor M16, the second electrode of the fifteenth transistor M15 is coupled to the second electrode of the seventeenth transistor M17, the first electrode of the twenty-third transistor M23, and the second electrode of the twenty-fifth transistor M25. The control electrode of the sixteenth transistor M16 is coupled to the first sampling voltage signal terminal VL1, and the second electrode of the sixteenth transistor M16 is coupled to the second electrode of the eighteenth transistor M18, the first electrode of the twenty-fourth transistor M24, and the second electrode of the twenty-sixth transistor M26. The control electrode of the seventeenth transistor M17 is coupled to the voltage signal terminal of the switch node SW, and the first electrode of the seventeenth transistor M17 is coupled to the first terminal of the fifth current source I5 and the first electrode of the eighteenth transistor M18. The control electrode of the eighteenth transistor M18 is coupled to the output terminal PGND of the power ground signal in the power output stage module 640. The control electrode of the nineteenth transistor M19 is coupled to the second electrode of the nineteenth transistor M19, the first electrode of the twenty-first transistor M21 and the control electrode of the twentieth transistor M20, and the first electrode of the nineteenth transistor M19 is coupled to the first voltage terminal V1. The first electrode of the twentieth transistor M20 is coupled to the first voltage terminal V1, and the second electrode of the twentieth transistor M20 is coupled to the first electrode of the twenty-second transistor M22. The control electrode of the twenty-first transistor M21 is coupled to the control electrode of the twenty-second transistor M22 and the third voltage terminal V BP The second electrode of the 21st transistor M21 is coupled to the second electrode of the 23rd transistor M23. The second electrode of the 22nd transistor M22 is coupled to the second electrode of the 24th transistor M24 and the input terminal of the second inverter D2. The control electrode of the 23rd transistor M23 is coupled to the control electrode of the 24th transistor M24 and the fourth voltage terminal V BN1 The control electrode of the twenty-fifth transistor M25 is coupled to the control electrode of the twenty-sixth transistor M26 and the fifth voltage terminal V BN2 , the first electrode of the second-fifth transistor M25 is coupled to the first electrode of the second-sixth transistor M26 and the second voltage terminal V2. The second end of the fourth current source I4 is coupled to the first voltage terminal V1. The second end of the fifth current source I5 is coupled to the first voltage terminal V1. The output end of the second inverter D2 is coupled to the input end of the third inverter D3. The output end of the third inverter D3 is coupled to the zero-crossing detection signal output end ZCD.

[0034] In the embodiment of the present disclosure, the circuit structure of the power output stage module 640 is not specifically limited, and only needs to include an upper power tube and a lower power tube whose switches are controlled by the logic drive module 610. The power output stage module 640 can obtain an output voltage containing duty cycle information through the switching process and filtering of external passive components.

[0035] exist Figure 6 , 8 In the example of -10, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. BP , the fourth voltage terminal V BN1 , the fifth voltage terminal V BN2 The fourth voltage terminal V BN1 The input bias voltage is greater than the fifth voltage terminal V BN2 The bias voltage input is not limited in the embodiment of the present disclosure. The first transistor M1, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the eighth transistor M9, the eleventh transistor M11, the thirteenth transistor M13, the fifteenth transistor M15 to the twenty-second transistor M22 are all PMOS transistors. The second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12, the fourteenth transistor M14, the twenty-third transistor M23 to the twenty-sixth transistor M26 are all NMOS transistors. The current value of the fifth current source I5 is m times the current value of the fourth current source I4. The width-to-length ratio of the seventeenth transistor M17 and the eighteenth transistor M18 is m times the width-to-length ratio of the fifteenth transistor M15 and the sixteenth transistor M16. Those skilled in the art should understand that based on the above-mentioned inventive concept, Figure 6 , 8 -10 should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 6 , 8 -10 examples shown with different settings.

[0036] In addition, in the above embodiment, although the zero-crossing detection circuit 600 is described as a Buck type converter, it can be understood that the embodiments of the present disclosure include but are not limited to Buck type, and can also be Boost type, Buck-boost type, motor type, driver type and other power supply circuits involving accurate zero-crossing detection implementation, and are also applicable.

[0037] Furthermore, the present disclosure provides a method corresponding to Figure 6 The zero-crossing detection method of the zero-crossing detection circuit 600 is combined with Figure 6-10The detection method is described in the structural diagram of FIG. 1 , which includes: when the upper power tube is turned off, sampling the voltage signal VSW of the switch node SW at the first sampling clock S1 and the second sampling clock S2 to obtain the first sampling voltage signal VL1 and the second sampling voltage signal VL2 respectively; obtaining the early shutdown amount VOS of the lower power tube according to the second sampling voltage signal VL2 and the first sampling voltage signal VL1; obtaining the zero-crossing detection signal ZCD according to the voltage signal VSW of the switch node SW, the early shutdown amount VOS and the power ground signal VPGND; and turning off the lower power tube based on the effective zero-crossing detection signal ZCD.

[0038] Specifically, when the inductor is in the freewheeling state, the shutdown signal provided by the logic driving module 610 to the lower power tube in the power output stage module 640 will be inverted by the first inverter INV1 and delayed by the first buffer BUFFER1, so that the first switch k1 is closed to sample the voltage signal of the switch node SW to the adaptive offset comparator 630, so as to prevent the voltage signal of the switch node SW from being interfered by the noise when the switch in the power output stage module 640 is switched. Then, the logic driving module 610 enables the sampling and holding module 620, and successively provides the first sampling clock S1 and the second sampling clock S2. The sampling and holding module 620 will close the second switch k2 at the first sampling clock S1, and use the voltage of the switch node SW of the sampling clock to charge the first capacitor C1, so as to obtain the first sampling voltage signal VL1; and close the third switch k3 at the second sampling clock S2, and use the voltage of the switch node SW of the sampling clock to charge the second capacitor C2, so as to obtain the second sampling voltage signal VL2.

[0039] The first sampling clock S1, the second sampling clock S2 provided by the sampling clock circuit 613 in the logic driving module 610 and the start signal LS ON of the lower power tube have the following relationship: the interval time between the start signal LS ON of the lower power tube and the first sampling clock S1 is 0.5 C3 V1 / I1, the interval between the first sampling clock S1 and the second sampling clock S2 (or the moment when the first sampling voltage signal VL1 is obtained) is 0.5 C4 V1 / I 2, the interval between the second sampling clock S2 and the moment of obtaining the second sampling voltage signal VL2 is 0.5 C5 V1 / I3. It is assumed that the flip threshold of the first AND gate G1 and the second AND gate G2 is 50% V1.

[0040] In addition, the transconductance of the transistor can be expressed by the following formula (1): Formula (1) in, is the oxide layer capacitance, is the electron mobility, is the ratio of transistor channel width to length, is the output current of the transistor.

[0041] Because the current value of the fifth current source I5 is m times the current value of the fourth current source I4, and the width-to-length ratio of the seventeenth transistor M17 to the eighteenth transistor M18 is m times the width-to-length ratio of the fifteenth transistor M15 to the sixteenth transistor M16, the following formula (2) can be obtained: Formula (2) in, is the output current of the seventeenth transistor M17 and the eighteenth transistor M18, is the output current of the fifteenth transistor M15 and the sixteenth transistor M16, is the width-to-length ratio of the seventeenth transistor M17 to the eighteenth transistor M18, is the width-to-length ratio of the fifteenth transistor M15 to the sixteenth transistor M16.

[0042] Therefore, the early shutdown amount VOS of the lower power tube can be obtained by the following formula (3): Formula (3) in, is the transconductance of the fifteenth transistor M15 and the sixteenth transistor M16, is the transconductance of the seventeenth transistor M17 and the eighteenth transistor M18.

[0043] In summary, the adaptive offset comparator 630 can be equivalent to Fig.11 When VSW+VOS=VPGND, the zero-crossing detection signal ZCD is a valid signal. By using the valid zero-crossing detection signal ZCD, the lower power tube is turned off just when the inductor current crosses zero. Fig.12 As shown, accurate zero-crossing detection control is achieved.

[0044] The disclosed embodiments can achieve high-precision zero-crossing detection in different output voltage and inductance application scenarios, thereby improving product flexibility while increasing the conversion efficiency of the chip when working in DCM and reducing the ringing of the switch node.

[0045] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0046] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0047] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A zero-crossing detection circuit, characterized in that: include: Logic driver module, sample and hold module, adaptive offset comparator and power output stage module, Wherein, the logic driving module is configured to enable the sampling and holding module when the upper power tube in the power output stage module is turned off, and provide the first sampling clock and the second sampling clock to the sampling and holding module; The sampling and holding module is configured to sample the voltage signal of the switch node in the power output stage module at the first sampling clock to obtain a first sampled voltage signal, and sample the voltage signal of the switch node at the second sampling clock to obtain a second sampled voltage signal; The adaptive offset comparator is configured to obtain an early shutdown amount of the lower power tube in the power output stage module according to the second sampled voltage signal and the first sampled voltage signal, and obtain a zero-crossing detection signal according to the voltage signal of the switch node, the early shutdown amount and the power ground signal in the power output stage module; The logic driving module is further configured to turn off the lower power tube in the power output stage module based on the effective zero-crossing detection signal; The power output stage module is configured to obtain an output voltage through a switching process of an upper power tube and a lower power tube.

2. The zero-crossing detection circuit according to claim 1, characterized in that: The logic driving module includes: a driving circuit, an enabling circuit and a sampling clock circuit. Wherein, the driving circuit is configured to control the switching of the upper power tube and the lower power tube; The enabling circuit is configured to provide an enabling signal to the sampling and holding module when the upper power tube is turned off; The sampling clock circuit is configured to provide the first sampling clock and the second sampling clock to the sample and hold module based on the start-up signal of the lower power tube.

3. The zero-crossing detection circuit according to claim 1, characterized in that: The logic driving module further includes: a noise reduction circuit, The noise reduction circuit is configured to provide the voltage signal of the switch node to the adaptive offset comparator based on the shutdown signal of the upper power tube.

4. The zero-crossing detection circuit according to claim 2, characterized in that: The sampling clock circuit comprises: seven stages of CMOS inverters connected end to end, a first current source, a second current source, a third current source, a third capacitor, a fourth capacitor, a fifth capacitor, a first AND gate and a second AND gate, Wherein, each stage of the CMOS inverter is coupled to the input end of the lower stage CMOS inverter through its output end, the input end of the first stage CMOS inverter is coupled to the input end of the start signal of the lower power tube, the first stage CMOS inverter includes a first transistor and a second transistor, the control electrode of the first transistor and the control electrode of the second transistor are coupled as the input end of the first stage CMOS inverter, the second electrode of the first transistor and the second electrode of the second transistor are coupled as the output end of the first stage CMOS inverter; the second stage CMOS inverter includes a third transistor and a fourth transistor, the control electrode of the third transistor and the control electrode of the fourth transistor are coupled as the second stage CMOS inverter. The third-stage CMOS inverter comprises a fifth transistor and a sixth transistor, the control electrode of the fifth transistor and the control electrode of the sixth transistor are coupled as the input terminal of the third-stage CMOS inverter, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are coupled as the output terminal of the third-stage CMOS inverter; the fourth-stage CMOS inverter comprises a seventh transistor and an eighth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor are coupled as the input terminal of the fourth-stage CMOS inverter, and the seventh transistor is coupled as the output terminal of the fourth-stage CMOS inverter. The second electrode of the eighth transistor and the second electrode of the eighth transistor are coupled to the output terminal of the fourth-stage CMOS inverter; the fifth-stage CMOS inverter includes a ninth transistor and a tenth transistor, the control electrode of the ninth transistor and the control electrode of the tenth transistor are coupled to the input terminal of the fifth-stage CMOS inverter, and the second electrode of the ninth transistor and the second electrode of the tenth transistor are coupled to the output terminal of the fifth-stage CMOS inverter; the sixth-stage CMOS inverter includes an eleventh transistor and a twelfth transistor, the control electrode of the eleventh transistor and the control electrode of the twelfth transistor are coupled to the input terminal of the sixth-stage CMOS inverter, and the second electrode of the eleventh transistor and the second electrode of the twelfth transistor are coupled to the input terminal of the sixth-stage CMOS inverter. coupled to the output terminal of the sixth-stage CMOS inverter; the seventh-stage CMOS inverter includes a thirteenth transistor and a fourteenth transistor, the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor are coupled to the input terminal of the seventh-stage CMOS inverter, and the second electrode of the thirteenth transistor and the second electrode of the fourteenth transistor are coupled to the output terminal of the seventh-stage CMOS inverter; the first electrodes of the first transistor, the fifth transistor, the ninth transistor and the thirteenth transistor are all coupled to the first voltage terminal, and the first electrodes of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, the tenth transistor, the twelfth transistor and the fourteenth transistor are all coupled to the second voltage terminal; A first terminal of the first current source is coupled to a first voltage terminal, and a second terminal of the first current source is coupled to a first electrode of the third transistor; A first terminal of the second current source is coupled to the first voltage terminal, and a second terminal of the second current source is coupled to the first electrode of the seventh transistor; A first terminal of the third current source is coupled to the first voltage terminal, and a second terminal of the third current source is coupled to the first electrode of the eleventh transistor; A first end of the third capacitor is coupled between the output end of the second-stage CMOS inverter and the input end of the third-stage CMOS inverter, and a second end of the third capacitor is coupled to the second voltage end; A first end of the fourth capacitor is coupled between the output end of the fourth-stage CMOS inverter and the input end of the fifth-stage CMOS inverter, and a second end of the fourth capacitor is coupled to the second voltage end; A first end of the fifth capacitor is coupled between the output end of the sixth-stage CMOS inverter and the input end of the seventh-stage CMOS inverter, and a second end of the fifth capacitor is coupled to the second voltage end; The first input end of the first AND gate is coupled to the input end of the start-up signal of the lower power tube, the second input end of the first AND gate is coupled to the output end of the fifth-stage CMOS inverter, and the output end of the first AND gate is coupled to the output end of the first sampling clock; The first input terminal of the second AND gate is coupled to the input terminal of the third-stage CMOS inverter, the second input terminal of the second AND gate is coupled to the output terminal of the seventh-stage CMOS inverter, and the output terminal of the second AND gate is coupled to the output terminal of the second sampling clock.

5. The zero-crossing detection circuit according to claim 3, characterized in that: The noise reduction circuit includes: a first inverter, a first buffer and a first switch. Wherein, the input end of the first inverter is coupled to the output end of the shutdown signal of the upper power tube, and the output end of the first inverter is coupled to the input end of the first buffer; The output terminal of the first buffer is coupled to the control terminal of the first switch; An input terminal of the first switch is coupled to an output terminal of a voltage signal of the switch node, and an output terminal of the first switch is coupled to a second non-inverting input terminal of the adaptive offset comparator.

6. The zero-crossing detection circuit according to claim 1, characterized in that: The sampling and holding module includes: a second switch, a third switch, a first capacitor and a second capacitor. The control end of the second switch is coupled to the output end of the first sampling clock, the input end of the second switch is coupled to the output end of the voltage signal of the switch node, and the output end of the second switch is coupled to the first end of the first capacitor and the first sampling voltage signal end; The control end of the third switch is coupled to the output end of the second sampling clock, the input end of the third switch is coupled to the output end of the voltage signal of the switch node, and the output end of the third switch is coupled to the first end of the second capacitor and the second sampling voltage signal end; The second terminal of the first capacitor is coupled to a second voltage terminal; The second terminal of the second capacitor is coupled to the second voltage terminal.

7. The zero-crossing detection circuit according to claim 1, characterized in that: The first non-inverting input terminal of the adaptive offset comparator is coupled to the second sampling voltage signal terminal, the first inverting input terminal of the adaptive offset comparator is coupled to the first sampling voltage signal terminal, the second non-inverting input terminal of the adaptive offset comparator is coupled to the output terminal of the voltage signal of the switch node, the second inverting input terminal of the adaptive offset comparator is coupled to the output terminal of the power ground signal in the power output stage module, and the output terminal of the adaptive offset comparator is coupled to the zero-crossing detection signal output terminal.

8. The zero-crossing detection circuit according to claim 7, characterized in that: The adaptive offset comparator includes: a fifteenth transistor to a twenty-sixth transistor, a fourth current source, a fifth current source, a second inverter and a third inverter. wherein a control electrode of the fifteenth transistor is coupled to the second sampling voltage signal terminal, a first electrode of the fifteenth transistor is coupled to the first terminal of the fourth current source and the first electrode of the sixteenth transistor, and a second electrode of the fifteenth transistor is coupled to the second electrode of the seventeenth transistor, the first electrode of the twenty-third transistor and the second electrode of the twenty-fifth transistor; The control electrode of the sixteenth transistor is coupled to the first sampling voltage signal terminal, and the second electrode of the sixteenth transistor is coupled to the second electrode of the eighteenth transistor, the first electrode of the twenty-fourth transistor and the second electrode of the twenty-sixth transistor; A control electrode of the seventeenth transistor is coupled to an output end of a voltage signal of the switch node, and a first electrode of the seventeenth transistor is coupled to a first end of the fifth current source and a first electrode of the eighteenth transistor; The control electrode of the eighteenth transistor is coupled to the output terminal of the power ground signal in the power output stage module; The control electrode of the nineteenth transistor is coupled to the second electrode of the nineteenth transistor, the first electrode of the twenty-first transistor and the control electrode of the twentieth transistor, and the first electrode of the nineteenth transistor is coupled to the first voltage terminal; A first electrode of the 20th transistor is coupled to the first voltage terminal, and a second electrode of the 20th transistor is coupled to the first electrode of the 22nd transistor; The control electrode of the twenty-first transistor is coupled to the control electrode of the twenty-second transistor and the third voltage terminal, and the second electrode of the twenty-first transistor is coupled to the second electrode of the twenty-third transistor; The second electrode of the 22nd transistor is coupled to the second electrode of the 24th transistor and the input terminal of the second inverter; The control electrode of the twenty-third transistor is coupled to the control electrode of the twenty-fourth transistor and the fourth voltage terminal; The control electrode of the twenty-fifth transistor is coupled to the control electrode of the twenty-sixth transistor and the fifth voltage terminal, and the first electrode of the twenty-fifth transistor is coupled to the first electrode of the twenty-sixth transistor and the second voltage terminal; The second terminal of the fourth current source is coupled to the first voltage terminal; The second terminal of the fifth current source is coupled to the first voltage terminal; The output terminal of the second inverter is coupled to the input terminal of the third inverter; An output terminal of the third inverter is coupled to the zero-crossing detection signal output terminal.

9. The zero-crossing detection circuit according to claim 1, characterized in that: The adaptive offset comparator is further configured to obtain the zero-crossing detection signal as a valid signal when the sum of the voltage signal of the switch node and the early closing amount is equal to the power ground signal in the power output stage module.

10. A zero-crossing detection method, characterized in that: According to the zero-crossing detection circuit according to any one of claims 1 to 9, the method comprises: When the upper power tube is turned off, the voltage signal of the switch node is sampled at the first sampling clock and the second sampling clock to obtain a first sampling voltage signal and a second sampling voltage signal respectively; Obtaining an early closing amount of the power tube under control according to the second sampling voltage signal and the first sampling voltage signal; Obtaining a zero-crossing detection signal according to the voltage signal of the switch node, the early closing amount and the power ground signal; The lower power tube is turned off based on the valid zero-crossing detection signal.

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