Chip test board, chip verification system, chip test system and chip test method
By designing a chip test board, using FPGA chips to connect to the chip to be tested, and obtaining the test program based on the startup code, the problem of high cost of existing automated testing equipment is solved and efficient chip testing is achieved.
Patent Information
- Application Number
- CN202411369116.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-02-25
AI Technical Summary
Existing automated testing equipment requires a proprietary testing environment and is costly.
Design a chip test board, including the chip to be tested, the FPGA chip and the test main chip, connect it to the chip to be tested through the FPGA chip, and use the startup code to obtain the test program to realize the test.
Reduces testing costs, and can verify different chips through one set of environments, saving additional cost of configuring the environment.
Smart Images
Figure CN119511026A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing board, a chip verification system, a chip testing system and a chip testing method. Background Art
[0002] Automated test equipment (ATE) can be any test assembly that tests a device, semiconductor wafer, or die, etc. ATE assemblies can be used to perform automated tests that quickly take measurements and generate test results that can then be analyzed. ATE assemblies can be anything from a computer system connected to a meter to a complex automated test assembly, which can include a customized dedicated computer control system and many different test instruments that can automatically test electronic device parts and / or semiconductors. Automatic test equipment (ATE) is commonly used in the field of electrical chip manufacturing. ATE systems both reduce the amount of time spent testing devices to ensure that the devices function as designed, and are used as diagnostic tools to determine the presence of faulty components in a given device before it reaches the hands of a consumer.
[0003] However, the current automated testing equipment approach requires a proprietary testing environment, which is costly. Summary of the invention
[0004] Based on this, it is necessary to provide a chip testing board, a chip verification system, a chip testing system and a chip testing method that can reduce the testing cost in response to the above technical problems.
[0005] In a first aspect, the present application provides a chip testing board, the chip testing board comprising:
[0006] Chip to be tested;
[0007] A socket plug-in, wherein the chip to be tested is placed in the socket plug-in;
[0008] FPGA chip, the FPGA chip is connected to the chip to be tested through the socket plug-in;
[0009] A test main chip, the test main chip communicates with the test host and is connected to the chip to be tested through the FPGA chip; the test main chip is used to download the test program from the test host;
[0010] A download interface, the download interface is connected to the FPGA chip and the chip to be tested respectively, and the download interface is used to download the startup code of the FPGA chip and the chip to be tested;
[0011] The FPGA chip is used to obtain a test program corresponding to the FPGA chip based on the startup code of the FPGA chip, and the chip to be tested is used to obtain a test program for the chip to be tested based on the startup code of the chip to be tested. The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain a test result.
[0012] In one embodiment, the chip testing board further includes:
[0013] A storage module, the storage module is used to store the test program downloaded by the test host, and the storage module includes the FPGA chip storage space and the chip to be tested storage space;
[0014] The startup code of the FPGA chip is used to control the FPGA chip to start from the first startup space of the FPGA chip storage space, and obtain the test program corresponding to the FPGA chip from the first test code space of the FPGA chip storage space;
[0015] The startup code of the chip under test is used to control the chip under test to start from the second startup space of the chip under test storage space, and obtain the test program corresponding to the chip under test from the second test code space of the chip under test storage space.
[0016] In one embodiment, the communication test protocol between the test main chip and different modules under test of the chip under test is the same, and the test protocol includes at least one of a write test protocol, a read test protocol, a configuration test protocol, and a test enable test protocol.
[0017] In a second aspect, the present application further provides a chip verification system, the chip verification system comprising:
[0018] Test host;
[0019] The chip test board mentioned above, the chip test board communicates with the test host;
[0020] The chip testing board is used to download the testing program from the testing host.
[0021] In a third aspect, the present application further provides a chip testing system, the chip testing system comprising:
[0022] The chip verification system mentioned above;
[0023] A server, the server communicating with the chip verification system;
[0024] at least one development terminal, the at least one development terminal being in communication with the server, and the at least one development terminal being used to upload a test program to the server;
[0025] The server is used for processing the test program and sending the processed test program to the chip verification system.
[0026] In a fourth aspect, the present application further provides a chip testing method, which is applied to the above-mentioned chip testing board; the testing method comprises:
[0027] The FPGA chip reads a test program corresponding to the FPGA chip based on the startup code of the FPGA chip;
[0028] The chip under test obtains the test program of the chip under test based on the startup code of the chip under test;
[0029] The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain the test results.
[0030] In one embodiment, the testing method further comprises:
[0031] The FPGA chip downloads the startup code of the FPGA chip through the download interface;
[0032] The chip under test downloads the startup code of the chip under test through the download interface;
[0033] The test main chip downloads the test program from the test host.
[0034] In one embodiment, the testing method further comprises:
[0035] When the test host confirms that the test program has been updated, the updated test program is downloaded through the test host, and the updated test program is downloaded to the storage space of the chip test board;
[0036] Before the FPGA chip reads the test program corresponding to the FPGA chip based on the startup code of the FPGA chip, the method further includes:
[0037] Resetting the FPGA chip;
[0038] Before the chip under test acquires the test program of the chip under test based on the startup code of the chip under test, the method further includes:
[0039] Reset the chip under test.
[0040] In one embodiment, downloading the updated test program to the storage space of the chip test board includes:
[0041] In the case where the updated test program is a test program for the FPGA chip, storing the updated test program in the FPGA chip storage space;
[0042] In the case where the updated test program is the test program of the chip to be tested, the updated test program is stored in the storage space of the chip to be tested.
[0043] In one embodiment, the test main chip, the FPGA chip, and the chip to be tested respectively execute the test program to obtain the test result, including:
[0044] Based on a unified communication test protocol and the test program, communication between the test main chip and the chip to be tested is realized through the FPGA chip;
[0045] The test results are obtained based on the communication data.
[0046] The above-mentioned chip test board, chip verification system, chip test system and chip testing method, the chip test board includes a chip to be tested, a socket plug-in, an FPGA chip and a test main chip, and the introduction of the socket plug-in makes it possible to freely switch the type of the inserted chip to be tested, and a set of environments can verify different chips, saving costs. In addition, the test main chip is connected to the chip to be tested through the FPGA chip, and the FPGA chip and the chip to be tested both include startup codes, so that the FPGA chip and the chip to be tested can be started based on the startup code to obtain the corresponding test program, and then realize the test. The startup of the FPGA chip and the chip to be tested and the update of the test program are separated, and no additional configuration environment is required, etc., saving costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0048] FIG1 is a schematic diagram of a test system in one embodiment;
[0049] FIG2 is a schematic diagram of a chip verification system in one embodiment;
[0050] FIG3 is a schematic diagram of a chip testing board in one embodiment;
[0051] FIG4 is a distribution diagram of storage space in one embodiment;
[0052] FIG5 is a schematic diagram of a general test instruction setting in one embodiment;
[0053] FIG6 is a schematic diagram of a flow chart of a chip testing method in one embodiment;
[0054] FIG. 7 is a schematic flow chart of a chip testing method in another embodiment. DETAILED DESCRIPTION
[0055] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0056] A chip testing system provided in an embodiment of the present application includes a chip verification system, a server and at least one development terminal; wherein at least one development terminal communicates with the server, and at least one development terminal is used to upload a test program to the server, and the server communicates with the chip verification system, and the server is used to process the test program and send the processed test program to the chip verification system.
[0057] Specifically, as shown in FIG1 , the local development environment represents different developers. Different developers modify their own codes locally and then upload them to the server. The server processes the codes and finally generates test codes and passes them to the chip verification system. The server processes the codes including checking, compiling, merging into the library, etc., which are not specifically limited here.
[0058] Specifically, in conjunction with FIG. 2, FIG. 2 is a schematic diagram of a chip verification system in an embodiment, in which the chip verification system includes a test host and a chip test board, the test host and the chip test board communicate with each other, wherein the test host can communicate with the debugging circuit through a USB connection, and then connect to the test main chip. The test host is used to download the test program from the server, and the chip test board is used to download the test program from the test host.
[0059] In addition, the present application can also introduce the combination of jenkies integrated tools and automated scripts, and with the system deployment, it can realize the rapid verification of developers developing, testing, and producing reports at the same time. For example, jenkies mainly uploads the developer content, and then triggers the compilation check through the script file. The subsequent test host updates the new code to the chip test board through instructions.
[0060] Optionally, at least one development terminal and a test host may be a computer device, and the computer device may be a terminal. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.
[0061] Those skilled in the art will appreciate that the limitation on the structure of the computer device in the above embodiments is merely a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than the computer device in the above embodiments, or combine certain components, or have a different arrangement of components.
[0062] Specifically, in combination with FIG. 3 , FIG. 3 is a schematic diagram of a chip test board in an embodiment. In this embodiment, the chip test board includes a chip to be tested, a socket plug-in, an FPGA chip, a test main chip, and a download interface.
[0063] The chip to be tested is placed in the socket plug-in, and the FPGA is connected to the chip to be tested through the socket plug-in; the test main chip communicates with the test host and is connected to the chip to be tested through the FPGA chip, and the download interface is connected to the FPGA chip and the chip to be tested respectively.
[0064] Optionally, the test main chip combines a USB and UART interface, and the test host can directly communicate with the test main chip via USB to update the test program.
[0065] The main function of the FPGA chip is a MUX chip. By writing code, the test pins of the test main chip can be directly connected to the chip to be tested, and the FPGA chip is connected to the socket plug-in, which ensures from the hardware that the FPGA chip can be connected to different chips to be tested. And as a programmable array, the FPGA chip can write different test codes according to different chips to be tested. The combination of these two makes this chip test board suitable for testing most of the different chips to be tested in terms of software and hardware.
[0066] The download interface is used to download the startup code of the FPGA chip and the chip to be tested. The startup code bootloader is added to both the FPGA chip and the chip to be verified, so that they can be started from the storage space norflash. That is, the FPGA chip is used to start from the storage space norflash based on the startup code of the FPGA chip to obtain the test program corresponding to the FPGA chip, and the chip to be tested is used to start from the storage space norflash based on the startup code of the chip to be tested to obtain the test program of the chip to be tested.
[0067] In this way, the test main chip, FPGA chip and chip under test respectively execute the test program to obtain the test results. The test program of the FPGA chip is mainly used to realize the communication between the test main chip and the chip under test, and the test program of the chip under test is used to respond to the test instructions of the test main chip.
[0068] In other embodiments, the chip testing board may further include other circuits, such as clock and power supply circuits.
[0069] The above-mentioned chip test board includes a chip to be tested, an FPGA chip and a test main chip, and the FPGA chip is connected to a socket plug-in, so that the purpose of freely switching the chip to be tested can be achieved by inserting different chips to be tested through the socket plug-in. One set of environment can verify different chips, saving costs. In addition, the test main chip is connected to the chip to be tested through the FPGA chip, and the FPGA chip and the chip to be tested both include startup code, so that the FPGA chip and the chip to be tested can be started based on the startup code to obtain the corresponding test program, and then realize the test. The startup of the FPGA chip and the chip to be tested and the update of the test program are separated, and no additional configuration environment is required, etc., saving costs.
[0070] In one of the optional embodiments, the chip testing board also includes: a storage module, the storage module is used to store the test program downloaded by the test host, and the storage module includes an FPGA chip storage space and a chip to be tested storage space; the startup code of the FPGA chip is used to control the FPGA chip to start from the first startup space of the FPGA chip storage space, and obtain the test program corresponding to the FPGA chip from the first test code space of the FPGA chip storage space; the startup code of the chip to be tested is used to control the chip to be tested to start from the second startup space of the chip to be tested storage space, and obtain the test program corresponding to the chip to be tested from the second test code space of the chip to be tested storage space.
[0071] As shown in FIG. 4, FIG. 4 is a distribution diagram of a storage space in an embodiment, and the storage space includes an FPGA chip storage space and a chip to be tested storage space; wherein the FPGA chip storage space includes a first startup space and a first test code space. The chip to be tested storage space includes a second startup space and a second test code space. In addition, the FPGA chip storage space and the chip to be tested storage space also each include some corresponding check areas and update areas, etc. For example, the FPGA chip storage space also includes FPGA check bytes, the starting address of the FPGA startup code, the length occupied by the FPGA startup code, the FPGA startup code checksum, the starting address of the FPGA test code, the length occupied by the FPGA test code, the FPGA test code checksum, the FPGA update flag, and the FPGA reserved area. The corresponding chip to be tested storage space also includes the chip to be tested check bytes, the starting address of the chip to be tested startup code, the length occupied by the chip to be tested startup code, the chip to be tested startup code checksum, the chip to be tested test code starting address, the length occupied by the chip to be tested test code, the chip to be tested test code checksum, the chip to be tested update flag, the chip to be tested reserved area, etc.
[0072] The update flag is used to indicate whether the test main chip has updated the corresponding FPGA test program or the test program of the chip under test, so as to facilitate the FPGA chip and the chip under test to read the new test program.
[0073] In this embodiment, the bootloader of the FPGA startup code needs to capture the test code of the first test code space of the FPGA in the storage space norflash to upgrade the test code of the FPGA chip.
[0074] The bootloader of the chip under test needs to fetch the test code of the second test code space of the chip under test in the storage space norflash to upgrade the test code of the chip under test.
[0075] In the above embodiment, based on the space configuration of the storage space norflash, it is not necessary to use a specific tool such as j-link to update the code of the FPGA chip and the chip to be tested every time, thus saving time.
[0076] In some optional embodiments, the communication test protocol between the test main chip and different modules under test of the chip under test is the same, and the test protocol includes at least one of a write test protocol, a read test protocol, a configuration test protocol, and a test enable test protocol.
[0077] In order to be applicable to different test main chips and chips to be tested, the present application stipulates the communication test protocol between the test main chip and different modules to be tested of the chip to be tested. The communication test protocol between the test main chip and different modules to be tested of the chip to be tested is the same, and only one interface can be used. The difference lies in the different starting bytes, such as UART or I2C, representing different modules to be tested.
[0078] Specifically, in combination with Figure 5, Figure 5 is a schematic diagram of a general test instruction setting in an embodiment. In this embodiment, the communication test protocols of different modules to be tested are the same. The modules to be tested include UART, I2C, SPI, CAN, USB, GPIO, SAI, MDIO and ETH, etc. Each test module includes 4 test modes, and the 4 test modes include a write test mode, a read test mode, a configuration test mode and a test-on test mode, which correspond to the write test protocol, the read test protocol, the configuration test protocol and the test-on test protocol, respectively.
[0079] For ease of understanding, the test protocol is illustrated with an example. For example, UART write 0 data:0 means writing data 0 through the UART0 interface, and CAN read 1 lens:8 means reading data with a length of 8 through CAN1.
[0080] In the above embodiment, a custom communication protocol is introduced so that all test items have a unified interface. Even if the chip is replaced, there is no need to update the test main chip code, and the compatibility is stronger.
[0081] In an exemplary embodiment, as shown in FIG6 , a chip testing method is provided, which is described by taking the method applied to the chip testing board in FIG3 as an example, and includes the following steps 602 to 606. Among them:
[0082] S602: The FPGA chip reads a test program corresponding to the FPGA chip based on the startup code of the FPGA chip.
[0083] The FPGA chip is started from the storage space based on the startup code of the FPGA chip, so that the test program corresponding to the FPGA chip can be obtained for subsequent testing.
[0084] S604: The chip under test obtains a test program of the chip under test based on the startup code of the chip under test.
[0085] The chip under test is started from the storage space based on the startup code of the chip under test, so that the test program corresponding to the chip under test can be obtained to facilitate subsequent testing.
[0086] S606: The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain the test results.
[0087] The test main chip, FPGA chip and chip under test respectively execute the test program to obtain the test results. The test program of the FPGA chip is mainly used to realize the communication between the test main chip and the chip under test, and the test program of the chip under test is used to respond to the test instructions of the test main chip.
[0088] The above-mentioned chip testing method, the chip testing board includes a chip to be tested, an FPGA chip and a test main chip, the FPGA chip is connected to a socket plug-in, so that the type of chip to be tested inserted into the socket plug-in can be switched, and one set of environments can verify different chips, saving costs. In addition, the test main chip is connected to the chip to be tested through the FPGA chip, and the FPGA chip and the chip to be tested both include startup codes, so that the FPGA chip and the chip to be tested can be started based on the startup code to obtain the corresponding test program, and then the test is realized. The startup of the FPGA chip and the chip to be tested and the update of the test program are separated, and no additional configuration environment is required, etc., saving costs.
[0089] In one of the optional embodiments, the testing method also includes: the FPGA chip downloads the startup code of the FPGA chip through the download interface; the chip to be tested is used to download the startup code of the chip to be tested through the download interface; and the test main chip is used to download the test program from the test host.
[0090] Before starting the test, the test is initialized first, and the FPGA chip and the chip under test download the corresponding startup code through the download interface, and the corresponding startup code is stored in the internal storage area of the FPGA chip and the chip under test. The test master chip downloads the test program from the test host through the USB and stores it in the storage space, wherein the test master chip stores the test program in the corresponding part of the storage space based on the type of the test program.
[0091] In one of the optional embodiments, the testing method also includes: when the testing host confirms that there is an update to the test program, downloading the updated test program through the testing host, and downloading the updated test program to the storage space of the chip testing board; before the FPGA chip reads the test program corresponding to the FPGA chip based on the startup code of the FPGA chip, it also includes: resetting the FPGA chip; before the chip to be tested obtains the test program of the chip to be tested based on the startup code of the chip to be tested, it also includes: resetting the chip to be tested.
[0092] Among them, during the test process, the test host confirms whether there is an update to the test program, that is, whether the server has updated the test program on the library. The specific update process is that each R&D terminal uploads the test program, Jenkins compiles the code, and then updates it to the library. After confirming that the test program on the library is updated, the server sends the updated test program to the test host. The test host sends the test program to the test main chip through the debugging interface, and the test main chip stores the test program to the corresponding location of the storage space.
[0093] In one of the optional embodiments, the updated test program is downloaded to the storage space of the chip test board, including: when the updated test program is a test program for the FPGA chip, the updated test program is stored in the FPGA chip storage space; when the updated test program is a test program for the chip to be tested, the updated test program is stored in the storage space of the chip to be tested. The specific storage space distribution can be seen in Figure 4 above, which will not be repeated here.
[0094] After the test program is stored, the FPGA chip and / or the chip to be tested is reset. After the test main chip stores the test program to the corresponding position of the storage space, if the test program of the FPGA chip is updated, the corresponding update flag in the storage space changes, and if the test program of the chip to be tested is updated, the corresponding update flag in the storage space changes. Therefore, in this embodiment, the FPGA chip and the chip to be tested can be reset every time, or the FPGA chip or the chip to be tested can be reset based on the update flag.
[0095] In one of the optional embodiments, the test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain the test results, including: based on a unified communication test protocol and a test program, realizing the communication between the test main chip and the chip to be tested through the FPGA chip; and obtaining the test results based on the communication data.
[0096] The communication between the test main chip and the chip to be tested can be tested based on a unified communication test protocol and test program.
[0097] For example, when testing the I2C slave mode, you need to first send instructions to the chip under test to make it enter the slave mode, then send instructions to the test master chip to make it enter the master mode, and then send instructions to the test master chip to make it send I2C data. If the chip under test receives the I2C data and the received data is the same as the sent data, the test passes. The test steps for other modules are similar.
[0098] For ease of understanding, combined with Figure 7, Figure 7 is a flow chart of a chip testing method in another embodiment. Before the test starts, initialization is performed, and the FPGA chip downloads the startup code of the FPGA chip through the download interface; the chip to be tested downloads the startup code of the chip to be tested through the download interface; and the test master chip downloads the test program from the test host.
[0099] The test host determines whether the test code is updated, where the update of the test code refers to whether the server has updated the test program on the library. The specific update process is that each R&D terminal uploads the test program, Jenkins compiles the code, and then updates it to the library. After confirming that the test program on the library has been updated, the server sends the updated test program to the test host; after the test host confirms that the test program has been updated, the test host sends the test program to the test main chip through the debugging interface, and the test main chip stores the test program to the corresponding location in the storage space.
[0100] Reset the FPGA chip and the chip under test so that the FPGA chip and the chip under test can capture the updated code from the storage space noflash and enter the test program.
[0101] Then start testing, for example, test the I2C module first, then test the UART module, and so on, until all modules to be tested are tested, generate a test report, and send the test report to the terminal of the relevant test developer.
[0102] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0103] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.
[0104] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A chip testing board, characterized in that: The chip testing board comprises: Chip to be tested; A socket plug-in, wherein the chip to be tested is placed in the socket plug-in; FPGA chip, the FPGA chip is connected to the chip to be tested through the socket plug-in; A test main chip, the test main chip communicates with the test host and is connected to the chip to be tested through the FPGA chip; the test main chip is used to download the test program from the test host; A download interface, the download interface is connected to the FPGA chip and the chip to be tested respectively, and the download interface is used to download the startup code of the FPGA chip and the chip to be tested; The FPGA chip is used to obtain a test program corresponding to the FPGA chip based on the startup code of the FPGA chip, and the chip to be tested is used to obtain a test program for the chip to be tested based on the startup code of the chip to be tested. The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain a test result.
2. The chip testing board according to claim 1, characterized in that: The chip testing board also includes: A storage module, the storage module is used to store the test program downloaded by the test host, and the storage module includes the FPGA chip storage space and the chip to be tested storage space; The startup code of the FPGA chip is used to control the FPGA chip to start from the first startup space of the FPGA chip storage space, and obtain the test program corresponding to the FPGA chip from the first test code space of the FPGA chip storage space; The startup code of the chip under test is used to control the chip under test to start from the second startup space of the chip under test storage space, and obtain the test program corresponding to the chip under test from the second test code space of the chip under test storage space.
3. The chip testing board according to claim 1, characterized in that: The communication test protocols between the test master chip and different modules under test of the chip under test are the same, and the test protocol includes at least one of a write test protocol, a read test protocol, a configuration test protocol and a test start test protocol.
4. A chip verification system, characterized in that: The chip verification system comprises: Test host; The chip testing board according to any one of claims 1 to 3, wherein the chip testing board communicates with the testing host; The chip testing board is used to download the testing program from the testing host.
5. A chip testing system, characterized in that: The chip testing system comprises: The chip verification system as claimed in claim 4; A server, the server communicating with the chip verification system; at least one development terminal, the at least one development terminal being in communication with the server, and the at least one development terminal being used to upload a test program to the server; The server is used for processing the test program and sending the processed test program to the chip verification system.
6. A chip testing method, characterized in that: The chip testing method is applied to the chip testing board according to any one of claims 1 to 3; The test method includes: The FPGA chip reads a test program corresponding to the FPGA chip based on the startup code of the FPGA chip; The chip under test obtains the test program of the chip under test based on the startup code of the chip under test; The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain the test results.
7. The method according to claim 6, characterized in that The test method also includes: The FPGA chip downloads the startup code of the FPGA chip through the download interface; The chip under test downloads the startup code of the chip under test through the download interface; The test main chip downloads the test program from the test host.
8. The method according to claim 7, characterized in that The test method also includes: When the test host confirms that the test program has been updated, the updated test program is downloaded through the test host, and the updated test program is downloaded to the storage space of the chip test board; Before the FPGA chip reads the test program corresponding to the FPGA chip based on the startup code of the FPGA chip, the method further includes: Resetting the FPGA chip; Before the chip under test acquires the test program of the chip under test based on the startup code of the chip under test, the method further includes: Reset the chip under test.
9. The testing method according to claim 8, characterized in that: The step of downloading the updated test program to the storage space of the chip test board includes: In the case where the updated test program is a test program for the FPGA chip, storing the updated test program in the FPGA chip storage space; In the case where the updated test program is the test program of the chip to be tested, the updated test program is stored in the storage space of the chip to be tested.
10. The testing method according to claim 6, characterized in that: The test main chip, the FPGA chip and the chip to be tested respectively execute the test program to obtain the test result, including: Based on a unified communication test protocol and the test program, communication between the test main chip and the chip to be tested is realized through the FPGA chip; The test results are obtained based on the communication data.