Multi-channel radar synchronous time service method and system based on FPGA

Abstract

The invention relates to a multi-channel radar synchronous time service method and system based on an FPGA, and the method comprises the steps: outputting a precise clock signal through the FPGA based on reference time; according to the precise clock signal, respectively calculating clock pulses corresponding to frequencies required by a plurality of channels of the radar to be subjected to time service; extracting pulse interrupt signals of a plurality of channels of the radar to be subjected to time service; and on the basis of the pulse interruption signal, transmitting the clock pulse difference to the radar to be subjected to time service so as to complete multichannel radar synchronous time service. According to the invention, the clock time service precision can be greatly improved, and multi-channel synchronous time service can be satisfied based on the parallel characteristic of the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of radar control technology, and in particular to a multi-channel radar synchronous timing method and system based on FPGA. Background Art

[0002] In the design of embedded computer systems, the control of high-precision devices such as radars often requires very accurate clock synchronization. Common clock synchronization schemes use timing methods controlled by microcontrollers or DSPs, which are limited to the serial working mode of the main processor. The timing method often uses a chip internal timer plus interrupt design. For multi-channel timing, due to factors such as interrupts have priority and processing interrupts takes time, it is often unable to meet the radar equipment's requirements for clock synchronization and rigor. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention provides a multi-channel radar synchronization timing method and system based on FPGA.

[0004] The present invention provides a multi-channel radar synchronization timing method based on FPGA, comprising:

[0005] S1: Based on the reference time, output the precise clock signal through FPGA;

[0006] S2: Calculate clock pulses corresponding to the frequencies required by multiple channels of the radar to be timed according to the precise clock signal;

[0007] S3: extracting pulse interruption signals of multiple channels of the radar to be timed;

[0008] S4: Based on the pulse interruption signal, the clock pulse is differentially transmitted to the radar to be timed, so as to complete the synchronous timing of the multi-channel radar.

[0009] According to a multi-channel radar synchronization timing method based on FPGA provided by the present invention, step S1 further comprises:

[0010] S11: Initialize the FPGA;

[0011] S12: Acquire a reference time through the FPGA;

[0012] S13: The phase-locked loop in the FPGA outputs the reference time.

[0013] According to a multi-channel radar synchronization timing method based on FPGA provided by the present invention, step S3 further includes:

[0014] S31: Detecting the rising edge of the radar to be timed;

[0015] S32: extracting pulse interruption information from the rising edge;

[0016] S33: Based on a preset serial interrupt protocol, convert the pulse terminal information into a pulse interrupt signal.

[0017] According to the FPGA-based multi-channel radar synchronization timing method provided by the present invention, the serial interrupt protocol in step S33 is the LPC serial terminal protocol.

[0018] According to a multi-channel radar synchronization timing method based on FPGA provided by the present invention, step S4 further comprises:

[0019] S41: receiving the clock pulse to obtain a TTL signal;

[0020] S42: Convert the TTL signal into a high-speed differential signal;

[0021] S43: Based on the pulse interruption signal, the high-speed differential signal is sent to the radar to be timed through the VPX interface.

[0022] The present invention also provides a FPGA-based multi-channel radar synchronization timing system, which is used to execute the FPGA-based multi-channel radar synchronization timing method as described in any one of the above items, including:

[0023] Clock module: used to provide reference time;

[0024] FPGA module: used to output a precise clock signal based on the reference time, and to calculate the clock pulses corresponding to the frequencies required by the multiple channels of the radar to be timed according to the precise clock signal, and to extract the pulse interruption signals of the multiple channels of the radar to be timed;

[0025] Differential transmission module: used for differentially transmitting the clock pulse to the VPX interface module;

[0026] VPX interface module: used for sending the received clock pulse to the radar to be timed based on the pulse interrupt signal.

[0027] According to a multi-channel radar synchronization timing system based on FPGA provided by the present invention, the FPGA module specifically includes:

[0028] PLL unit: used to receive the reference time provided by the clock module and convert the reference time into a precise clock signal;

[0029] Clock pulse unit: used to calculate the clock pulses corresponding to the frequencies required by multiple channels of the radar to be timed according to the precise clock signal output by the PLL unit;

[0030] Interrupt arbitration unit: used to extract pulse interrupt information of multiple channels of the radar to be timed;

[0031] Interrupt protocol unit: used to write the pulse interrupt information extracted by the interrupt arbitration unit into the interrupt number to obtain a pulse interrupt signal.

[0032] According to a multi-channel radar synchronous timing system based on FPGA provided by the present invention, the clock pulse unit specifically includes:

[0033] A plurality of parallel clock pulse sub-units, wherein the plurality of clock pulse sub-units respectively correspond to the plurality of channels of the radar to be timed, and are used to respectively extract the required frequencies of the plurality of channels and calculate the clock pulses of the corresponding channels.

[0034] According to the FPGA-based multi-channel radar synchronous timing system provided by the present invention, the differential mode transmission module is a MAX488 chip.

[0035] According to the FPGA-based multi-channel radar synchronous timing system provided by the present invention, the VPX interface module is a 3UVPX connector.

[0036] The present invention provides a method and system for synchronous timing of a multi-channel radar based on FPGA. Through a phase-locked loop circuit, a high-precision clock signal is output to ensure that the time synchronization accuracy of the multi-channel radar system meets the requirements, which is crucial for improving the detection accuracy and positioning accuracy of the radar system. In addition, FPGA has programmability and can be flexibly configured according to the specific needs of the radar system. Secondly, high-speed differential signals are used for transmission, which can significantly reduce the attenuation and interference of the signal during the transmission process, and improve the reliability and stability of the signal. In general, the present invention uses FPGA as the main control, which can improve the clock accuracy based on the PLL IP core, and multiple clock channels can be independently timed, which can further improve the timing accuracy. The parallelism of FPGA also realizes the synchronization of timing of multiple clock channels.

[0037] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1It is a schematic flow chart of a multi-channel radar synchronization timing method based on FPGA provided by an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the structure of a multi-channel radar synchronous timing system based on FPGA provided by an embodiment of the present invention;

[0041] Figure 3 The present invention provides a schematic diagram of the FPGA module structure in a FPGA-based multi-channel radar synchronous timing system.

[0042] Reference numerals:

[0043] 100, clock module; 200, FPGA module; 300, differential transmission module; 400, VPX interface module;

[0044] 210, PLL unit; 220, clock pulse unit; 230, interrupt arbitration unit; 240, interrupt protocol unit. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0046] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0047] Combine the following Figures 1 to 3 Embodiments of the present invention are described.

[0048] like Figure 1 As shown, the present invention provides a multi-channel radar synchronization timing method based on FPGA, comprising:

[0049] S1: Based on the reference time, the precise clock signal is output through the FPGA.

[0050] In step S1, the host is first powered on, the clock module provides the working clock to the FPGA module, the FPGA module starts working, and the PLL unit (phase-locked loop circuit) in the FPGA module outputs a precise clock signal.

[0051] Wherein, step S1 further comprises:

[0052] S11: Initialize the FPGA;

[0053] S12: Acquire a reference time through the FPGA;

[0054] S13: The phase-locked loop in the FPGA outputs the reference time.

[0055] In steps S11 to S13, after the FPGA is initialized, a reference time is obtained from an external time source, such as an atomic clock, a GPS timing system, or other high-precision clock. The FPGA communicates with a clock module with an external time source through its interface (UART in this embodiment) to obtain current time information.

[0056] Subsequently, the FPGA obtains the reference time and uses the internal phase-locked loop (PLL) circuit to output the reference time. The PLL is a circuit that can lock and track the frequency and phase of the input signal. It can match the input signal by adjusting the frequency and phase of its output signal. In the FPGA, the PLL is usually used to generate a clock signal. By adjusting the parameters of the PLL, the FPGA can output a clock signal that is precisely synchronized with the reference time and has the required frequency and stability.

[0057] S2: According to the precise clock signal, respectively calculate the clock pulses corresponding to the frequencies required by the multiple channels of the radar to be timed.

[0058] First, each radar channel has its own specific operating frequency requirements, based on the radar system's target detection requirements, signal processing algorithms, and radar waveform characteristics. Therefore, when designing a radar system, it is necessary to clarify the clock frequency required for each channel.

[0059] Therefore, in step S2, multiple clock pulse units are configured accordingly according to the frequency requirements of the radar channel, such as clock pulse unit A, unit B and unit C, and then the required clock pulses are calculated and generated through the above units.

[0060] The specific process is to first receive the clock source as input, and then the internal PLL (phase-locked loop) will divide or multiply the input clock source according to the configuration parameters to generate the required output frequency. If necessary, the phase of the generated clock pulses can also be adjusted to ensure that they are synchronized with other parts of the radar system.

[0061] S3: Extract the pulse interruption signals of multiple channels of the radar to be timed.

[0062] Wherein, step S3 further comprises:

[0063] S31: Detecting the rising edge of the radar to be timed;

[0064] S32: extracting pulse interruption information from the rising edge;

[0065] S33: Based on a preset serial interrupt protocol, convert the pulse terminal information into a pulse interrupt signal.

[0066] Wherein, the serial interrupt protocol in step S33 is the LPC serial terminal protocol.

[0067] While calculating the clock pulse in step S2, it is also necessary to detect the rising edge of each channel pulse, extract the clock pulse interrupt information, and transmit each channel interrupt information to the high-speed serial interrupt protocol unit. The high-speed serial interrupt protocol unit writes the channel interrupt information into the corresponding interrupt number according to the LPC serial interrupt protocol and outputs it.

[0068] In steps S31 to S33, the system needs to monitor the signal output of the radar to be timed, especially the rising edge of the signal. The rising edge refers to the process in which the signal changes rapidly from a low level (usually 0V or close to 0V) to a high level (usually a positive voltage value, such as 3.3V or 5V).

[0069] The specific steps for extracting pulse interrupt information are as follows: first, record the time point when the rising edge occurs and obtain a timestamp. Then, based on the detection of the rising edge, the system generates an interrupt signal. The actual interrupt signal is a level change, or a complex signal containing more information (such as event type, timestamp, etc.). The pulse interrupt information is then encapsulated into a data packet or message for subsequent transmission.

[0070] S4: Based on the pulse interruption signal, the clock pulse is differentially transmitted to the radar to be timed, so as to complete the synchronous timing of the multi-channel radar.

[0071] Wherein, step S4 further comprises:

[0072] S41: receiving the clock pulse to obtain a TTL signal;

[0073] S42: Convert the TTL signal into a high-speed differential signal;

[0074] S43: Based on the pulse interruption signal, the high-speed differential signal is sent to the radar to be timed through the VPX interface.

[0075] In step S4, the aforementioned clock pulse A unit, clock pulse B unit and clock pulse C unit send the output timing pulses, convert the TTL single-ended signal into a high-speed differential signal, and forward the signal to the VPX interface module, and send it to the long-distance radar equipment through the VPX interface module, thereby completing the synchronous timing of the radar multi-channel.

[0076] like Figure 2 As shown, the present invention also provides a multi-channel radar synchronization timing system based on FPGA, comprising:

[0077] Clock module 100: used to provide reference time.

[0078] FPGA module 200: used to output a precise clock signal based on a reference time, and to calculate clock pulses corresponding to the frequencies required for multiple channels of the radar to be timed according to the precise clock signal, and also used to extract pulse interruption signals of multiple channels of the radar to be timed.

[0079] like Figure 3 As shown, the FPGA module 200 specifically includes:

[0080] The PLL unit 210 is configured to receive the reference time provided by the clock module 100 and convert the reference time into a precise clock signal.

[0081] The clock pulse unit 220 is used to calculate the clock pulses corresponding to the frequencies required by the multiple channels of the radar to be timed according to the precise clock signal output by the PLL unit 210.

[0082] The clock pulse unit 220 specifically includes:

[0083] A plurality of parallel clock pulse sub-units, wherein the plurality of clock pulse sub-units respectively correspond to the plurality of channels of the radar to be timed, and are used to respectively extract the required frequencies of the plurality of channels and calculate the clock pulses of the corresponding channels.

[0084] The interrupt arbitration unit 230 is used to extract the pulse interrupt information of multiple channels of the radar to be timed.

[0085] The interrupt protocol unit 240 is used to write the pulse interrupt information extracted by the interrupt arbitration unit 230 into the interrupt number to obtain a pulse interrupt signal.

[0086] Furthermore, the FPGA module includes an interrupt protocol unit, a PLL unit, an interrupt arbitration unit and multiple clock pulse sub-units, wherein the interrupt protocol unit is connected to the interrupt arbitration unit, the interrupt protocol unit is connected to the PLL unit, the PLL unit is connected to the interrupt arbitration unit, the PLL unit is respectively connected to the multiple clock pulse sub-units, and the serial interrupt unit is respectively connected to the multiple clock pulse sub-units.

[0087] The differential transmission module 300 is used to differentially transmit the clock pulse to the VPX interface module 400 .

[0088] VPX interface module 400: used for sending the received clock pulse to the radar to be timed based on the pulse interruption signal.

[0089] Furthermore, the above-mentioned VPX interface module adopts a domestically produced 3UVPX connector, the differential transmission module adopts a MAX488 chip, and the clock module adopts a domestically produced 50M crystal oscillator.

[0090] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel radar synchronization timing method based on FPGA, characterized in that: include: S1: Based on the reference time, output the precise clock signal through FPGA; S2: Calculate clock pulses corresponding to the frequencies required by multiple channels of the radar to be timed according to the precise clock signal; S3: extracting pulse interruption signals of multiple channels of the radar to be timed; S4: Based on the pulse interruption signal, the clock pulse is differentially transmitted to the radar to be timed, so as to complete the synchronous timing of the multi-channel radar.

2. A multi-channel radar synchronization timing method based on FPGA according to claim 1, characterized in that: Step S1 further comprises: S11: Initialize the FPGA; S12: Acquire a reference time through the FPGA; S13: The phase-locked loop in the FPGA outputs the reference time.

3. A multi-channel radar synchronization timing method based on FPGA according to claim 1, characterized in that: Step S3 further comprises: S31: Detecting the rising edge of the radar to be timed; S32: extracting pulse interruption information from the rising edge; S33: Based on a preset serial interrupt protocol, convert the pulse terminal information into a pulse interrupt signal.

4. The FPGA-based multi-channel radar synchronization timing method according to claim 3, characterized in that: The serial interrupt protocol in step S33 is the LPC serial terminal protocol.

5. The FPGA-based multi-channel radar synchronization timing method according to claim 1, characterized in that: Step S4 further comprises: S41: receiving the clock pulse to obtain a TTL signal; S42: Convert the TTL signal into a high-speed differential signal; S43: Based on the pulse interruption signal, the high-speed differential signal is sent to the radar to be timed through the VPX interface.

6. A multi-channel radar synchronization timing system based on FPGA, used to execute the multi-channel radar synchronization timing method based on FPGA as claimed in any one of claims 1 to 5, characterized in that: include: Clock module: used to provide reference time; FPGA module: used to output a precise clock signal based on the reference time, and to calculate the clock pulses corresponding to the frequencies required by the multiple channels of the radar to be timed according to the precise clock signal, and to extract the pulse interruption signals of the multiple channels of the radar to be timed; Differential transmission module: used for differentially transmitting the clock pulse to the VPX interface module; VPX interface module: used for sending the received clock pulse to the radar to be timed based on the pulse interrupt signal.

7. The FPGA-based multi-channel radar synchronous timing system according to claim 6, characterized in that: The FPGA module specifically includes: PLL unit: used to receive the reference time provided by the clock module and convert the reference time into a precise clock signal; Clock pulse unit: used to calculate the clock pulses corresponding to the frequencies required by multiple channels of the radar to be timed according to the precise clock signal output by the PLL unit; Interrupt arbitration unit: used to extract pulse interrupt information of multiple channels of the radar to be timed; Interrupt protocol unit: used to write the pulse interrupt information extracted by the interrupt arbitration unit into the interrupt number to obtain a pulse interrupt signal.

8. The FPGA-based multi-channel radar synchronous timing system according to claim 7, characterized in that: The clock pulse unit specifically comprises: A plurality of parallel clock pulse sub-units, wherein the plurality of clock pulse sub-units respectively correspond to the plurality of channels of the radar to be timed, and are used to respectively extract the required frequencies of the plurality of channels and calculate the clock pulses of the corresponding channels.

9. The FPGA-based multi-channel radar synchronous timing system according to claim 6, characterized in that: The differential mode transmission module is a MAX488 chip.

10. The FPGA-based multi-channel radar synchronous timing system according to claim 6, characterized in that: The VPX interface module is a 3UVPX connector.

Images