Current limiting precision calibration method of current limiting switch

Abstract

The invention discloses a current-limiting precision calibration method of a current-limiting switch, which is applied to a current-limiting precision calibration circuit, the current-limiting precision calibration circuit comprises a mirror image circuit, a current-to-voltage module and an overcurrent comparison module, the mirror image circuit is electrically connected with a charge pump, and the current-to-voltage module is electrically connected with the charge pump. The ratio of current I0 of the input end of the mirror image circuit to current I3 of the output end of the mirror image circuit is P (I3 = I0 / P), the current-to-voltage module is used for converting internal reference current I4 and current I3 into corresponding voltage V4 and voltage V3 respectively, and the overcurrent comparison module is used for comparing the voltage V4 with the voltage V3. According to the method, on the basis of two-point method trimming, the trimming mirror image proportion P is increased, and the precision of the actual chip working large-current current limiting value is remarkably improved through small-current trimming.

Description

Technical Field

[0001] The invention relates to the field of chip technology, and in particular to a current limiting accuracy calibration method for a current limiting switch. Background Art

[0002] With the development of intelligent electrical appliances, product applications have put forward higher requirements on the power consumption and accuracy of chips. During the mass adjustment process, the chip output end cannot directly pull the target current limit value (generally 2 to 6A). The usual practice is to pull a small current through the output end, adjust the small current accurately, and use the linear principle of the circuit to make the output current the target current limit value. However, in the actual circuit architecture design, tape-out, packaging and testing process, non-ideal effects will be introduced, causing deviations in the MOS tube replication ratio and the current limit gear, resulting in a large error between the ideal chip current limit value and the actual current limit value after the adjustment operation. Summary of the invention

[0003] The purpose of the present invention is to solve at least one of the technical problems existing in the prior art and to provide a current limiting accuracy calibration method for a current limiting switch that improves the deviation of a target current limiting value of batch chips.

[0004] A current limiting accuracy calibration method for a current limiting switch according to an embodiment of the present invention is applied to a current limiting accuracy calibration circuit, wherein the current limiting accuracy calibration circuit comprises a mirror circuit, a current-to-voltage module and an overcurrent comparison module, wherein the mirror circuit is electrically connected to a charge pump, wherein the ratio between the current I0 at the input end of the mirror circuit and the current I3 at the output end thereof is P (I3=I0 / P), wherein the current-to-voltage module is used to convert the internal reference current I4 and the current I3 into corresponding voltages V4 and V3 respectively, wherein the overcurrent comparison module is used to compare the magnitudes of the voltage V4 and the voltage V3, and wherein the method comprises the following steps:

[0005] Step 1, adjusting the internal reference current I4 until the voltage V4 is greater than the voltage V3, at which time no overcurrent occurs, and the ratio P of the mirror circuit is recorded as P1;

[0006] Step 2, adjusting the current I0 of the mirror circuit to increase it by one gear P1*Imin, where Imin is the minimum gear current corresponding to the internal reference current I4;

[0007] Step 3, adjust the internal reference current I4 to increase it by one level Imin;

[0008] Step 4, determining whether voltage V4>voltage V3, or voltage V4<voltage V3;

[0009] If voltage V4 < voltage V3, an overcurrent occurs, and step 5 is executed;

[0010] If voltage V4>voltage V3, no overcurrent occurs, and step 6 is executed;

[0011] Step 5, reducing the ratio P of the mirror circuit until no overcurrent occurs, at which time the ratio P is recorded as P2, and writing the value corresponding to P2 into the chip, and executing step 8;

[0012] Step 6, increasing the ratio P of the mirror circuit until overcurrent occurs, at which time the ratio P is recorded as P3, and executing step 7;

[0013] Step 7, reducing the ratio P3 of the mirror circuit by a minimum gear, at which time the ratio P is recorded as P4, and writing the value corresponding to P4 into the chip, and executing step 8;

[0014] Step 8, adjusting the current I0 of the mirror circuit to the actual current limit value I of the chip, increasing the internal reference current I4 by the corresponding level, and completing the adjustment.

[0015] A current limiting accuracy calibration method for a current limiting switch according to an embodiment of the present invention has at least the following beneficial effects: the magnitudes of the internal reference current I4 and the ratio P of the mirror circuit can be adjusted by changing the register value, firstly, the internal reference current I4 is adjusted until the voltage V4 is greater than the voltage V3, at which time no overcurrent occurs, and the ratio P of the mirror circuit at this time is recorded as P1; then, the external input current I0 of the mirror circuit is adjusted first, and then the internal reference current I4 is changed, and then the magnitude relationship between the voltage V4 and the voltage V3 is determined, 1. If the voltage V4 < the voltage V3, it means that an overcurrent occurs, and the ratio P of the mirror circuit needs to be reduced until no overcurrent occurs, and then 1. The external input current I0 of the mirror circuit is adjusted to the actual current limiting value I of the chip, and the internal reference current I4 is increased by the corresponding gear to complete the adjustment; 2. If the voltage V4> the voltage V3 at this time, it means that no overcurrent phenomenon occurs, and the ratio P of the mirror circuit needs to be increased until overcurrent occurs. At this time, the ratio P is recorded as P3; because overcurrent just occurs at this time, it is only necessary to reduce the ratio P3 of the mirror circuit by a minimum gear, so that the current I3 is reduced by a minimum gear current Imin, and it can be adjusted from just overcurrent to just not overcurrent, and then the external input current I0 of the mirror circuit is adjusted to the actual current limiting value I of the chip, and the internal reference current I4 is increased by the corresponding gear to complete the adjustment. That is, the present invention adjusts the mirror ratio P on the basis of the two-point method adjustment, and significantly improves the accuracy of the actual chip working large current limiting value through small current adjustment.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings;

[0018] Figure 1 is a block diagram of a current limiting accuracy calibration circuit;

[0019] Figure 2 It is the schematic diagram of the mirror circuit;

[0020] Figure 3 This is the schematic diagram of the current-to-voltage module;

[0021] Figure 4 This is the schematic diagram of the overcurrent comparison module;

[0022] Figure 5 It is a control flow chart of the current limiting accuracy calibration method. DETAILED DESCRIPTION

[0023] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0024] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0025] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0026] Reference Figures 1 to 5The present invention provides a current limiting accuracy calibration method for a current limiting switch, which is applied to a current limiting accuracy calibration circuit. The current limiting accuracy calibration circuit includes a mirror circuit 10, a current-to-voltage module 20, and an overcurrent comparison module 30. The mirror circuit 10 is electrically connected to a charge pump. The ratio between the current I0 at the input end of the mirror circuit 10 and the current I3 at the output end thereof is P (I3=I0 / P). The current-to-voltage module 20 is used to convert an internal reference current I4 and a current I3 into corresponding voltages V4 and V3, respectively. The overcurrent comparison module 30 is used to compare the magnitudes of the voltages V4 and V3. Figure 5 , the method comprises the following steps:

[0027] Step 1, adjusting the internal reference current I4 until the voltage V4 is greater than the voltage V3, at which time no overcurrent occurs, and the ratio P of the mirror circuit is recorded as P1;

[0028] Step 2, adjusting the current I0 of the mirror circuit to increase it by one gear P1*Imin, where Imin is the minimum gear current corresponding to the internal reference current I4;

[0029] Step 3, adjust the internal reference current I4 to increase it by one level Imin;

[0030] Step 4, determining whether voltage V4>voltage V3, or voltage V4<voltage V3;

[0031] If voltage V4 < voltage V3, an overcurrent occurs, and step 5 is executed;

[0032] If voltage V4>voltage V3, no overcurrent occurs, and step 6 is executed;

[0033] Step 5, reducing the ratio P of the mirror circuit until no overcurrent occurs, at which time the ratio P is recorded as P2, and writing the value corresponding to P2 into the chip, and executing step 8;

[0034] Step 6, increasing the ratio P of the mirror circuit until overcurrent occurs, at which time the ratio P is recorded as P3, and executing step 7;

[0035] Step 7, reducing the ratio P3 of the mirror circuit by a minimum gear, at which time the ratio P is recorded as P4, and writing the value corresponding to P4 into the chip, and executing step 8;

[0036] Step 8, adjusting the current I0 of the mirror circuit to the actual current limit value I of the chip, increasing the internal reference current I4 by the corresponding level, and completing the adjustment.

[0037] In certain embodiments, such as Figure 2As shown, the mirror circuit 10 includes a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a MOS transistor Q5, a MOS transistor Q6, a MOS transistor Q7, a MOS transistor Q8 and a comparator OP1, wherein the MOS transistor Q1 and the MOS transistor Q2 form a first mirror circuit 10, the MOS transistor Q4 and the MOS transistor Q5 form a second mirror circuit 12, the ratio of the first mirror circuit 11 is M, the ratio of the second mirror circuit 12 is N, and the ratio P of the mirror circuit 10 is M*N; the gate of the MOS transistor Q1 and the gate of the MOS transistor Q2 are respectively electrically connected to the charge pump, the drain of the MOS transistor Q1 and the drain of the MOS transistor Q2 are respectively connected to the input voltage VIN, and the source of the MOS transistor Q1 is respectively connected to the comparator O The inverting input terminal of P1 is electrically connected to the source of the MOS transistor Q3, the output terminal of the comparator OP1 is electrically connected to the gate of the MOS transistor Q3, the drain of the MOS transistor Q3 is electrically connected to the gate and drain of the MOS transistor Q4 and the gate of the MOS transistor Q5, the source of the MOS transistor Q4 and the source of the MOS transistor Q5 are grounded, the drain of the MOS transistor Q5 is electrically connected to the source of the MOS transistor Q8, the drain of the MOS transistor Q8 is electrically connected to the gate and drain of the MOS transistor Q6 and the gate of the MOS transistor Q7, the source of the MOS transistor Q6 and the source of the MOS transistor Q7 are connected to the working voltage VCC, the current of the drain of the MOS transistor Q7 is the output current I3, and the current of the source of the MOS transistor Q2 is the input current I0.

[0038] like Figure 3 The overcurrent comparison module 30 includes a comparator CMP, a MOS tube Q9 and a MOS tube Q10. The positive input terminal of the comparator CMP inputs a voltage V4, the reverse input terminal of the comparator CMP inputs a voltage V3, the output terminal of the comparator CMP is respectively electrically connected to the drain and gate of the MOS tube Q9 and the gate of the MOS tube Q10, and is electrically connected to the charge pump. The source of the MOS tube Q9 and the source of the MOS tube Q10 are respectively grounded, and the drain of the MOS tube Q10 is electrically connected to the charge pump. When the voltage V4> the voltage V3, the comparator CMP outputs a low level, so that the charge pump is not pulled down, indicating that no overcurrent occurs at this time; when the voltage V4< the voltage V3, the comparator CMP outputs a high level, so that the charge pump is pulled down, indicating that an overcurrent occurs at this time.

[0039] like Figure 4 The current-to-voltage module 20 includes a resistor R1 and a resistor R2. One end of the resistor R1 is electrically connected to the output end of the mirror circuit 10 to input the output current I3. One end of the resistor R2 inputs the internal reference current I4. The other end of the resistor R1 and the other end of the resistor R2 are grounded respectively. The voltage V3 = I3*R1, and the voltage V4 = I4*R2.

[0040] According to the existing chip technology, both the internal reference current I4 and the ratio P of the mirror circuit 10 can be adjusted by changing the register value, thereby changing the magnitude of the mirror current I3. For example, the register value 00011011 corresponds to 6.75 uA, 00011100 corresponds to 7 uA, and for each increase of 1 in the binary number, the corresponding internal reference current I4 increases by a step of 0.25 uA. This 0.25 uA step is equivalent to the minimum gear current Imin.

[0041] Since batch trimming does not support increasing the current at the output end, generally the maximum supported current is 1 A. The closer it is to 1 A, the shorter the life of the machine probe. Also, the target current at the output end is not fixed and there are various requirements, such as 2 A, 3 A, 3.5 A, etc. To unify the test conditions, trimming is performed with a small current, which improves the trimming efficiency; and for testers, the smaller the current, the lower the risk factor and the safer the test environment. Moreover, the number of chips for batch trimming is relatively large, so compared with a large current, a small current can reduce power consumption. Therefore, in step one, the input current I0 of the mirror circuit 10 needs to be reduced to 0.1 - 1 A for trimming.

[0042] Taking I0 = 700 mA and ratio P = 100000 as an example, for current I3 = I0 / P = 700 mA / 100000 = 7 uA. In the current - to - voltage module 20, V3 = I3 * R1 and V4 = I4 * R2. The judgment basis for just not having an over - current is: by changing the register value to traverse and decrease the digital register, just making the voltage V4 > V3, then the over - current comparison module 30 outputs a low level, and the charge pump will not be pulled down, indicating that no over - current occurs at this time. If V4 < V3, the over - current comparison module 30 outputs a high level and the charge pump is pulled down, indicating that an over - current occurs at this time.

[0043] That is, first reduce the input current I0 of the mirror circuit 10 to 0.1 - 1 A, adjust the internal reference current I4 until the voltage V4 is greater than the voltage V3. At this time, no over - current phenomenon occurs, and record the ratio P of the mirror circuit 10 at this time as P1; then first adjust the external input current I0 of the mirror circuit 10 to increase it by one gear P1 * Imin (0.25 uA * 100000 = 25 mA), then adjust the internal reference current I4 to increase it by a minimum gear current Imin (0.25 uA). Then, through the over - current comparison module 30, judge the magnitude relationship between the voltage V4 and the voltage V3 at this time. 1. If the voltage V4 < voltage V3 at this time, it means an over - current phenomenon occurs, and the ratio P of the mirror circuit 10 needs to be reduced. The ratio P can be reduced by reducing Figure 2 the magnitude of the ratio N of the second mirror circuit 10 in it to reduce the mirror ratio P (generally, Figure 2The ratio M of the first mirror circuit 10 in the circuit is not allowed to be adjusted. In this example, M=5000 is set, and the default register value 10000 corresponds to N=40, and 10001 corresponds to N=41) until overcurrent just does not occur. At this time, the ratio P is recorded as P2, and the value (binary number) corresponding to P2 is written into the chip. Then, the external input current I0 of the mirror circuit is adjusted to the actual current limit value I of the chip (generally 2 to 6A), and the internal reference current I4 is increased by the corresponding gear (I-I0) / P2, and the adjustment can be completed;

[0044] 2. If the voltage V4> the voltage V3 at this time, it means that there is no overcurrent phenomenon. It is necessary to increase the ratio P of the mirror circuit 10 until overcurrent occurs. At this time, the ratio P of the mirror circuit 10 is recorded as P3; because overcurrent just occurs at this time, it is only necessary to reduce the ratio P3 of the mirror circuit 10 by a minimum gear, so that the current I3 is reduced by a minimum gear current Imin, that is, the register value is reduced by 1 bit, and the corresponding N value is reduced by 1. At this time, the ratio P is recorded as P4, and the value (binary number) corresponding to P4 is written into the chip, and it can be adjusted from just overcurrent to just no overcurrent, and then the external input current I0 of the mirror circuit is adjusted to the actual current limit value I of the chip (generally 2 to 6A), and the internal reference current I4 is increased by the corresponding gear (I-I0) / P4, and the adjustment is completed. The deviation of the current limit value in batch testing does not exceed ±3%.

[0045] That is, the present invention adjusts the mirror ratio P on the basis of the two-point method adjustment, and significantly improves the accuracy of the actual chip working large current limit value through small current adjustment.

[0046] It is easy for those skilled in the art to understand that the above preferred embodiments can be freely combined and superimposed without conflict.

[0047] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or directly or indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A current limiting accuracy calibration method for a current limiting switch, applied to a current limiting accuracy calibration circuit, characterized in that: The current limiting precision calibration circuit comprises a mirror circuit (10), a current-to-voltage module (20) and an overcurrent comparison module (30); the mirror circuit (10) is electrically connected to a charge pump; the ratio between the current I0 at the input end of the mirror circuit (10) and the current I3 at its output end is P (I3=I0 / P); the current-to-voltage module (20) is used to convert an internal reference current I4 and a current I3 into corresponding voltages V4 and V3 respectively; the overcurrent comparison module (30) is used to compare the magnitudes of the voltages V4 and V3; the method comprises the following steps: Step 1, adjusting the internal reference current I4 until the voltage V4 is greater than the voltage V3, at which time no overcurrent occurs, and the ratio P of the mirror circuit is recorded as P1; Step 2, adjusting the current I0 of the mirror circuit to increase it by one gear P1*Imin, where Imin is the minimum gear current corresponding to the internal reference current I4; Step 3, adjust the internal reference current I4 to increase it by one level Imin; Step 4, determining whether voltage V4>voltage V3, or voltage V4<voltage V3; If voltage V4 < voltage V3, an overcurrent occurs, and step 5 is executed; If voltage V4>voltage V3, no overcurrent occurs, and step 6 is executed; Step 5, reducing the ratio P of the mirror circuit until no overcurrent occurs, at which time the ratio P is recorded as P2, and writing the value corresponding to P2 into the chip, and executing step 8; Step 6, increasing the ratio P of the mirror circuit until overcurrent occurs, at which time the ratio P is recorded as P3, and executing step 7; Step 7, reducing the ratio P3 of the mirror circuit by a minimum gear, at which time the ratio P is recorded as P4, and writing the value corresponding to P4 into the chip, and executing step 8; Step 8, adjusting the current I0 of the mirror circuit to the actual current limit value I of the chip, increasing the internal reference current I4 by the corresponding level, and completing the adjustment.

2. The current limiting accuracy calibration method of a current limiting switch according to claim 1, characterized in that: In step 1, the input current I0 of the mirror circuit (10) has a value range of 0.1 to 1A.

3. The current limiting accuracy calibration method of a current limiting switch according to claim 1, characterized in that: The overcurrent comparison module (30) comprises a comparator CMP, a MOS transistor Q9 and a MOS transistor Q10, a positive input terminal of the comparator CMP inputs a voltage V4, a negative input terminal of the comparator CMP inputs a voltage V3, an output terminal of the comparator CMP is respectively electrically connected to the drain and gate of the MOS transistor Q9 and the gate of the MOS transistor Q10, and is electrically connected to a charge pump, a source of the MOS transistor Q9 and a source of the MOS transistor Q10 are respectively grounded, and a drain of the MOS transistor Q10 is electrically connected to the charge pump, when the voltage V4> the voltage V3, the comparator CMP outputs a low level, so that the charge pump is not pulled down, indicating that no overcurrent occurs at this time; when the voltage V4< the voltage V3, the comparator CMP outputs a high level, so that the charge pump is pulled down, indicating that an overcurrent occurs at this time.

4. The current limiting accuracy calibration method of a current limiting switch according to claim 1, characterized in that: The mirror circuit (10) comprises a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a MOS transistor Q5, a MOS transistor Q6, a MOS transistor Q7, a MOS transistor Q8 and a comparator OP1, wherein the MOS transistor Q1 and the MOS transistor Q2 form a first mirror circuit (11), and the MOS transistor Q4 and the MOS transistor Q5 form a second mirror circuit (12), the ratio of the first mirror circuit (11) is M, the ratio of the second mirror circuit (12) is N, and the ratio of the mirror circuit (10) is P=M*N; The gate of the MOS transistor Q1 and the gate of the MOS transistor Q2 are electrically connected to the charge pump respectively, the drain of the MOS transistor Q1 and the drain of the MOS transistor Q2 are connected to the input voltage VIN respectively, the source of the MOS transistor Q1 is electrically connected to the inverting input terminal of the comparator OP1 and the source of the MOS transistor Q3 respectively, the output terminal of the comparator OP1 is electrically connected to the gate of the MOS transistor Q3, the drain of the MOS transistor Q3 is electrically connected to the gate and drain of the MOS transistor Q4 and the gate of the MOS transistor Q5 respectively, the source of the MOS transistor Q4 and the source of the MOS transistor Q5 are grounded respectively, the drain of the MOS transistor Q5 is electrically connected to the source of the MOS transistor Q8, the drain of the MOS transistor Q8 is electrically connected to the gate and drain of the MOS transistor Q6 and the gate of the MOS transistor Q7 respectively, the source of the MOS transistor Q6 and the source of the MOS transistor Q7 are connected to the operating voltage VCC respectively, the current of the drain of the MOS transistor Q7 is the output current I3, and the current of the source of the MOS transistor Q2 is the input current I0.

5. The current limiting accuracy calibration method of a current limiting switch according to claim 1, characterized in that: The current-to-voltage module (20) comprises a resistor R1 and a resistor R2, one end of the resistor R1 is electrically connected to the output end of the mirror circuit to input the output current I3, one end of the resistor R2 inputs the internal reference current I4, the other end of the resistor R1 and the other end of the resistor R2 are grounded respectively, the voltage V3 = I3*R1, and the voltage V4 = I4*R2.

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