Low dropout regulator, ferroelectric memory, and electronic device

Abstract

The invention discloses a low dropout linear regulator, a ferroelectric memory and electronic equipment, which can be applied to the technical field of electronic circuits. According to the low dropout linear regulator, the current environment module, the first error amplifier module, the buffer module, the feedback module, the second error amplifier module and the discharge module are arranged in the low dropout linear regulator; after error amplification processing is carried out through a first error amplifier module according to input reference voltage and feedback voltage, first amplified voltage is cached through a cache module, working voltage is provided for a ferroelectric chip through a feedback module according to the first amplified voltage, and feedback voltage is generated. Then the second error amplifier module performs voltage amplification processing according to the input reference voltage and the feedback voltage to obtain a second amplified voltage, and the discharge module adjusts the output voltage of the feedback module according to the second amplified voltage, so that the working frequency of the ferroelectric memory chip is improved, and the size of the whole circuit is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a low voltage drop linear regulator, a ferroelectric memory and an electronic device. Background Art

[0002] In the related art, Low Dropout Regulator (LDO) is a common basic circuit module in analog circuits, which is used to realize level conversion and provide stable, low-interference power supply for other circuits. Due to the particularity of the storage array of large-capacity ferroelectric memory chips, the output load of LDO is required to be above 100mA. However, current ferroelectric chips usually use two LDOs to be responsible for high and low load conditions respectively. When switching between high and low loads, this method often has serious voltage fluctuations and slow recovery time, thereby limiting the operating frequency of the ferroelectric chip. At the same time, the use of two LDOs also increases the size of the overall circuit.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a low voltage difference linear regulator, a ferroelectric memory and an electronic device, which can increase the operating frequency of the ferroelectric memory chip and reduce the size of the overall circuit.

[0005] To achieve the above object, one aspect of an embodiment of the present application provides a low voltage dropout linear regulator, the regulator comprising:

[0006] A current environment module, wherein the current environment module is used to provide a bias voltage;

[0007] A first error amplifier module, which is connected to the current amplifier module and obtains a first amplified voltage after performing error amplification processing according to an input reference voltage and a feedback voltage;

[0008] a buffer module, the buffer module being connected to the current control module and the first error amplifier module respectively, and being used for buffering the first amplified voltage;

[0009] A feedback module, the feedback module is connected to the current environment and the buffer module respectively, and is used to provide a working voltage to the ferroelectric chip according to the first amplified voltage, and generate the feedback voltage;

[0010] a second error amplifier module, the second error amplifier module is connected to the feedback module and is used to obtain a second amplified voltage after performing voltage amplification processing according to an input reference voltage and the feedback voltage;

[0011] A leakage module, the leakage module is respectively connected to the feedback module and the second error amplifier module, and is used to adjust the output voltage of the feedback module according to the second amplified voltage.

[0012] In some embodiments, the current environment module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and a first resistor;

[0013] The source stage of the first MOS tube, the source stage of the second MOS tube, and the source stage of the fifth MOS tube are all connected to an input power supply;

[0014] The drain of the first MOS tube, the gate of the first MOS tube and the drain of the third MOS tube are all connected to the gate of the second MOS tube;

[0015] The drain of the second MOS tube is connected to the drain of the fourth MOS tube;

[0016] The gate of the third MOS tube is connected to the gate of the fourth MOS tube;

[0017] The source of the fourth MOS tube is connected to the first end of the first resistor;

[0018] The drain of the sixth MOS tube and the gate of the sixth MOS tube are both connected to the drain of the fifth MOS tube;

[0019] The drain of the seventh MOS tube and the gate of the seventh MOS tube are both connected to the source of the sixth MOS tube;

[0020] The gate of the sixth MOS tube is externally connected to an input bias current;

[0021] The source of the third MOS tube, the second end of the first resistor and the source of the seventh MOS tube are all grounded.

[0022] In some embodiments, the first error amplifier module includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube;

[0023] The gate of the eighth MOS tube is connected to the feedback module;

[0024] The source stage of the eighth MOS tube, the source stage of the fifteenth MOS tube and the source stage of the sixteenth MOS tube are all connected to an input power supply;

[0025] The drain of the eighth MOS tube is connected to the source of the ninth MOS tube and the source of the tenth MOS tube respectively;

[0026] The drain of the ninth MOS tube is connected to the drain of the eleventh MOS tube and the source of the thirteenth MOS tube respectively;

[0027] The drain of the tenth MOS tube is connected to the drain of the twelfth MOS tube and the source of the fourteenth MOS tube respectively;

[0028] The gate of the thirteenth MOS tube is connected to the gate of the fourteenth MOS tube;

[0029] The drain of the thirteenth MOS tube is respectively connected to the drain of the fifteenth MOS tube, the gate of the fifteenth MOS tube and the gate of the sixteenth MOS tube;

[0030] The drain of the sixteenth MOS tube and the drain of the fourteenth MOS tube are both connected to the buffer module;

[0031] The gate of the eleventh MOS tube is connected to the gate of the twelfth MOS tube;

[0032] The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are both grounded.

[0033] In some embodiments, the buffer module includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0034] The first end of the second resistor, the source of the eighteenth MOS tube and the source of the nineteenth MOS tube are all connected to an input power supply;

[0035] The second end of the second resistor is connected to the first end of the first capacitor;

[0036] The second end of the first capacitor and the gate of the seventeenth MOS tube are connected to the drain of the sixteenth MOS tube;

[0037] The drain of the eighteenth MOS tube, the drain of the nineteenth MOS tube, and the gate of the nineteenth MOS tube are all connected to the source of the seventeenth MOS tube;

[0038] The drain of the seventeenth MOS tube is grounded;

[0039] The first end of the second capacitor is connected to the source of the fourteenth MOS tube;

[0040] The second end of the second capacitor is connected to the first end of the second resistor;

[0041] The second end of the second resistor is connected to the feedback module.

[0042] In some embodiments, the feedback module includes a twentieth MOS transistor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0043] The source of the 20th MOS tube is connected to the input power supply;

[0044] The gate of the 20th MOS tube is connected to the gate of the 19th MOS tube;

[0045] The drain of the 20th MOS tube is respectively connected to the second end of the third resistor and the first end of the fourth resistor;

[0046] The second end of the fourth resistor and the first end of the fifth resistor are both connected to the gate of the ninth MOS tube;

[0047] The second end of the fifth resistor and the first end of the sixth resistor are both connected to the second error amplifier module;

[0048] A second end of the sixth resistor is grounded.

[0049] In some embodiments, the second error amplifier module includes a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube and a twenty-fifth MOS tube;

[0050] The source stage of the twenty-first MOS tube and the source stage of the twenty-second MOS tube are both connected to an input power supply;

[0051] The gate of the twenty-first MOS tube is connected to the gate of the twenty-second MOS tube;

[0052] The drain of the twenty-first MOS tube is connected to the drain of the twenty-third MOS tube;

[0053] The gate of the twenty-third MOS tube is connected to the first end of the sixth resistor;

[0054] The source of the twenty-third MOS tube is connected to the source of the twenty-fourth MOS tube and the drain of the twenty-fifth MOS tube respectively;

[0055] The source of the twenty-fifth MOS tube is grounded;

[0056] The drain of the twenty-second MOS tube and the drain of the twenty-fourth MOS tube are both connected to the power leakage module;

[0057] The gate of the twenty-fourth MOS tube is connected to a bias current.

[0058] In some embodiments, the power dissipation module includes a twenty-sixth MOS tube and a twenty-seventh MOS tube;

[0059] The drain of the twenty-sixth MOS tube is connected to the output end of the feedback module;

[0060] The gate of the twenty-sixth MOS tube is connected to the drain of the twenty-fourth MOS tube;

[0061] The gate electrode of the twenty-seventh MOS tube and the drain electrode of the twenty-seventh MOS tube are both connected to the source electrode of the twenty-sixth MOS tube;

[0062] The source of the twenty-seventh MOS tube is grounded.

[0063] In some embodiments, the voltage regulator further includes a third capacitor;

[0064] The first end of the third capacitor is connected to the input power supply;

[0065] The second end of the third capacitor is connected to the gate of the fifteenth MOS tube.

[0066] To achieve the above objective, another aspect of an embodiment of the present application provides a ferroelectric memory, comprising the above low voltage dropout linear regulator.

[0067] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, comprising the above ferroelectric memory.

[0068] The embodiments of the present application include at least the following beneficial effects: The present application provides a low-voltage difference linear regulator, a ferroelectric memory and an electronic device. The scheme is to set a current environment module, a first error amplifier module, a buffer module, a feedback module, a second error amplifier module and a leakage module in the low-voltage difference linear regulator, so that after the bias voltage is provided by the current environment module, the first error amplifier module performs error amplification processing according to the input reference voltage and feedback voltage, and then caches the first amplified voltage through the cache module, and provides the ferroelectric chip with the working voltage and generates the feedback voltage through the feedback module according to the first amplified voltage, and then the second error amplifier module performs voltage amplification processing according to the input reference voltage and feedback voltage to obtain the second amplified voltage, and then the leakage module adjusts the output voltage of the feedback module according to the second amplified voltage, so that the ferroelectric memory chip can maintain stability even when the output load of the regulator fluctuates rapidly under high-frequency working conditions, thereby improving the working frequency of the ferroelectric memory chip and reducing the size of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 is a module block diagram of a low voltage dropout linear regulator provided in an embodiment of the present application;

[0070] Figure 2 1 is a circuit diagram of a low voltage dropout linear regulator provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application, they are only examples of devices and methods consistent with some aspects of the embodiments of the present application.

[0072] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0073] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0075] Reference Figure 1The present application provides a low voltage difference linear regulator, which includes a current environment module, a first error amplifier module, a buffer module, a feedback module, a second error amplifier module and a leakage module. Among them, the current environment module is used to provide a bias voltage; the first error amplifier module is connected to the current environment module, and obtains a first amplified voltage after error amplification according to the input reference voltage and feedback voltage; the buffer module is respectively connected to the current environment module and the first error amplifier module, and is used to cache the first amplified voltage; the feedback module is respectively connected to the current environment and the buffer module, and is used to provide a working voltage to the ferroelectric chip according to the first amplified voltage and generate a feedback voltage; the second error amplifier module is connected to the feedback module, and is used to obtain a second amplified voltage after voltage amplification according to the input reference voltage and feedback voltage; the leakage module is respectively connected to the feedback module and the second error amplifier module, and is used to adjust the output voltage of the feedback module according to the second amplified voltage. Specifically, the regulator provided by this embodiment can effectively increase the operating frequency of the ferroelectric memory chip and reduce the size of the overall circuit.

[0076] In the embodiments of the present application, Figure 2 As shown, the current environment module includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and a first resistor R1; the source of the first MOS tube M1, the source of the second MOS tube M2 and the source of the fifth MOS tube M5 are all connected to the input power supply; the drain of the first MOS tube M1, the gate of the first MOS tube M1 and the drain of the third MOS tube M3 are all connected to the gate of the second MOS tube M2; the drain of the second MOS tube M2 is connected to the gate of the fourth MOS tube M4. The drain of the third MOS tube M4 is connected; the gate of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4; the source of the fourth MOS tube M4 is connected to the first end of the first resistor; the drain of the sixth MOS tube M6 and the gate of the sixth MOS tube M6 are both connected to the drain of the fifth MOS tube M5; the drain of the seventh MOS tube M7 and the gate of the seventh MOS tube M7 are both connected to the source of the sixth MOS tube M6; the gate of the sixth MOS tube M6 is externally connected to the input bias current; the source of the third MOS tube M3, the second end of the first resistor R1 and the source of the seventh MOS tube M7 are all grounded. Specifically, the first MOS tube, the second MOS tube and the fifth MOS tube of this embodiment can adopt PMOS tubes, and the third MOS tube, the fourth MOS tube, the sixth MOS tube and the seventh MOS tube adopt NMOS tubes. This embodiment obtains a stable mirror current by mirroring the input current to provide tail current to the first error amplifier module and the cache module, and provides bias current to the first error amplifier, the cache module and the feedback module.

[0077] In the embodiments of the present application, Figure 2As shown, the first error amplifier module includes an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15 and a sixteenth MOS tube M16; the gate of the eighth MOS tube M8 is connected to the feedback module; the source level of the eighth MOS tube M8, the source level of the fifteenth MOS tube M15 and the source level of the sixteenth MOS tube M16 are all connected to the input power supply; the drain of the eighth MOS tube M8 is respectively connected to the source level of the ninth MOS tube M9 and the source level of the tenth MOS tube M10; the drain of the ninth MOS tube M9 is respectively connected to the drain of the eleventh MOS tube M11 and the drain of the thirteenth MOS tube M16 The source of the MOS tube M13 is connected; the drain of the tenth MOS tube M10 is respectively connected to the drain of the twelfth MOS tube M12 and the source of the fourteenth MOS tube M14; the gate of the thirteenth MOS tube M13 is connected to the gate of the fourteenth MOS tube M14; the drain of the thirteenth MOS tube M13 is respectively connected to the drain of the fifteenth MOS tube M15, the gate of the fifteenth MOS tube M15 and the gate of the sixteenth MOS tube M16; the drain of the sixteenth MOS tube M16 and the drain of the fourteenth MOS tube M14 are both connected to the buffer module; the gate of the eleventh MOS tube M11 is connected to the gate of the twelfth MOS tube M12; the source of the eleventh MOS tube M11 and the source of the twelfth MOS tube M12 are both grounded. Specifically, the eighth MOS tube is a tail current tube, the ninth MOS tube and the tenth MOS tube are input pair tubes, and the fourteenth MOS tube and the sixteenth MOS tube constitute an output end. This embodiment performs error amplification processing according to the feedback module return voltage FB_U and the input reference voltage VREF, thereby realizing the voltage regulation process.

[0078] In the embodiments of the present application, Figure 2As shown, the buffer module includes a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a second resistor R2, a third resistor R2, a first capacitor C1 and a second capacitor C2; the first end of the second resistor R2, the source of the eighteenth MOS tube M18 and the source of the nineteenth MOS tube M19 are all connected to the input power supply; the second end of the second resistor R2 is connected to the first end of the first capacitor; the second end of the first capacitor and the gate of the seventeenth MOS tube M17 are connected to the drain of the sixteenth MOS tube M16; the drain of the eighteenth MOS tube M18, the drain of the nineteenth MOS tube M19 and the gate of the nineteenth MOS tube M19 are all connected to the source of the seventeenth MOS tube M17; the drain of the seventeenth MOS tube M17 is grounded; the first end of the second capacitor C2 is connected to the source of the fourteenth MOS tube M14; the second end of the second capacitor C2 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the feedback module. In this embodiment, by providing a buffer module between the first error amplifier module and the feedback module, a buffer operation can be performed on the output voltage of the first error amplifier module, thereby improving circuit stability.

[0079] In the embodiment of the present application, the feedback module includes a twentieth MOS tube M20, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the source of the twentieth MOS tube M20 is connected to the input power supply; the gate of the twentieth MOS tube M20 is connected to the gate of the nineteenth MOS tube M19; the drain of the twentieth MOS tube M20 is respectively connected to the second end of the third resistor R3 and the first end of the fourth resistor R4; the second end of the fourth resistor R4 and the first end of the fifth resistor R5 are both connected to the gate of the ninth MOS tube M9; the second end of the fifth resistor R5 and the first end of the sixth resistor R6 are both connected to the second error amplifier module; the second end of the sixth resistor R6 is grounded. Specifically, the twentieth MOS tube of the present embodiment can be a PMOS tube. The present embodiment can effectively adjust the stability of the output voltage by feeding back the output voltage.

[0080] In the embodiment of the present application, the second error amplifier module includes a twenty-first MOS tube M21, a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, and a twenty-fifth MOS tube M25; the source of the twenty-first MOS tube M21 and the source of the twenty-second MOS tube M22 are both connected to the input power supply; the gate of the twenty-first MOS tube M21 is connected to the gate of the twenty-second MOS tube M22; the drain of the twenty-first MOS tube M21 is connected to the drain of the twenty-third MOS tube M23; the gate of the twenty-third MOS tube M23 is connected to the first end of the sixth resistor; the source of the twenty-third MOS tube M23 is respectively connected to the source of the twenty-fourth MOS tube M24 and the drain of the twenty-fifth MOS tube M25; the source of the twenty-fifth MOS tube M25 is grounded; the drain of the twenty-second MOS tube M22 and the drain of the twenty-fourth MOS tube M24 are both connected to the discharge module; the gate of the twenty-fourth MOS tube M24 is connected to the bias current. Specifically, the twenty-fifth MOS tube of the present embodiment is a tail current tube, and the twenty-third MOS tube and the twenty-fourth MOS tube are input pair tubes. In this embodiment, the output voltage can be error-amplified so that the leakage module can adjust the output voltage of the voltage regulator.

[0081] In the embodiments of the present application, Figure 2 As shown, the leakage module includes a twenty-sixth MOS tube 26 and a twenty-seventh MOS tube M27; the drain of the twenty-sixth MOS tube M26 is connected to the output end of the feedback module; the gate of the twenty-sixth MOS tube M26 is connected to the drain of the twenty-fourth MOS tube M24; the gate of the twenty-seventh MOS tube M27 and the drain of the twenty-seventh MOS tube M27 are both connected to the source of the twenty-sixth MOS tube M26; the source of the twenty-seventh MOS tube M27 is grounded. In this embodiment, the leakage module is used to discharge electricity to the ground, so that the output voltage of the voltage regulator can be adjusted.

[0082] In the embodiments of the present application, Figure 2 As shown, the voltage regulator further includes a third capacitor C3; a first end of the third capacitor C3 is connected to the input power supply; a second end of the third capacitor C3 is connected to the gate of the fifteenth MOS tube M25. This embodiment performs isolation operation through the third capacitor, thereby improving the circuit working stability.

[0083] It can be understood that this embodiment uses the principle of virtual short of the first error amplifier module to force the resistor string feedback point FB_U to be equal to the reference voltage, and then generates the output voltage VOUT through the resistor string voltage division. The seventeenth MOS tube in the buffer module is a source follower structure, and the output of the first error amplifier module controls the conduction degree of the seventeenth MOS tube. The nineteenth MOS tube in the buffer module and the twentieth MOS tube of the feedback module form a current mirror, and the load current can be tolerated within the current mirror ratio range, and the feedback resistor string voltage division point FB_L is always lower than FB_; when the output jitters upward FB_L higher than the reference voltage, the leakage path punches VOUT and discharges directly to the ground through the twenty-sixth MOS tube and the twenty-seventh MOS tube.

[0084] Comparing the present application with the existing voltage regulator tube, the results shown in Table 1 are obtained:

[0085] Table 1

[0086] Existing Ferroelectric Internal LDO This application Load Capacity 20mA 100mA Build Time >10us <5us

[0087] It can be seen that the voltage regulator tube provided by this application has the following effects:

[0088] First, it can adapt to load current changes with a span of more than 100mA, and is used to adapt to the specific layout and current requirements of the ferroelectric memory chip storage array.

[0089] Second, when the chip state changes and the load switches, the LDO output can quickly follow the load to adjust the output, solving the problem of slow switching of existing ferroelectric chips.

[0090] Thirdly, the output establishment problem when the existing ferroelectric memory chip uses two LDOs with large and small loads to switch can be solved, and it can adapt to the faster operating frequency of the chip.

[0091] In addition, the embodiment of the present application further provides a ferroelectric memory and an electronic device, wherein the ferroelectric memory includes the above-mentioned low voltage difference linear regulator, and the electronic device includes the ferroelectric memory.

[0092] It can be understood that the contents of the above-mentioned low voltage difference linear regulator embodiment are applicable to the present ferroelectric memory and electronic device embodiment, and the beneficial effects achieved by the present ferroelectric memory and electronic device embodiment are the same as the beneficial effects achieved by the above-mentioned bandgap reference circuit embodiment.

[0093] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0094] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0095] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0097] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0098] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0099] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0100] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0103] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A low voltage dropout linear regulator, characterized in that: The voltage regulator comprises: A current environment module, wherein the current environment module is used to provide a bias voltage; A first error amplifier module, which is connected to the current amplifier module and obtains a first amplified voltage after performing error amplification processing according to an input reference voltage and a feedback voltage; a buffer module, the buffer module being connected to the current control module and the first error amplifier module respectively, and being used for buffering the first amplified voltage; A feedback module, the feedback module is connected to the current environment and the buffer module respectively, and is used to provide a working voltage to the ferroelectric chip according to the first amplified voltage, and generate the feedback voltage; a second error amplifier module, the second error amplifier module is connected to the feedback module and is used to obtain a second amplified voltage after performing voltage amplification processing according to an input reference voltage and the feedback voltage; A leakage module, the leakage module is respectively connected to the feedback module and the second error amplifier module, and is used to adjust the output voltage of the feedback module according to the second amplified voltage.

2. The voltage stabilizer according to claim 1, characterized in that: The current environment module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and a first resistor; The source stage of the first MOS tube, the source stage of the second MOS tube, and the source stage of the fifth MOS tube are all connected to an input power supply; The drain of the first MOS tube, the gate of the first MOS tube and the drain of the third MOS tube are all connected to the gate of the second MOS tube; The drain of the second MOS tube is connected to the drain of the fourth MOS tube; The gate of the third MOS tube is connected to the gate of the fourth MOS tube; The source of the fourth MOS tube is connected to the first end of the first resistor; The drain of the sixth MOS tube and the gate of the sixth MOS tube are both connected to the drain of the fifth MOS tube; The drain of the seventh MOS tube and the gate of the seventh MOS tube are both connected to the source of the sixth MOS tube; The gate of the sixth MOS tube is externally connected to an input bias current; The source of the third MOS tube, the second end of the first resistor and the source of the seventh MOS tube are all grounded.

3. The voltage stabilizer according to claim 2, characterized in that: The first error amplifier module includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube; The gate of the eighth MOS tube is connected to the feedback module; The source stage of the eighth MOS tube, the source stage of the fifteenth MOS tube and the source stage of the sixteenth MOS tube are all connected to an input power supply; The drain of the eighth MOS tube is connected to the source of the ninth MOS tube and the source of the tenth MOS tube respectively; The drain of the ninth MOS tube is connected to the drain of the eleventh MOS tube and the source of the thirteenth MOS tube respectively; The drain of the tenth MOS tube is connected to the drain of the twelfth MOS tube and the source of the fourteenth MOS tube respectively; The gate of the thirteenth MOS tube is connected to the gate of the fourteenth MOS tube; The drain of the thirteenth MOS tube is respectively connected to the drain of the fifteenth MOS tube, the gate of the fifteenth MOS tube and the gate of the sixteenth MOS tube; The drain of the sixteenth MOS tube and the drain of the fourteenth MOS tube are both connected to the buffer module; The gate of the eleventh MOS tube is connected to the gate of the twelfth MOS tube; The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are both grounded.

4. The voltage stabilizer according to claim 3, characterized in that: The buffer module includes a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a second resistor, a third resistor, a first capacitor and a second capacitor; The first end of the second resistor, the source of the eighteenth MOS tube and the source of the nineteenth MOS tube are all connected to an input power supply; The second end of the second resistor is connected to the first end of the first capacitor; The second end of the first capacitor and the gate of the seventeenth MOS tube are connected to the drain of the sixteenth MOS tube; The drain of the eighteenth MOS tube, the drain of the nineteenth MOS tube, and the gate of the nineteenth MOS tube are all connected to the source of the seventeenth MOS tube; The drain of the seventeenth MOS tube is grounded; The first end of the second capacitor is connected to the source of the fourteenth MOS tube; The second end of the second capacitor is connected to the first end of the second resistor; The second end of the second resistor is connected to the feedback module.

5. The voltage stabilizer according to claim 4, characterized in that: The feedback module includes a twentieth MOS tube, a fourth resistor, a fifth resistor and a sixth resistor; The source of the 20th MOS tube is connected to the input power supply; The gate of the 20th MOS tube is connected to the gate of the 19th MOS tube; The drain of the 20th MOS tube is respectively connected to the second end of the third resistor and the first end of the fourth resistor; The second end of the fourth resistor and the first end of the fifth resistor are both connected to the gate of the ninth MOS tube; The second end of the fifth resistor and the first end of the sixth resistor are both connected to the second error amplifier module; A second end of the sixth resistor is grounded.

6. The voltage stabilizer according to claim 5, characterized in that: The second error amplifier module includes a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube and a twenty-fifth MOS tube; The source stage of the twenty-first MOS tube and the source stage of the twenty-second MOS tube are both connected to an input power supply; The gate of the twenty-first MOS tube is connected to the gate of the twenty-second MOS tube; The drain of the twenty-first MOS tube is connected to the drain of the twenty-third MOS tube; The gate of the twenty-third MOS tube is connected to the first end of the sixth resistor; The source of the twenty-third MOS tube is connected to the source of the twenty-fourth MOS tube and the drain of the twenty-fifth MOS tube respectively; The source of the twenty-fifth MOS tube is grounded; The drain of the twenty-second MOS tube and the drain of the twenty-fourth MOS tube are both connected to the power leakage module; The gate of the twenty-fourth MOS tube is connected to a bias current.

7. The voltage stabilizer according to claim 6, characterized in that: The power leakage module includes a twenty-sixth MOS tube and a twenty-seventh MOS tube; The drain of the twenty-sixth MOS tube is connected to the output end of the feedback module; The gate of the twenty-sixth MOS tube is connected to the drain of the twenty-fourth MOS tube; The gate electrode of the twenty-seventh MOS tube and the drain electrode of the twenty-seventh MOS tube are both connected to the source electrode of the twenty-sixth MOS tube; The source of the twenty-seventh MOS tube is grounded.

8. The voltage stabilizer according to any one of claims 1 to 7, characterized in that: The voltage stabilizer further includes a third capacitor; The first end of the third capacitor is connected to the input power supply; The second end of the third capacitor is connected to the gate of the fifteenth MOS tube.

9. A ferroelectric memory, characterized in that: A low voltage drop linear regulator comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: Includes the ferroelectric memory as claimed in claim 9.

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