1553B bus protocol device communication device based on FPGA (Field Programmable Gate Array) and control method of 1553B bus protocol device communication device

Abstract

The invention provides an FPGA-based 1553B bus protocol device communication device and a control method thereof, the device comprises a processor, an FPGA chip and an interface circuit, the FPGA chip comprises a CPU control interface module and an FPGA core module, and the FPGA chip communicates with the processor through the CPU control interface module; the FPGA core module is used for realizing core logic of a 1553B bus protocol and realizing bus control through the CPU control interface module according to the 1553B bus protocol; the processor controls the interface module to configure the register through the CPU, and the working mode of the 1553B bus is set to be one of a bus controller, a remote terminal or a bus monitor. The 1553B bus protocol is realized through one FPGA chip, the interoperability among different components is reduced by integrating the CPU control interface module, the adaptability and the flexibility of the device are improved, and the overall development cost is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of aviation 1553B bus protocol devices, and in particular, relates to a 1553B bus protocol device communication device based on FPGA and a control method thereof. Background Art

[0002] As an avionics bus standard, the MIL-STD-1553B (hereinafter referred to as 1553B) bus standard has been widely recognized once it was used. Although the 1553B bus has been developed and applied for many years, it still occupies an important position in high-reliability communication fields such as aviation, aerospace, and ships due to its advantages such as simple centralized control, real-time response, and fault tolerance and reliability. Since the core technology of the 1553B bus has long been monopolized by European and American companies, the independent research and development of protocol chips and products for the 1553B bus is of great strategic significance. With the continuous advancement of technology and the expansion of application scenarios, more and more users are beginning to consider using domestically produced 1553B chips to replace DDC's products, such as BU61580, BU65170, etc.

[0003] Therefore, it is extremely important to reduce the cost of domestic equipment, reduce dependence on the supply chain, enhance independent research and development capabilities, and improve the adaptability and flexibility of domestic equipment, so as to enhance the overall industry's independent controllability and market competitiveness. Summary of the invention

[0004] The present application discloses a 1553B bus protocol communication device based on FPGA and a control method thereof, which can realize the 1553B bus protocol stack through an FPGA chip, and integrate a CPU control interface module to reduce the interoperability problems between different components, reduce the complexity of development and testing, improve the adaptability and flexibility of the device, and reduce the overall development cost and dependence on imported equipment.

[0005] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0006] To achieve one or part or all of the above purposes or other purposes, the present application provides a 1553B bus protocol communication device based on FPGA, the device comprising: a processor, an FPGA chip and an interface circuit, the FPGA chip comprising a CPU control interface module and an FPGA core module, the FPGA chip communicates with the processor through the CPU control interface module, and the FPGA chip is physically connected to the 1553B bus through the interface circuit; the FPGA core module is used to implement the core logic of the 1553B bus protocol, and implement bus control through the CPU control interface module according to the 1553B bus protocol, the bus control includes timing control, maintaining command block space, and indicating command block operations through register mapping; the processor configures the registers inside the FPGA chip through the CPU control interface module, and sets the working mode of the 1553B bus to one of the bus controller, remote terminal or bus monitor.

[0007] In one implementation, the control logic of the CPU control interface module adopts register mapping. In the initialization phase, the CPU control interface module is used to reset the registers and state machine to the initial state, and map the internal register address to the address space of the processor through register mapping, and determine the working mode of the 1553B bus by configuring the register information.

[0008] In one implementation, the CPU control interface module is used to control the input and output of the FPGA core module. The CPU control interface module is used to clear the status register and the error register, and determine whether the local bus status is idle. If so, send a data request, if not, retry; the CPU control interface module is also used to automatically trigger the sending of an arbitration request signal when entering the local bus arbitration logic, and wait for the local bus control right. If the local bus control right is obtained, data transmission is performed; the CPU control interface module is also used to send write operation data, receive read operation data, and determine the response status of the local bus. If a response is received, data transmission continues, if no response is received, an error is recorded; the CPU control interface module is also used to send a transmission completion signal and update the status register when the data transmission is completed.

[0009] In one implementation, the CPU control interface module is also used for error identification and processing; the CPU control interface module is used to determine the error type and enter the corresponding error handling process according to the error type; the CPU control interface module is also used to record error information, perform retries or corresponding error handling notifications.

[0010] In one implementation, the FPGA core module accesses internal registers through the CPU control interface module, and performs read and write operations on command data and command block memory space to maintain the command block space.

[0011] In one implementation, the command block space includes 8 words of consecutive memory locations, and the 8 words of consecutive memory locations include a control word, two command words, a data pointer, two status words, a branch address, and a timer.

[0012] In one implementation, the FPGA core module operates the designated register through the CPU control interface module to achieve mutual communication between the bus controller and the remote terminal; if the bus controller sends a message to a remote terminal, the remote terminal will send back a status word within a set response time; if the message transmission is erroneous, the remote terminal will refuse to send back the status word.

[0013] In one implementation, the CPU control interface module has an interrupt processing capability. If the 1553B bus core sends an interrupt signal to the CPU control interface module, the CPU control interface module manages the enabling, clearing and priority of the interrupt through an interrupt control register.

[0014] In one implementation, the FPGA core module includes a timing control module and a protocol implementation module. The timing control module is used to control the signal timing to comply with the 1553B bus protocol. The timing control module uses the FPGA clock management and synchronization module to test and verify the 1553B bus protocol so that the data transmission on the 1553B bus complies with the specifications of the 1553B bus protocol; the protocol implementation module generates command words according to the command format of the 1553B standard and parses the received command words to process the commands and responses of the 1553B bus.

[0015] In one implementation, the FPGA core module also includes a data processing module and an error detection module; the data processing module performs data transmission and data forwarding through the CPU control interface module, the data processing module is used to store and parse data, and uses a FIFO buffer to process data streams; the error detection module is used to detect data integrity, parity checks of command words, data words and status words, and uses a cyclic redundancy check algorithm to perform error correction and detect whether the remote terminal address configuration is incorrect.

[0016] Another technical solution of the present application provides a control method for a 1553B bus protocol device communication device based on FPGA, and the control method is applicable to any of the above-mentioned 1553B bus protocol device communication devices based on FPGA, and the control method includes: in the initialization stage, timing start-up of the CPU control interface module, reading the register information inside the FPGA chip, and setting the working mode of the 1553B bus to one of the bus controller, remote terminal or bus monitor according to the register information; after the initialization is completed, accessing the register through the CPU control interface module to perform read and write operations to realize bus control, and the bus control includes timing control, maintaining command block space, and indicating command block operations through register mapping.

[0017] In one implementation, the control method also includes: in the initialization phase, resetting the register and the state machine to the initial state, configuring the register mapping information, setting the working mode of the 1553B bus, and clearing the status register and the error register; determining whether the local bus is idle, if so, sending a data request, and converting the request into a 1553B standard command format; determining whether the bus enters the local bus arbitration logic, if so, automatically triggering the sending of an arbitration request signal, and waiting for the local bus control right, and performing data transmission when the local bus control right is obtained; starting data transmission, sending a command and waiting for a response, determining the response status of the local bus, if a response is received, continuing the data transmission and performing data verification, if no response is received, recording the error; if the data transmission is completed, sending a transmission completion signal and updating the status register.

[0018] The above-mentioned FPGA-based 1553B bus protocol communication device and control method thereof implement the 1553B bus protocol stack through an FPGA chip, and integrate the CPU control interface module to reduce the interoperability problems between different components, reduce the complexity of development and testing, improve the adaptability and flexibility of the device, and reduce the overall development cost and dependence on imported equipment.

[0019] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1This is a structural block diagram of the 1553B bus protocol communication device based on FPGA in this application.

[0022] Figure 2 This is a structural block diagram of the communication connection between the CPU control interface module and the processor of this application.

[0023] Figure 3 This is a judgment flow chart of the CPU control interface module control method of this application.

[0024] Figure 4 This is a judgment flow chart of the overall control method of the communication device of this application.

[0025] Figure 5 This is a flow chart of the control logic in the BC mode of this application.

[0026] Figure 6 This is a schematic diagram of the structure of the device of the present application applied to a bus communication network topology system. DETAILED DESCRIPTION

[0027] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0028] During the research process, the inventor of the present application found that in the existing technical solutions of aviation 1553B bus protocol devices, imported integrated circuits and modules are usually used, which leads to high costs, insufficient independent innovation, poor adaptability and difficult maintenance. At the same time, in the existing solutions for implementing 1553B bus protocol devices, read and write operations are usually implemented by the system external PCI interface or built-in ACE read and write interface, which leads to the problems of limited data transmission rate, high cost and difficult development and maintenance.

[0029] Therefore, providing a domestically produced integrated device that implements the 1553B bus protocol with better effects and lower costs can bring new opportunities and impetus to the development of the industry, help promote the localization process, and enhance the country's independent innovation capabilities in the field of avionics.

[0030] The present embodiment provides a 1553B bus protocol communication device based on FPGA, which uses domestic FPGA to replace the imported 1553B dedicated protocol conversion chip. The 1553B protocol conversion uses the digital FPGA built-in 1553B IP core to replace the BU61580, BU65170 and other protocol chips, that is, the 1553B protocol stack is implemented through an FPGA, and the FPGA can realize the level conversion function, so the data uplink can be directly connected to the processor, and the downlink can be connected to the transceiver with an isolation transformer, forming a complete 1553B aviation communication system, which can be used as a bus controller BC, a remote terminal RT or a bus monitor BM (hereinafter referred to as: BC, RT, BM), realizing the integration of BC, RT, and BM terminals of 2 1553B buses. At the same time, the device uses the CPU control interface module and the processor for communication connection, forming a simplified user access path, linking the user software application layer to the data transmission path of the bus interface, that is, through the CPU control interface module, the user can directly define the read and write functions through the software layer of the processor to access the 1553B bus protocol device, thereby simplifying the system integration process and reducing the interoperability problems between different components. It can be seen that this device uses fewer devices and does not rely on imported special chip devices, and is completely domestically controlled. It provides most domestic users with a simple, flexible and low-cost domestic implementation device for the aviation 1553B bus protocol, which better expands its universal application in industrial and commercial fields. At the same time, this device makes the system easier to build and deploy through the CPU control interface module, reduces the complexity of development and testing, and reduces the overall development cost.

[0031] The present application is described in detail below with reference to the accompanying drawings.

[0032] The present application embodiment provides a 1553B bus protocol communication device based on FPGA (hereinafter referred to as "device"), referring to Figure 1 The device includes a processor, an FPGA chip and an interface circuit. The FPGA chip implements the 1553B protocol. The FPGA chip includes a CPU control interface module, an FPGA core module, an interface control module and a power management module. The FPGA chip communicates with the processor through the CPU control interface module, and the FPGA chip is physically connected to the 1553B bus through the interface circuit.

[0033] The processor may be, but is not limited to, a DSP, an MCU, an ARM processor, etc., and may also be a computer host. In this embodiment, a DSP processor is used as an example. The DSP processor is used to configure the FPGA, monitor the test process, collect data and analyze the results. It can realize the real-time recording and playback functions of the data and support the user's analysis of the test results. The DSP processor can communicate with the upper user interface through a serial port, and the downstream interface uses an EMIF external memory interface to communicate with the CPU control interface module of the FPGA chip.

[0034] The CPU control interface module is the entry and exit of the FPGA core module operation. The CPU control interface module is used to execute judgment logic to control the input and output of the FPGA core module, so that the FPGA core module can control the bus through the CPU control interface module, including timing control, maintaining command block space, indicating the operation of the command block through register mapping, realizing communication between BC and RT, etc.

[0035] The FPGA core module is used to implement the core logic of the 1553B protocol, including data processing, protocol analysis, bus control and other functions. The uplink interface of the FPGA core module can be connected to the DSP control module using the EMIF external memory interface, and the downlink uses the 3.3V CMOS level standard to receive and send control drive signals to connect to the interface circuit.

[0036] The interface circuit is used to physically connect to the 1553B bus. The interface circuit includes a transceiver with an isolation transformer and uses differential signals for communication to ensure signal integrity. At the same time, it can effectively suppress the influence of external electromagnetic interference (EMI) and noise and improve the signal's anti-interference ability. The interface control module is used to manage and control the signal transmission of the interface circuit, mainly controlling the reception and transmission of the external transceiver circuit, including but not limited to signal conditioning, command and control, etc.

[0037] The power management module is responsible for the power status monitoring, temperature monitoring and management of the processor, FPGA core module and interface circuit, especially the control of power on and off timing.

[0038] In this embodiment, the FPGA chip also includes a level conversion module, which is used to implement a level conversion function to ensure that signals can be correctly transmitted between interfaces with different voltage standards, ensure signal stability and compatibility, and protect the circuit from damage, thereby improving system reliability.

[0039] In this embodiment, the device may also include a user interface, which is used to provide a platform for users to interact with the system. Users can develop control software on a PC to configure FPGA parameters, send test instructions, and receive and analyze results. The user interface is connected to the DSP processor via serial communication, and the serial communication rate is set to 115200bps.

[0040] The design of the CPU control interface module and FPGA core module of this application is described in detail below.

[0041] refer to Figure 2 , the DSP processor mainly implements the read and write functions of the software layer, including register and memory read and write functions. The read and write functions are packaged into read and write timing by the CPU master and given to the CPU control interface module of the FPGA chip through the hardware physical interface for communication. The communication methods include control bus, address bus and data bus. For example, the software layer of the DSP processor calls the write function, specifies the data to be written and the target address, puts the data on the data bus, puts the address on the address bus, and sends a write control signal; the control signal, address and data are transmitted to the CPU control interface module of the FPGA chip through the hardware interface. After receiving the signal, the FPGA writes the data to the corresponding register or memory location according to the address.

[0042] refer to Figure 3 , the CPU control interface module implements the following control logic: Step S11: Initialization phase, a. Ensure that all registers and state machines are reset to the initial state; b. Control the function and state of the bus by mapping registers with specific addresses; c. Set the working mode of the 1553B bus, including host BC mode or slave RT mode, and configure the data buffer and message format.

[0043] Step S12: Clear the status register and the error register.

[0044] Step S13: The CPU control interface module receives the read request or write request input by the DSP and determines whether the local bus is idle. If so, step S14 is executed. If not, the local bus status is re-determined.

[0045] Step S14: Sending a data request. The CPU control interface module formats the request command of the bus protocol controller's read request or write request initiated by the DSP processor, that is, converts the request command into a 1553B standard command format.

[0046] Step S15: Enter the local bus arbitration logic. Automatically trigger the sending of arbitration request signal and wait for the control of the local bus; if the control is obtained, execute step S16; if the control is not obtained, wait for a period of time and try again, that is, return to the local bus status judgment.

[0047] Step S16: Start data transmission and send a read command or a write command.

[0048] Step S17: Determine the response status. If a response is received, continue data transmission and perform write or read operations; if no response is received, record the error and execute the error handling process; Step S18: Verify the received data using CRC check. If there is no error in the verification, end the data transmission. If there is an error in the verification, enter the error handling logic.

[0049] Step S19: End the data transmission. Send a data transmission completion signal to the DSP processor, update the status register, and mark the success or failure of the read or write operation.

[0050] Step S20: Enter the error processing logic. Determine the error type. If a bus error, timeout error, data error, etc. occurs, enter the error processing flow; if error processing is performed, record the error information and re-notify the DSP processor to perform the corresponding error processing.

[0051] Through the control logic of the CPU control interface module, the accuracy of data transmission and reception can be ensured, thereby avoiding data loss or errors and improving communication efficiency. At the same time, the CPU control interface module can solve the synchronization problem of read and write operations. For example, the CPU control interface module solves the synchronization problem of read and write operations through judgment logic and bus arbitration, thereby effectively reading and writing data and ensuring data consistency. Through the timing control and synchronization mechanism of the CPU control interface module, the data transmission efficiency is significantly improved and the delay is reduced. Moreover, the CPU control interface module realizes the conversion of data format through the register mapping function, that is, the correct transmission of commands and data, and the commands are reasonably executed and the correct status is returned. The CPU control interface module can also effectively identify and handle errors in communication, further improving the reliability and integrity of data transmission.

[0052] The following mainly introduces the design of the FPGA core module, which is the core of the 1553B protocol. The device adopts modular RTL circuit design, which decomposes the entire 1553B bus communication protocol into multiple functional modules, which simplifies the design process and improves reusability and maintainability. The FPGA core module includes a protocol implementation module, a data processing module, a timing control module, and an error detection module. Among them, the protocol implementation module is used to generate command words and parse received command words according to the MIL-STD-1553B standard, and design a state machine to process bus commands, responses, error detection and correction functions.

[0053] The data processing module is used to store, forward and analyze data, and uses a FIFO buffer to process data streams to ensure that data is transmitted in the correct timing. Before data transmission, data preprocessing algorithms (data compression and Manchester II encoding) can be used to reduce the amount of data and improve transmission efficiency. The data processing module can also define a data frame structure. The length of the data frame is 20 bytes. The data frame structure includes command words, data words and status words. The format of each data frame is fixed, which simplifies the data, thereby improving the efficiency of data transmission. In this embodiment, the data transmission rate is 1Mbps, and each message contains a maximum of 32 words. The time required to transmit a fixed message is short. The data processing module adopts command / response and "broadcast" communication methods. The bus controller BC can send a time synchronization message to all RTs in a "broadcast" mode, so that all message transmissions on the bus are controlled by instructions issued by the bus controller, and the relevant terminals should respond to the instructions and perform operations.

[0054] The timing control module is used to ensure that the timing of the signal meets the requirements of 1553B. The FPGA clock management and synchronization modules are used to test the communication performance and stability of the 1553B protocol and verify whether the data transmission on the bus meets the protocol specifications.

[0055] The error detection module is used to implement data integrity checks and parity checks for command words, data words, and status words, as well as remote terminal address configuration error detection. The error detection module is used for error detection and correction. The bus protocol contains parity checks and CRC (cyclic redundancy check) error detection mechanisms, which can promptly detect and correct errors in data transmission and reduce the number of retransmissions. The error detection module uses a feedback retransmission error correction method. When the bus controller BC sends a command or a message to a remote terminal RT, the remote terminal should send back a status word within the set response time. If the transmitted message is wrong, the remote terminal will refuse to send back the status word, thereby reporting that the last message transmission is invalid. This method not only enables the system to complete data communication control tasks, but also checks fault conditions and completes fault-tolerant management functions.

[0056] The device can ensure the correctness of functions and timing through this modular design. In simulation verification, the board verification can also be carried out through the host computer test, and the loopback test can be carried out on buses of different numbers to verify the correctness of the system. This device realizes the message transmission format of BC to RT transmission, RT to BC transmission, and RT to RT transmission of RT response mode commands, and realizes the integration of BC, RT, and BM terminals. At the same time, 10 types of fault injection functions can be introduced to improve system reliability.

[0057] refer to Figure 4 , the control process of the communication device provided in this embodiment includes: After the device is powered on, the system automatically starts initialization. The main task of initialization is to start the timing of the CPU control interface module access registers and the back-end memory interface. Another important task of initialization is to read the pre-configured register information and determine the current bus working mode according to the register setting content. There are three types: bus controller BC mode, remote terminal RT mode and bus monitoring BM mode. Once the working mode is determined, the corresponding working mode will be entered to execute the communication function of the corresponding mode. There is a reset option in each working mode for the system to reset and reset, so as to ensure the current device fault recovery and working mode change, and meet the application requirements of online switching working mode.

[0058] After initialization is completed, the user logic can immediately begin to access the internal registers through the CPU control interface module for read and write operations, as well as read and write operations on the data and command block memory space.

[0059] The following is an example of the specific control process of the bus controller BC mode branch operation: refer to Figure 5 After the device is powered on, the system power-on delay automatically starts to initialize, the bus controller BC working mode is set, and the CPU control interface module control timing is started.

[0060] Next, the user logic can immediately start data maintenance, that is, read and write command data and command block memory space through the CPU control interface module to maintain the command block space. Among them, the memory consists of N command block spaces, N represents the number of command blocks required by the application. If the size of the space resource is not limited, N can reach 256, that is, a total of 256 command blocks can be supported. The command block is a continuous memory block of 8 words, which contains the opcodes for controlling the 1553B protocol core and the command words and related data locations in the memory. Each command word transmitted through the bus must be associated with a command block. The 8 continuous memory locations of the command block are a control word, two command words, a data pointer, two status words, a branch address and a timer.

[0061] After completing the command block data maintenance, the user can operate register 8 through the CPU control interface module to instruct the system to start the operation from that command block. It can default to start the operation from command block 1. Next, the user can operate register 0 through the CPU control interface module. Its function is to formally start the bus controller BC. All the previous processes from power-on are preparations before starting the work. Only then does the processor enter the communication moment, that is, the bus controller BC communicates with the remote terminal RT. The FPGA core module operates the specified register through the CPU control interface module to realize the mutual communication between the bus controller and the remote terminal.

[0062] The processor is responsible for sending data bus commands, participating in data transmission, receiving status responses, and monitoring the bus system. The system creates a command block list in memory before. When the bus starts, the bus controller BC will traverse the command block list, send the specified commands and data, and receive the status word and related data words and write them to the corresponding address of the memory. During this process, the bus controller BC monitors all possible 1553B error conditions. If the remote terminal RT does not respond correctly, the bus controller BC will retry the message on the original bus and the backup bus.

[0063] In this embodiment, a user judgment logic can also be provided for the user to decide whether the content of the command block needs to be updated. For example, when the data content of the existing command block no longer meets the current function or test requirements, the update command block is triggered. This setting further improves the flexibility and universality of the device. The operation flow of updating the memory command block is consistent with the operation after the power-on delay initialization is completed, and will not be repeated here.

[0064] refer to Figure 6 , is a schematic diagram of an embodiment of the present application device applied to a 1553B bus communication network topology system, and this application system is composed of device equipment, terminal resistors, couplers, main line cables, and short stubs. The following is a detailed introduction to the network topology structure, which is mainly composed of the following main components: The network topology includes 33 1553B devices. Each device has the same hardware, but based on the bus topology system, each device is assigned / configured with different functions. The 1553B devices include a master station (bus control), a slave station (remote terminal), and a bus monitor. The master station is responsible for controlling and managing communications, while the slave station responds to the master station's requests. Each device contains two 1553B interfaces, that is, two 1553B bus channels. This example only uses one of the 1553B bus channels to send and receive data. Devices communicate through the bus to ensure the reliability and real-time nature of data transmission.

[0065] The terminal resistor is used to provide a stable load to prevent the signal from being reflected on the bus and causing interference. Since the 1553B bus is a differential signal transmission system, terminal resistors (usually 78Ω) need to be connected at both ends of the bus to eliminate signal reflection and ensure signal integrity.

[0066] Couplers are used to connect the 1553B bus with external devices to ensure effective transmission of signals. The role of the coupler is to pass the signal from the bus to the connected device without affecting the signal quality on the bus. It can be passive or active, and the specific choice depends on the application requirements.

[0067] The main line cable is the physical medium that constitutes the 1553B bus. It uses twisted pair or coaxial cable and has good anti-interference ability and signal transmission characteristics. The quality of the main line cable directly affects the communication reliability of the system and must meet the standard requirements of the 1553B protocol.

[0068] The stub is used to connect the 1553B bus to the short-distance transmission between each device to ensure the integrity and transmission efficiency of the signal when connecting the devices. The length and cable type of the stub need to be reasonably selected according to the actual application to avoid signal attenuation or delay.

[0069] These components together form an efficient and reliable 1553B bus network topology that can meet the data transmission needs of complex systems. This device is currently the most complete, convenient and reliable 1553B bus simulation / test device at home and abroad. Its high reliability, good versatility, strong usability and simple operation have been proven not only in multiple aircraft models, but also in the aerospace field.

[0070] In summary, the FPGA-based 1553B bus protocol communication device of the present application reduces production costs and improves market competitiveness through domestic materials and processes. The device has complete simulation / test functions and can simulate and test the data of the MIL-STD-1553B bus system. The FPGA can integrate the 1553B protocol stack and other functions (such as data processing, storage, etc.) on the same chip, reducing the need for external components, and can achieve real-time processing at the hardware level to ensure that the transmission and reception of each data packet are completed within the specified time window. At the same time, the modular design makes maintenance and upgrading more convenient, improves the scalability of the system, and the integrated design reduces the complexity and cost of the system and improves reliability. At the same time, the device is a distributed integrated simulation / test system based on a serial port for the MIL-STD-1553B bus system. It adopts a standardized and normalized design to realize the integration of MIL-STD-1553B (hereinafter referred to as 1553B) bus system design and testing, which completely changes the situation that the development of 1553B bus system simulation / test equipment has always been in a high investment, low efficiency, and low reliability. It can be widely used in the simulation / testing of various 1553B bus systems such as aviation, aerospace, ships, missiles, armored vehicles, etc.

[0071] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A 1553B bus protocol communication device based on FPGA, characterized in that: The device comprises: a processor, an FPGA chip and an interface circuit, wherein the FPGA chip comprises a CPU control interface module and an FPGA core module, wherein the FPGA chip communicates with the processor via the CPU control interface module, and the FPGA chip is physically connected to a 1553B bus via the interface circuit; The FPGA core module is used to implement the core logic of the 1553B bus protocol, and implement bus control through the CPU control interface module according to the 1553B bus protocol, wherein the bus control includes timing control, maintaining command block space, and indicating command block operations through register mapping; The processor configures the registers inside the FPGA chip through the CPU control interface module, and sets the working mode of the 1553B bus to one of a bus controller, a remote terminal or a bus monitor.

2. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The control logic of the CPU control interface module adopts register mapping. In the initialization stage, the CPU control interface module is used to reset the registers and state machine to the initial state, and map the internal register address to the address space of the processor through register mapping, and determine the working mode of the 1553B bus by configuring the register information.

3. A 1553B bus protocol communication device based on FPGA according to claim 2, characterized in that: The CPU control interface module is used to control the input and output of the FPGA core module. The CPU control interface module is used to clean up the status register and the error register, and determine whether the local bus state is idle. If so, send a data request, if not, retry; The CPU control interface module is also used to automatically trigger the sending of an arbitration request signal when entering the local bus arbitration logic, and wait for the local bus control right. If the local bus control right is obtained, data transmission is performed; The CPU control interface module is also used to send write operation data, receive read operation data, and determine the response status of the local bus. If a response is received, the data transmission continues; if no response is received, an error is recorded; The CPU control interface module is also used to send a transmission completion signal and update the status register when the data transmission is completed.

4. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The CPU control interface module is also used for error identification and processing; the CPU control interface module is used to determine the error type and enter the corresponding error processing process according to the error type; the CPU control interface module is also used to record error information, perform retries or corresponding error processing notifications.

5. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The FPGA core module accesses the internal registers through the CPU control interface module, and performs read and write operations on the command data and command block memory space to maintain the command block space.

6. The 1553B bus protocol communication device based on FPGA according to claim 5, characterized in that: The command block space includes 8 words of consecutive memory locations, and the 8 words of consecutive memory locations include a control word, two command words, a data pointer, two status words, a branch address and a timer.

7. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The FPGA core module operates the designated register through the CPU control interface module to realize the mutual communication between the bus controller and the remote terminal; If the bus controller sends a message to a remote terminal, the remote terminal will send back a status word within a set response time; if the message transmission is erroneous, the remote terminal will refuse to send back the status word.

8. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The CPU control interface module has interrupt processing capability. If the 1553B bus core sends an interrupt signal to the CPU control interface module, the CPU control interface module manages the enabling, clearing and priority of the interrupt through the interrupt control register.

9. The 1553B bus protocol communication device based on FPGA according to claim 1, characterized in that: The FPGA core module includes a timing control module and a protocol implementation module. The timing control module is used to control the signal timing to comply with the 1553B bus protocol. The timing control module uses the FPGA clock management and synchronization modules to test and verify the 1553B bus protocol so that the data transmission on the 1553B bus complies with the specifications of the 1553B bus protocol. The protocol implementation module generates command words according to the command format of the 1553B standard and parses the received command words to process the commands and responses of the 1553B bus.

10. The 1553B bus protocol communication device based on FPGA according to claim 9, characterized in that: The FPGA core module also includes a data processing module and an error detection module; The data processing module controls the interface module through the CPU to perform data transmission and data forwarding, and the data processing module is used to store and parse data and use a FIFO buffer to process data streams; The error detection module is used to detect data integrity, parity check of command words, data words and status words, and to perform error correction and detect whether the remote terminal address configuration is wrong using a cyclic redundancy check algorithm.

11. A control method for a 1553B bus protocol communication device based on FPGA, characterized in that: The control method is applicable to the FPGA-based 1553B bus protocol device communication device of any one of claims 1 to 10, and the control method comprises: In the initialization phase, the CPU control interface module is started sequentially, the register information inside the FPGA chip is read, and the working mode of the 1553B bus is set to one of the bus controller, remote terminal or bus monitor according to the register information; After initialization is completed, the CPU controls the interface module to access registers for read and write operations to implement bus control, which includes timing control, maintaining command block space, and indicating command block operations through register mapping.

12. The control method of a 1553B bus protocol communication device based on FPGA according to claim 11, characterized in that: The control method further comprises: In the initialization phase, the registers and state machine are reset to the initial state, the register mapping information is configured, the working mode of the 1553B bus is set, and the status register and error register are cleared; Determine whether the local bus is idle. If so, send a data request and convert the request into the 1553B standard command format; Determine whether the bus enters the local bus arbitration logic. If so, automatically trigger the sending of arbitration request signal and wait for the local bus control right. When the local bus control right is obtained, data transmission is performed; Start data transmission, send commands and wait for responses, determine the response status of the local bus, if a response is received, continue data transmission and perform data verification, if no response is received, record an error; If the data transmission is completed, a transmission completion signal is sent and the status register is updated.

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