Target identification method and device based on double double-precision type, and storage medium

Abstract

The invention relates to the field of data processing, and discloses a target recognition method and device based on a double double-precision type, and a storage medium, the method is applied to a target processor, and the method comprises the steps: obtaining a to-be-recognized image collected by a camera; according to the cache surplus, determining the size of each block, and carrying out double-double type data batch loading on the to-be-identified image based on the size of each block to obtain to-be-processed data corresponding to each block; according to each operation type in a preset target identification algorithm, determining an initial operation instruction corresponding to each operation type in the target processor; according to each initial operation instruction and a preset target recognition algorithm, determining each acceleration processing instruction; and determining a target recognition result according to each acceleration processing instruction and the to-be-processed data corresponding to each block, thereby realizing high-precision data processing in the field of automatic driving, improving the accuracy of target recognition, and greatly improving the operation efficiency while ensuring the data precision.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a target recognition method, device and storage medium based on double double precision type. Background Art

[0002] In the field of high-performance computing, such as the target recognition field of autonomous driving, solutions rely on very precise numerical simulations. During the solution process, due to the accumulation of rounding errors, it is easy to make the algorithm difficult to converge or the results inaccurate, so high-precision floating-point numerical calculations are very important.

[0003] However, the 64-bit double floating-point type natively supported by current processor hardware can no longer provide sufficiently high precision. The general solution is to use software to simulate high precision, but this will greatly increase the running time of the algorithm and make the processing results lose timeliness.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a target recognition method, device and storage medium based on double double precision type, which realizes high-precision data processing in the field of autonomous driving, improves the accuracy of target recognition, and greatly improves computing efficiency while ensuring data accuracy.

[0006] An embodiment of the present invention provides a target recognition method based on double double precision type, which is applied to a target processor. The method includes:

[0007] Obtain the image to be recognized collected by the camera;

[0008] Determine the block size according to the remaining amount of the cache, and perform batch loading of double-double type data on the image to be identified based on the block size to obtain the data to be processed corresponding to each block;

[0009] Determining, according to each operation type in the preset target recognition algorithm, initial operation instructions corresponding to each operation type in the target processor;

[0010] Determining each accelerated processing instruction according to each initial operation instruction and the preset target recognition algorithm;

[0011] Determine the target recognition result according to each accelerated processing instruction and the to-be-processed data corresponding to each block;

[0012] The target processor supports double-double type processing.

[0013] An embodiment of the present invention provides an electronic device, the electronic device comprising:

[0014] Processor and memory;

[0015] The processor is used to execute the steps of the target recognition method based on double double precision type described in any embodiment by calling the program or instruction stored in the memory.

[0016] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program or instruction, wherein the program or instruction enables a computer to execute the steps of the target recognition method based on double-double precision type described in any embodiment.

[0017] The embodiments of the present invention have the following technical effects:

[0018] By acquiring the image to be recognized collected by the camera, determining the block size according to the remaining amount of the cache, and batch loading double-double type data of the image to be recognized based on the block size, the data to be processed corresponding to each block is obtained, and according to each operation type in the preset target recognition algorithm, the initial operation instructions corresponding to each operation type in the target processor are determined, and according to each initial operation instruction and the preset target recognition algorithm, each accelerated processing instruction is determined, and according to each accelerated processing instruction and the data to be processed corresponding to each block, the target recognition result is determined, thereby realizing high-precision data processing in the field of autonomous driving, improving the accuracy of target recognition, and greatly improving the computing efficiency while ensuring data accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a flow chart of a target recognition method based on double double precision type provided by an embodiment of the present invention;

[0021] Figure 2 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0023] The double double precision type target recognition method provided by the embodiment of the present invention is mainly suitable for high-precision recognition of targets around the vehicle, so as to facilitate various subsequent automatic driving operations. The double double precision type target recognition method provided by the embodiment of the present invention can be integrated in an electronic device and executed by the electronic device.

[0024] Embodiment 1

[0025] Figure 1 is a flow chart of a target recognition method based on double double precision type provided by an embodiment of the present invention. Figure 1 The target recognition method based on the double double precision type is applied to the target processor. The double double precision type is the double-double type. The target processor supports the double-double type processing. The target processor may include the extended support of the multi-word format double-double type. At the same time, the acceleration optimization of the double-double type operation is performed for the hardware architecture of the target processor. For example, the target processor may be a domestic Feiteng processor. Of course, other processors with the above characteristics may also be used as the target processor. The target recognition method based on the double double precision type specifically includes:

[0026] S110: Obtain an image to be recognized captured by a camera.

[0027] The camera is a camera installed on the vehicle, and the user captures the image of the vehicle's surroundings. The image to be identified is an image that needs to be subsequently identified as a target, and is an image of the vehicle's surroundings.

[0028] Specifically, many autonomous driving operations need to rely on image-based target recognition algorithms. Therefore, it is necessary to collect images of the vehicle's surroundings through the camera installed on the vehicle, which are the images to be recognized.

[0029] S120 , determining a block size according to the remaining amount of the cache, and batch loading double-double type data of the image to be recognized based on the block size to obtain the data to be processed corresponding to each block.

[0030] The remaining amount of cache is the remaining amount of each level of cache of the target processor. The block size is the size of data used to load the image to be identified later. It can be understood that the block size is less than or equal to the remaining amount of cache. The data to be processed is the double-double type data loaded each time the image to be identified is loaded according to the block size.

[0031] Specifically, first determine the remaining cache size of the target processor, and use the remaining cache size or the difference between the remaining cache size and the reserved size as the block size, where the reserved size is a predetermined size to ensure that there is space in the cache. Then, double-double type data can be loaded for the image to be recognized multiple times according to the block size, that is, batch loading, thereby obtaining the data to be processed at each loading, that is, the data to be processed corresponding to each block.

[0032] The double-double type is a double-double precision type, which stores two double-type data, of which the hi part (high part) can store the nearest similar value of the operation result; the lo part (low part) stores the error term to capture the precision lost due to rounding. At the same time, it is necessary to perform multi-byte alignment for the double-double type data in the memory of the target processor to maintain the access memory continuity of the members in the structure and ensure that multiple double-double type data can be aligned to the access boundary of SIMD (Single Instruction Multiple Data) acceleration instructions.

[0033] Based on the above example, the following method can be used to determine the block size according to the remaining amount of the cache, and batch load the double-double type data of the image to be recognized based on the block size to obtain the data to be processed corresponding to each block:

[0034] For each level of cache, obtain the single-level remaining amount of the cache, and take the sum of the single-level remaining amounts of caches at all levels as the cache remaining amount;

[0035] Determine the block size based on the remaining amount of cache;

[0036] In response to the remaining data size of the image to be identified being greater than or equal to the block size, based on the block size, loading part of the remaining data of the image to be identified into double-double type data to be processed, and updating the remaining data and the remaining data size until the remaining data size is less than the block size;

[0037] In response to the remaining data size being smaller than the block size, the remaining data of the image to be recognized is loaded into double-double type data to be processed based on the remaining data size.

[0038] The single-level remaining amount is the current free storage amount of each level of cache. The block size is less than or equal to the cache remaining amount. The remaining data is the part of the data that is not loaded in the image to be recognized, and the remaining data size is the size of the remaining data.

[0039] Specifically, for each level of cache, the free storage capacity of the cache at that level, that is, the single-level residual capacity, is obtained, and then the single-level residual capacity of each level of cache is summed, and the sum value is used as the cache residual capacity. The cache residual capacity or the difference between the cache residual capacity and the reserved size is used as the block size, wherein the reserved size is a predetermined size to ensure that there is space in the cache. If the remaining data size of the image to be identified is greater than or equal to the block size, it means that data can be loaded according to the block size. Therefore, based on the block size, part of the remaining data of the image to be identified is loaded in double-double type, and the data that has not been loaded is updated, that is, the remaining data and the remaining data size are updated until the remaining data size is less than the block size. If the remaining data size is less than the block size, it means that it is the last load, and the amount of data loaded is less than the block size, and only the remaining part can be loaded. Therefore, based on the remaining data size, the remaining data of the image to be identified is loaded in double-double type. Thus, the data to be processed after each block processing can be obtained.

[0040] Definition of double-double type data structure:

[0041]

[0042]

[0043] Use the vectorized load instructions provided by the target processor to load multiple double-double data into registers at one time during operation. And adjust the block size of batch data according to the capacity of each level of cache of the target processor (cache remaining amount) to keep the data in the cache as much as possible during operation, reducing the time overhead of accessing the memory outside the cache.

[0044] Since the double-double type data distinguishes between a high-order double part and a low-order double part, for reading data of the dd_type type (double-double type), the target processor can use vectorized instructions for the basic double type to separately vectorize and load the high-order and low-order parts.

[0045] When the size of the input data is not a multiple of the block size, there will be remaining elements (remaining data) that cannot be processed by the vectorized instruction at one time, so these remaining elements will be processed separately after the vectorized program.

[0046] S130. Determine, according to each operation type in the preset target recognition algorithm, an initial operation instruction corresponding to each operation type in the target processor.

[0047] The preset target recognition algorithms are target recognition algorithms in the field of autonomous driving, and the operation types are types of arithmetic operations in each analysis and processing step in the preset target recognition algorithm, such as addition and subtraction. The initial operation instructions are high-precision operation instructions constructed in the target processor for the operation type.

[0048] Specifically, an algorithm for processing the data to be processed to identify the target of the vehicle's surrounding environment is determined as a preset target recognition algorithm. It can be understood that the preset target recognition algorithm is a logical idea, so each operation type in the preset target recognition algorithm can be accelerated instruction processing, and the initial operation instruction corresponding to each operation type in the preset target recognition algorithm can be determined from the acceleration instructions corresponding to each operation type in the target processor.

[0049] Based on the above example, the initial operation instructions corresponding to each operation type in the target processor may be determined according to each operation type in the preset target recognition algorithm in the following manner:

[0050] According to the preset target recognition algorithm, determining each operation type in the preset target recognition algorithm;

[0051] According to each operation type and the candidate operation instructions corresponding to each candidate type stored in the target processor, an initial operation instruction corresponding to each operation type is determined.

[0052] The operation instructions to be selected are acceleration instructions corresponding to different types of operations stored in the target processor.

[0053] Specifically, the preset target recognition algorithm is analyzed to determine the various operation types in the preset target recognition algorithm. Then, according to each determined operation type, the candidate operation instructions corresponding to each candidate type stored in the target processor are matched to obtain the initial operation instructions corresponding to each determined operation type.

[0054] Based on the above example, the candidate operation instructions corresponding to each candidate type stored in the target processor can be determined in the following manner:

[0055] For each type to be selected, determine the high-order part of the target data according to the high-order part of the first input data, the high-order part of the second input data, and the vectorization instruction corresponding to the type to be selected;

[0056] The high-order part of the first input data, the high-order part of the second input data and the high-order part of the target data are used as error source data, and error compensation data is determined according to the error source data and the type to be selected;

[0057] The low-order part of the target data is determined according to the first input data, the second input data, the error compensation data and the type to be selected.

[0058] Among them, the types to be selected are various operation types stored in advance. The first input data and the second input data can be understood as two input data when performing the operation of the selected type, such as two addends of addition, dividend and divisor of division, etc. The first input data and the second input data are both double-double type data. Vectorized instructions can be understood as various accelerated processing instructions, which are instructions adapted to the target processor and can perform accelerated processing. Error data is the result data after the first input data and the second input data perform the operation of the selected type. Error source data is data that will cause errors when performing the operation of the selected type. Error compensation data is error data generated when the high-order part operation has been performed.

[0059] Specifically, for each type to be selected, corresponding operation instructions to be selected can be constructed respectively. First, the high-order part of the first input data and the high-order part of the second input data are calculated by the vectorization instruction corresponding to the type to be selected to obtain the high-order part of the target data. Then, the high-order part of the first input data, the high-order part of the second input data and the high-order part of the target data are used as error source data. The error source data is processed according to the error calculation method corresponding to the type to be selected to obtain error compensation data. Finally, the low-order part of the first input data and the low-order part of the second input data are calculated by the vectorization instruction corresponding to the type to be selected, and the error compensation data is used to compensate to obtain the low-order part of the target data. In this way, the high-order part and the low-order part of the target data can be obtained, and the above process is the operation instruction to be selected corresponding to the type to be selected.

[0060] It is understandable that the core of double-double type operations is to use the idea of ​​error-free transformation to retain and store rounding errors. It mainly includes three parts: high-order approximate term calculation, rounding error correction, and low-order error term calculation. At the same time, double-double type operations can essentially be divided into a combination of operations on the high-order part (double data) and the low-order part (double data), so the target processor's natively supported double type SIMD instructions can be used in combination to accelerate operations.

[0061] First, the high-order approximate term is calculated, that is, the high-order part of the target data. The high-order part of the input data that has been vectorized and loaded is directly operated, and the appropriate candidate operation instruction on the target processor is selected for operation acceleration according to the actual operation type. The most approximate high-order result is obtained, which will be assigned to the high-order part of the final result, that is, the high-order part of the target data. Further, rounding error correction. Mainly based on the specific source of rounding errors in different operation types, these errors are recalculated and saved, and various operations for double types in the error compensation algorithm are replaced with the candidate operation instructions corresponding to the target processor for acceleration. Finally, the low-order error term is calculated. Mainly based on the high-order approximate term results, rounding errors, and high and low-order information in the previous two steps, the low-order error term in the final result, that is, the low-order part of the target data, is further calculated. Similarly, according to the actual operation type combination, the appropriate SIMD operation instruction on the target processor is used for operation acceleration, and the operation value is assigned to the low-order part of the final result.

[0062] Furthermore, since double-double type data needs to store the high-order double type data and the low-order double type data separately, it is also necessary to use the vectorized storage instruction of the target processor to write the high-order and low-order parts back to the final result separately.

[0063] Based on the above example, if the type to be selected is the addition type, the error compensation data can be determined according to the error source data and the type to be selected in the following manner:

[0064] By using a vectorized subtraction instruction, a difference between a high-order portion of the target data and a high-order portion of the first input data is calculated to obtain first intermediate data;

[0065] According to the high-order part of the first input data, the high-order part of the second input data and the first intermediate data, the error compensation data is determined by a vectorized subtraction instruction and a vectorized addition instruction.

[0066] The first intermediate data is the difference between the high-order part of the target data and the high-order part of the first input data after vectorized subtraction.

[0067] Specifically, the high-order part of the target data is used as the minuend, the high-order part of the first input data is used as the subtrahend, and the calculated difference is used as the first intermediate data through the vectorized subtraction instruction. Then, the error compensation data is calculated by continuous acceleration instructions, that is, the high-order part of the first input data is used as the minuend, the high-order part of the first intermediate data is used as the subtrahend, and the difference result is obtained through the vectorized subtraction instruction, the high-order part of the second input data is used as the minuend, the high-order part of the first intermediate data is used as the subtrahend, and the difference result is obtained through the vectorized subtraction instruction, and the two difference results are processed by the vectorized addition instruction to obtain the error compensation data. It can be understood that the above steps can be obtained by calculating the acceleration instruction in one step without step-by-step processing.

[0068] Accordingly, the low-order part of the target data is determined according to the first input data, the second input data, the error compensation data and the type to be selected in the following manner:

[0069] According to the low-order part of the first input data, the low-order part of the second input data and the error compensation data, accumulation is performed through a vectorized addition instruction to determine the low-order part of the target data.

[0070] Specifically, the low-order part of the first input data, the low-order part of the second input data and the error compensation data are obtained, and the above three data are accumulated through a vectorized addition instruction, which is the low-order part of the target data.

[0071] Exemplarily, firstly, the vectorized loading of the high and low bits of the data is performed separately. When looping through the block data input according to the block size, each iteration will use the double type vectorized loading instruction to first batch read the high-order floating-point numbers of x (first input data) and y (second input data) into the register. The specific instructions are x_hi=vld_f64(x.hi), y_hi=vld_f64(y.hi), where vld_f64 is a vectorized loading instruction, x_hi is the high-order part of x after loading, y_hi is the high-order part of y after loading, x.hi is the high-order part of x before loading, and y.hi is the high-order part of y before loading. After that, the low-order floating-point numbers of x and y are vectorized loaded. The specific instructions are x_lo=vld_f64(x.lo), y_lo=vld_f64(y.lo), where x_lo is the low-order part of x after loading, y_lo is the low-order part of y after loading, x.lo is the low-order part of x before loading, and y.lo is the low-order part of y before loading. Further, the high-order approximate result item is calculated, that is, the high-order part of the target data. The vectorized addition instruction is used to directly add the high-order parts of x and y. The instruction is sum_hi=vadd_f64(x_hi,y_hi), vadd_f64 is a vectorized addition instruction, and sum_hi is the high-order part of the target data. Using the above method, it will automatically round to the double type floating point number closest to the theoretical addition result to obtain the high-order approximate item of the final result. Next, an error-free transformation is performed. First, a vectorized subtraction instruction is used to calculate the difference between sum_hi and x_hi, that is, the first intermediate data: v = vsub_f64 (sum_hi, x_hi), where vsub_f64 is a vectorized subtraction instruction, and v is used to compensate for the error that may occur in the operation, that is, the first intermediate data. After that, the error term e (error compensation data) is calculated: e = vadd_f64 (vsub_f64 (x_hi, v), vsub_f64 (y_hi, v)), e uses the information of v to perform error correction and calculates the low-order part that may have been lost. Further, the low-order error term is calculated, and the vectorized addition instruction is first used to perform an operation on the low-order part of the two inputs to obtain a low-order result, and then the error term e is compensated into the low-order result: sum_lo = vadd_f64 (vadd_f64 (x_lo, y_lo), e_hi), and the low-order error term of the final result, that is, the low-order part of the target data, is obtained. Finally, the high-order approximate result item and the low-order error item are written back to the final result. Specifically, the high-order and low-order separated write-backs can be performed using vectorized storage instructions: vst_f64(res.hi,sum_hi), vst_f64(res.lo,sum_lo).

[0072] Based on the above example, if the type to be selected is the multiplication type, the error compensation data can be determined according to the error source data in the following manner:

[0073] Determine the second intermediate data by vectorizing the multiplication instruction according to the high-order part of the first input data and the splitting constant, and determine the third intermediate data by vectorizing the multiplication instruction according to the high-order part of the second input data and the splitting constant;

[0074] The error compensation data is determined according to the high-order part of the target data, the second intermediate data and the third intermediate data by using a vectorized subtraction instruction and a vectorized multiplication instruction.

[0075] The splitting constant is a preset constant, specifically 2^27+1. The second intermediate data is data obtained by vectorizing the high-order part of the first input data and the splitting constant. The third intermediate data is data obtained by vectorizing the high-order part of the second input data and the splitting constant.

[0076] Specifically, the high-order part of the first input data and the split constant are used as two multipliers, and the second intermediate data is obtained by a vectorized multiplication instruction, and the high-order part of the second input data and the split constant are used as two multipliers, and the third intermediate data is obtained by a vectorized multiplication instruction. The second intermediate data and the third intermediate data are used as the minuend by the operation result of the vectorized multiplication instruction, and the high-order part of the target data is used as the subtrahend, and the error compensation data is obtained by a vectorized subtraction instruction. It can be understood that the above steps can be obtained by a one-step acceleration instruction calculation without step-by-step processing.

[0077] Accordingly, the low-order part of the target data may be determined according to the first input data, the second input data and the error compensation data in the following manner:

[0078] Determine fourth intermediate data according to the high-order part of the first input data and the low-order part of the second input data by vectorizing the multiplication instruction;

[0079] Determine fifth intermediate data according to the low-order part of the first input data and the high-order part of the second input data by vectorizing the multiplication instruction;

[0080] Determine sixth intermediate data according to the low-order part of the first input data and the low-order part of the second input data by vectorizing the multiplication instruction;

[0081] Determine low-order product data by accumulating the fourth intermediate data, the fifth intermediate data, and the sixth intermediate data through a vectorized addition instruction;

[0082] According to the low-order product data and the error compensation data, the low-order part of the target data is determined by vectorizing the addition instruction.

[0083] The fourth intermediate data is data obtained by vectorizing the multiplication of the low-order part of the first input data and the high-order part of the second input data. The fifth intermediate data is data obtained by vectorizing the multiplication of the low-order part of the first input data and the high-order part of the second input data. The sixth intermediate data is data obtained by vectorizing the multiplication of the low-order part of the first input data and the low-order part of the second input data. The low-order product data is data obtained by vectorizing the addition and accumulation of the fourth intermediate data, the fifth intermediate data, and the sixth intermediate data.

[0084] Specifically, the high-order part of the first input data and the low-order part of the second input data are used as two multipliers, and the vectorized multiplication instruction is used to perform an operation to obtain the fourth intermediate data. The low-order part of the first input data and the high-order part of the second input data are used as two multipliers, and the vectorized multiplication instruction is used to perform an operation to obtain the fifth intermediate data. The low-order part of the first input data and the low-order part of the second input data are used as two multipliers, and the vectorized multiplication instruction is used to perform an operation to obtain the sixth intermediate data. The fourth intermediate data, the fifth intermediate data, and the sixth intermediate data are accumulated by a vectorized addition instruction to obtain low-order product data. According to the low-order product data and the error compensation data, the low-order part of the target data is determined by a vectorized addition instruction.

[0085] Exemplarily, a vectorized load is performed similar to the addition type to separate the high and low bits of data. Further, the high-order product (the high-order part of the target data) is calculated, specifically, the high-order part of x and y is directly multiplied using a vectorized multiplication instruction: prod_hi = vmul_f64 (x_hi, y_hi), and the high-order product term prod_hi of the final result is obtained, and vmul_f64 is a vectorized multiplication instruction. The split constant split = 2^27+1 is used to further split the high-order part of x_hi and y_hi: x_split = vmul_f64 (x_hi, vdup_f64 (split)), y_split = vmul_f64 (y_hi, vdup_f64 (split)), wherein x_split is the second intermediate data, and y_split is the third intermediate data. This process is intended to intercept high-order information to improve the accuracy of the calculation. Further, calculate the low-order product (low-order product data), first calculate two mixed products respectively: term1 = vmul_f64(x_hi, y_lo) (the high-order part of x is multiplied by the low-order part of y to obtain the fourth intermediate data term1), term2 = vmul_f64(x_lo, y_hi) (the low-order part of x is multiplied by the high-order part of y to obtain the fifth intermediate data term2), then calculate term3 = vmul_f64(x_lo, y_lo) (the low-order part of x is multiplied by the low-order part of y to obtain the sixth intermediate data term3), and then, accumulate these products: low_product = vadd_f64(vadd_f64(term1, term2), term3) to obtain the low-order product. Furthermore, error compensation is performed, specifically, the error compensation term e is calculated using the further split high-order product (the second intermediate data and the third intermediate data) and the high-order product term of the result (the high-order part of the target data): e = vsub_f64 (vmul_f64 (x_split, ysplit), prod_hi), and this error compensation data is used to compensate for the deviation that may occur in the operation. Then, the low-order product is added to the error compensation data, sum_lo = vadd_f64 (low_product, e), to obtain the final low-order result, that is, the low-order part of the target data. Finally, the high-order product and the low-order result are written back to the final result, specifically, the high-order and low-order separation write-back can be performed using vectorized storage instructions: vst_f64 (res.hi, prod_hi), vst_f64 (res.lo, sum_lo).

[0086] Based on the above example, if the type to be selected is the division type, the error compensation data can be determined according to the error source data and the type to be selected in the following manner:

[0087] Determine seventh intermediate data according to the high-order part of the target data and the high-order part of the second input data by vectorizing the multiplication instruction;

[0088] By using a vectorized subtraction instruction, a difference between a high-order portion of the first input data and the seventh intermediate data is calculated to obtain eighth intermediate data;

[0089] The quotient of the eighth intermediate data and the high-order part of the second input data is calculated by a vectorized division instruction to obtain error compensation data.

[0090] The seventh intermediate data is data obtained by vectorizing the high-order part of the target data and the high-order part of the second input data. The eighth intermediate data is difference data obtained by vectorizing the high-order part of the first input data minus the seventh intermediate data.

[0091] Specifically, the high-order part of the target data and the high-order part of the second input data are used as two multipliers, and the seventh intermediate data is obtained by vectorized multiplication instruction. The high-order part of the first input data is used as the minuend, and the seventh intermediate data is used as the subtrahend, and the eighth intermediate data is obtained by vectorized subtraction instruction. The eighth intermediate data is used as the dividend, and the high-order part of the second input data is used as the divisor, and the error compensation data is obtained by vectorized division instruction.

[0092] Accordingly, the low-order part of the target data may be determined according to the first input data, the second input data, the error compensation data and the type to be selected in the following manner:

[0093] According to the low-order part of the first input data, the high-order part of the second input data and the error compensation data, the low-order part of the target data is determined by a vectorized division instruction and a vectorized addition instruction.

[0094] Specifically, the low-order part of the first input data is vectorized and divided by the high-order part of the second input data to obtain a preliminary low-order quotient, and the error compensation data is superimposed on the preliminary low-order quotient through a vectorized addition instruction for error compensation to obtain the low-order part of the target data.

[0095] Exemplarily, a vectorized load is performed similar to the addition type to separate the high and low bits of data. Further, the high-order quotient is calculated, and the high-order parts of x and y are directly divided using the vectorized division instruction: quot_hi = vdiv_f64 (x_hi, y_hi), and the high-order quotient quot_hi of the final result (the high-order part of the target data) is obtained, wherein vdiv_f64 is a vectorized division. Further, the high-precision remainder is calculated, and the high-precision remainder (seventh intermediate data) is calculated using the vectorized multiplication instruction according to the high-order quotient: prod = vmul_f64 (quot_hi, y_hi), and the remainder (eighth intermediate data) is calculated using the vectorized subtraction instruction: r = vsub_f64 (x_hi, prod). Further, the error compensation term (error compensation data) is calculated, specifically, the quotient of the remainder r and the high-order part of y (error compensation data) is calculated using a vectorized division instruction: q_rem = vdiv_f64 (r, y_hi), and this quotient is used to compensate for the error in subsequent calculations. Further, the low-order quotient is calculated, the low-order of x is divided by the high-order of y to obtain a preliminary low-order quotient, and q_rem is used for error compensation to obtain a low-order result (the low-order part of the target data): quot_lo = vadd_f64 (vdiv_f64 (x_lo, y_hi), q_rem), quot_lo is the low-order part of the target data. Finally, the high-order quotient and the low-order result are written back to the final result. Use vectorized storage instructions to write back the high and low bits separately: vst_f64 (res.hi, quot_hi), vst_f64 (res.lo, quot_lo).

[0096] S140, determining each accelerated processing instruction according to each initial operation instruction and a preset target recognition algorithm.

[0097] The accelerated processing instructions are instructions obtained by substituting each initial operation instruction into a preset target recognition algorithm.

[0098] Specifically, each initial operation instruction is substituted into the preset target recognition algorithm for processing, and each accelerated processing instruction corresponding to the preset target recognition algorithm can be obtained. It can be understood that the target recognition can be performed by executing each accelerated processing instruction.

[0099] S150, determining a target recognition result according to each accelerated processing instruction and the to-be-processed data corresponding to each block.

[0100] The target recognition result is the targets around the vehicle obtained by recognizing the image to be recognized captured by the camera.

[0101] Specifically, target recognition processing is performed on the to-be-processed data corresponding to each block by using each acceleration processing instruction corresponding to the preset target recognition algorithm, so as to obtain a target recognition result.

[0102] It can be understood that the first input data X and the second input data Y are both double-double type vectors, each vector element contains a high-order part hi and a low-order part lo, and a double-double type result vector is returned. Let x and y represent the block data of the first input vector X and the second input vector Y in the loop iteration, respectively, and the loop traverses the input vector data, and the iteration index steps the length of the block size each time.

[0103] Image recognition algorithms are crucial in autonomous driving technology. They identify environmental elements such as road signs, pedestrians, and vehicles by analyzing the real-time images to be recognized captured by the camera. Feature matching is the core of this process, which involves extracting key features from the image and comparing them with the features in the database to achieve accurate recognition. Feature matching relies on a variety of mathematical operations, especially when using the SIFT (Scale-Invariant Feature Transform) algorithm. The description and matching of feature points requires accurate calculation of image gradients and feature vectors. These algorithms involve a large number of floating-point operations, especially when normalizing and measuring similarity of feature descriptors, which have extremely high requirements for numerical accuracy. Even a small rounding error may cause feature points to be incorrectly matched, which in turn causes the autonomous driving system to misjudge the meaning of road signs, which may lead to inappropriate reactions, such as sudden deceleration or lane changes.

[0104] It is also understandable that in complex scenarios, such as nighttime driving or bad weather, the image quality of the image to be identified degrades, which increases the difficulty of feature extraction. In this case, ordinary floating-point operations often cannot meet the high-precision requirements, and subtle changes may be magnified, resulting in matching errors. Therefore, it is particularly important to adopt higher-precision numerical calculation methods to ensure that the system maintains accuracy and safety in various environments.

[0105] The preset target recognition algorithm usually includes processes such as image gradient calculation, feature descriptor, similarity measurement, and normalization of feature descriptors. Using double-double type for data processing in these processes can effectively improve the reliability of subsequent target recognition results. Specifically, in feature matching, the calculation of image gradient is crucial. Using double-double type can reduce rounding errors in gradient calculation, thereby ensuring that the extracted feature points are more accurate. Feature descriptors (such as descriptors in SIFT) usually rely on weighted calculations of pixels around feature points. Using double-double type data for processing can ensure the high accuracy of these weighted calculations and avoid false matching caused by small errors in the feature matching process. When calculating the similarity between feature vectors (such as Euclidean distance), using double-double type can improve the accuracy of calculation, which is particularly important for ensuring the reliability of feature matching, because small changes in similarity measurement may directly affect the matching results. Normalization of feature descriptors involves division operations, and traditional floating-point operations may cause inaccurate results due to rounding errors. Using double-double for normalization can effectively improve the reliability of the results.

[0106] Based on the above example, if the target processor includes at least two cores and the number of images to be recognized is at least two, the block size can be determined according to the remaining amount of the cache in the following manner, and double-double type data can be batch loaded for the images to be recognized based on the block size to obtain the data to be processed corresponding to each block:

[0107] According to the number of images to be recognized, the number of initial tasks is determined, and according to the number of initial tasks and the number of cores of the target processor, the number of tasks to be processed corresponding to each core is determined;

[0108] For each core, determine the core block size based on the remaining amount of the core cache;

[0109] Based on the core's block size, batch load double-double type data for the number of to-be-recognized images corresponding to the core's pending tasks.

[0110] The number of initial tasks is the number of images to be recognized, which is the number of images that need to be recognized. The number of cores is the number of cores in the target processing. The number of tasks to be processed is the number of tasks that each core needs to process.

[0111] Specifically, the number of images to be identified is taken as the initial number of tasks, and the initial number of tasks is divided by the number of cores of the target processor to obtain the number of tasks to be processed corresponding to each core. For each core, according to the cache remaining amount of the core, the cache remaining amount or the difference between the cache remaining amount and the reserved size is taken as the block size of the core, wherein the reserved size is a predetermined size to ensure that there is space left in the cache of the core. Each core is processed in parallel, and for each core, based on the block size of the core, double-double type data is batch loaded for the images to be identified for the number of tasks to be processed corresponding to the core. Subsequent steps can also be continued, that is, the cores are processed in parallel, which will not be repeated in this embodiment.

[0112] It is understandable that when the double-double data processing tasks that require batch operations (such as the number of images to be recognized) reach a certain scale, the loop block strategy will be further set according to the number of multi-cores (number of cores) of the target processor. With the help of the OpenMP (shared memory parallel programming) thread optimization library, by embedding the loop parallel identifier outside the loop body of the program and adding the task scheduling statement in OpenMP, the original number of tasks that need to be processed in the linear loop is evenly distributed to each core on the target processor, and each core processes "number of tasks / number of cores" (initial number of tasks / number of cores of the target processor) block tasks (number of tasks to be processed tasks), thereby performing hardware multi-core parallel operations. When the overall number of tasks cannot be completely divided by the number of cores, the dynamic scheduling strategy of OpenMP will dynamically allocate the remaining tasks to the idle cores.

[0113] Introducing the double-double type into the target processor, such as the Phytium processor, effectively solves the problem of non-convergence of algorithms and inaccurate results caused by insufficient precision in ultra-large-scale numerical simulation applications, and expands the capabilities of the target processor in high-precision numerical simulation operations. In addition, based on the multi-core architecture and hardware acceleration instruction set of the target processor, combined with the idea of ​​error-free transformation, large-scale double-double type calculations are accelerated in parallel on the Phytium processor, which greatly improves the computing efficiency while ensuring data accuracy.

[0114] It can also be understood that the behavior of the overall double-double type vectorized acceleration algorithm can be split, and the pipeline parallelism between different instruction behaviors will be further performed under the data block condition allowed by the hardware register capacity of the target processor. When the error-free transformation algorithm of the current batch of block data is performed, the vectorized loading of the next batch of block data in the loop iteration can be performed simultaneously, and the vectorized storage of the previous batch of block results in the loop history can be performed simultaneously, thereby increasing the operating efficiency of concurrent data processing.

[0115] The technical solution of the above example improves the ability of the target processor in high-precision simulation calculation. When traditional double-precision floating-point calculation is difficult to meet the convergence requirements, by introducing double-double type high-precision calculation and error compensation technology for the target processor, the stability and convergence efficiency of the target recognition algorithm are significantly improved, which can effectively deal with complex and difficult-to-converge numerical simulation problems and ensure higher precision calculation results. In addition, it can achieve high-precision calculation and efficient accelerated execution of double-double type data on the target processor. By making full use of the multi-core parallel architecture of the target processor, combined with SIMD instruction set and multi-threading technology, the parallel acceleration of double-double type floating-point operations is successfully achieved. While ensuring the calculation accuracy, the execution time of large-scale double-double type calculation tasks is greatly shortened, and the overall computing performance is improved. In addition to the target recognition field of autonomous driving, it can also be applied to large-scale scientific research and high-precision engineering simulation tasks in high-performance computing, such as atmospheric, climate and ocean simulation, molecular dynamics simulation, supernova simulation, celestial orbit simulation, computational geometry and other application fields, which significantly optimizes the utilization efficiency of computing resources. Introducing double-double type high-precision computing in the target processor can also enhance the competitiveness of the independent supercomputing ecosystem. Through the efficient adaptation of the double-double type in the target processor, the ability of the independent supercomputing platform in the field of high-precision and high-performance computing has been significantly improved. This not only enhances the competitiveness of the independent supercomputing ecosystem in the domestic and foreign markets, but also provides stable and reliable high-performance computing support for scientific research, industrial and engineering computing, and promotes the further development and application of domestic supercomputing technology.

[0116] The present invention has the following technical effects: by acquiring an image to be recognized acquired by a camera, determining a block size according to a remaining amount of a cache, and batch loading double-double type data of the image to be recognized based on the block size, obtaining the data to be processed corresponding to each block, determining the initial operation instructions corresponding to each operation type in the target processor according to each operation type in a preset target recognition algorithm, determining each accelerated processing instruction according to each initial operation instruction and a preset target recognition algorithm, determining a target recognition result according to each accelerated processing instruction and the data to be processed corresponding to each block, thereby realizing high-precision data processing in the field of autonomous driving, improving the accuracy of target recognition, and greatly improving the computing efficiency while ensuring data accuracy.

[0117] Embodiment 2

[0118] Figure 2 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 2As shown, the electronic device 200 includes one or more processors 201 and a memory 202 .

[0119] The processor 201 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 200 to perform desired functions. The processor 201 is a target processor.

[0120] The memory 202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 201 may run the program instructions to implement the target recognition method based on the double double precision type and / or other desired functions of any embodiment of the present invention described above. Various contents such as initial external parameters, thresholds, etc. may also be stored in the computer-readable storage medium.

[0121] In one example, the electronic device 200 may further include: an input device 203 and an output device 204, which are interconnected via a bus system and / or other forms of connection mechanisms (not shown). The input device 203 may include, for example, a keyboard, a mouse, etc. The output device 204 may output various information to the outside, including early warning information, braking force, etc. The output device 204 may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0122] Of course, to simplify, Figure 2 Only some of the components related to the present invention in the electronic device 200 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application conditions, the electronic device 200 may also include any other appropriate components.

[0123] In addition to the above methods and devices, an embodiment of the present invention may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the target recognition method based on double double precision type provided by any embodiment of the present invention.

[0124] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present invention, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0125] In addition, an embodiment of the present invention may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the target recognition method based on double-double precision type provided by any embodiment of the present invention.

[0126] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0127] It should be noted that the terms used in the present invention are only for describing specific embodiments, rather than limiting the scope of the present application. As shown in the present specification, unless the context clearly indicates an exception, the words "one", "a", "a kind of" and / or "the" do not specifically refer to the singular, but may also include the plural. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method or device including the elements.

[0128] It should also be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A target recognition method based on double double precision type, characterized in that: Applies to target processors, including: Obtain the image to be recognized collected by the camera; Determine the block size according to the remaining amount of the cache, and perform batch loading of double-double type data on the image to be identified based on the block size to obtain the data to be processed corresponding to each block; Determining, according to each operation type in the preset target recognition algorithm, initial operation instructions corresponding to each operation type in the target processor; Determining each accelerated processing instruction according to each initial operation instruction and the preset target recognition algorithm; Determine the target recognition result according to each accelerated processing instruction and the to-be-processed data corresponding to each block; The target processor supports double-double type processing.

2. The method according to claim 1, characterized in that The step of determining the block size according to the remaining amount of the cache, and batch loading the double-double type data of the image to be identified based on the block size to obtain the data to be processed corresponding to each block includes: For each level of cache, obtain the single-level remaining amount of the cache, and take the sum of the single-level remaining amounts of caches at all levels as the cache remaining amount; Determine a block size according to the remaining amount of the cache; wherein the block size is less than or equal to the remaining amount of the cache; In response to the remaining data size of the image to be identified being greater than or equal to the block size, based on the block size, loading part of the remaining data of the image to be identified into double-double type data to be processed, and updating the remaining data and the remaining data size until the remaining data size is less than the block size; In response to the remaining data size being smaller than the block size, the remaining data of the image to be recognized is loaded into double-double type data to be processed based on the remaining data size.

3. The method according to claim 1, characterized in that The step of determining, according to each operation type in the preset target recognition algorithm, an initial operation instruction corresponding to each operation type in the target processor comprises: According to the preset target recognition algorithm, determining each operation type in the preset target recognition algorithm; According to each operation type and the candidate operation instructions corresponding to each candidate type stored in the target processor, an initial operation instruction corresponding to each operation type is determined.

4. The method according to claim 3, characterized in that The candidate operation instructions corresponding to each candidate type stored in the target processor include: For each type to be selected, determine the high-order part of the target data according to the high-order part of the first input data, the high-order part of the second input data, and the vectorized instruction corresponding to the type to be selected; wherein the first input data and the second input data are both double-double type data; Using the high-order part of the first input data, the high-order part of the second input data, and the high-order part of the target data as error source data, and determining error compensation data according to the error source data and the selected type; A low-order portion of the target data is determined according to the first input data, the second input data, the error compensation data, and the type to be selected.

5. The method according to claim 4, characterized in that The type to be selected is an addition type, and the error compensation data is determined according to the error source data and the type to be selected, including: Calculate the difference between the high-order part of the target data and the high-order part of the first input data by using a vectorized subtraction instruction to obtain first intermediate data; Determine error compensation data according to the high-order part of the first input data, the high-order part of the second input data and the first intermediate data by using a vectorized subtraction instruction and a vectorized addition instruction; Accordingly, determining the low-order part of the target data according to the first input data, the second input data, the error compensation data, and the selected type includes: The low-order part of the target data is determined by accumulating the low-order part of the first input data, the low-order part of the second input data and the error compensation data through a vectorized addition instruction.

6. The method according to claim 4, characterized in that The selected type is a multiplication type, and the determining of error compensation data according to the error source data includes: Determine second intermediate data by vectorizing a multiplication instruction according to a high-order portion of the first input data and a split constant, and determine third intermediate data by vectorizing a multiplication instruction according to a high-order portion of the second input data and the split constant; Determine error compensation data according to the high-order part of the target data, the second intermediate data and the third intermediate data by using a vectorized subtraction instruction and a vectorized multiplication instruction; Accordingly, determining the low-order portion of the target data according to the first input data, the second input data, and the error compensation data includes: Determine fourth intermediate data according to the high-order part of the first input data and the low-order part of the second input data by using a vectorized multiplication instruction; Determine fifth intermediate data according to the low-order part of the first input data and the high-order part of the second input data by using a vectorized multiplication instruction; Determine sixth intermediate data according to the low-order part of the first input data and the low-order part of the second input data by using a vectorized multiplication instruction; Determine low-order product data by accumulating the fourth intermediate data, the fifth intermediate data, and the sixth intermediate data through a vectorized addition instruction; According to the low-order product data and the error compensation data, the low-order part of the target data is determined by vectorizing the addition instruction.

7. The method according to claim 4, characterized in that The type to be selected is a division type, and the error compensation data is determined according to the error source data and the type to be selected, including: Determine seventh intermediate data according to the high-order part of the target data and the high-order part of the second input data by vectorizing the multiplication instruction; Calculate the difference between the high-order part of the first input data and the seventh intermediate data by using a vectorized subtraction instruction to obtain eighth intermediate data; Calculate the quotient of the eighth intermediate data and the high-order part of the second input data by using a vectorized division instruction to obtain error compensation data; Accordingly, determining the low-order part of the target data according to the first input data, the second input data, the error compensation data, and the selected type includes: The low-order part of the target data is determined according to the low-order part of the first input data, the high-order part of the second input data and the error compensation data through a vectorized division instruction and a vectorized addition instruction.

8. The method according to claim 1, characterized in that: The target processor includes at least two cores, the number of the images to be identified is at least two, the block size is determined according to the remaining amount of the cache, and the double-double type data is batch loaded for the images to be identified based on the block size to obtain the data to be processed corresponding to each block, including: Determine the number of initial tasks according to the number of images to be recognized, and determine the number of tasks to be processed corresponding to each core according to the number of initial tasks and the number of cores of the target processor; For each core, determining a block size of the core according to a remaining amount of a cache of the core; Based on the block size of the core, batch loading of double-double type data is performed on the to-be-recognized images corresponding to the number of tasks to be processed of the core.

9. An electronic device, characterized in that: The electronic device comprises: Processor and memory; The processor is used to execute the steps of the double-double-precision type target recognition method as described in any one of claims 1 to 8 by calling the program or instruction stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program or an instruction, and the program or the instruction enables a computer to execute the steps of the target recognition method based on the double-double precision type as claimed in any one of claims 1 to 8.

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