Test method and device for nonvolatile memory and test equipment

Abstract

The invention relates to the technical field of integrated circuit testing, and discloses a testing method for a nonvolatile memory, which comprises the following steps of: in response to a reading instruction, reading testing data from a plurality of input / output ports of a nonvolatile memory array; inputting the test data to a data verification module to perform verification processing on the test data, and obtaining a verification result in a first form; storing the verification result in the first form to a parallel input and serial output shift register, and outputting a verification result in a second form through a single output port of the parallel input and serial output shift register; and performing data integrity verification on the test data according to the verification result in the second form. According to the method, the verification test of the test data of the multiple input and output ports of the nonvolatile memory array can be realized, and the test efficiency of the nonvolatile memory is improved. The invention further discloses a testing device and testing equipment for the nonvolatile memory.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, for example, to a testing method and device, and testing equipment for non-volatile memory. Background Art

[0002] Currently, in modern electronic devices, non-volatile memory (such as NOR FLASH) is widely used as a medium for storing firmware or other important data. In order to improve production efficiency and reduce costs, manufacturers often need to test these memories to ensure that the performance of the memory meets the standards.

[0003] In order to ensure that the performance of the memory meets the standards, the related technology discloses a testing method for a non-volatile memory. The non-volatile memory is configured with multiple input and output interfaces. The method includes: performing data reading operations on the non-volatile memory through a single input and output interface and obtaining test data; and performing data integrity verification on the test data to determine whether the performance of the non-volatile memory meets the standards.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The related technology can only use a single input / output interface to perform a read and verification operation on the test data of the non-volatile memory, and cannot read the test data of multiple input / output ports, and also cannot test the test data of multiple input / output ports, thus affecting the test efficiency.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a testing method and apparatus for a non-volatile memory, and a testing device to implement a verification test of test data of a non-volatile memory array with multiple input and output ports, and improve the testing efficiency of the non-volatile memory.

[0009] In some embodiments, the method includes: in response to a read instruction, reading test data from multiple input and output ports of a non-volatile memory array; inputting the test data to a data verification module to perform verification processing on the test data and obtain a verification result in a first form; storing the verification result in the first form to a parallel-input serial-output shift register, and outputting the verification result in a second form through a single output port of the parallel-input serial-output shift register; and performing data integrity verification on the test data according to the verification result in the second form.

[0010] In some embodiments, the data verification module includes a cyclic redundancy check module; inputting test data into the data verification module to perform verification processing on the test data, including: obtaining a cyclic redundancy check code; wherein the cyclic redundancy check code is generated by the cyclic redundancy check module according to a preset polynomial; inputting test data into the cyclic redundancy check module to perform cyclic redundancy check processing on the test data through the cyclic redundancy check code.

[0011] In some embodiments, the parallel-input serial-output shift register processes the verification result of the first form in the following manner to obtain the verification result of the second form: under a low-level clock signal, the parallel-input serial-output shift register latches the verification data corresponding to the verification result of the first form; under a high-level clock signal, the parallel-input serial-output shift register shifts the output verification data serially bit by bit through a single output port to obtain the verification result of the second form.

[0012] In some embodiments, the first form of the verification result is parallel verification data, the second form of the verification result is serial verification data, and the second form of the verification result is generated by parallel-to-serial conversion of the first form of the verification result.

[0013] In some embodiments, data integrity verification is performed on test data based on a verification result of the second form, including: reading a verification reference value; determining that the test data has passed the integrity verification if the verification result of the second form matches the verification reference value; or, determining that the test data has not passed the integrity verification, and / or that the test data is damaged if the verification result of the second form does not match the verification reference value.

[0014] In some embodiments, it also includes: after verifying the data integrity of the test data according to the verification result, outputting the verification result.

[0015] In some embodiments, the method further includes: monitoring the status of the non-volatile memory array; and sending an alarm signal when the status is abnormal.

[0016] In some embodiments, the test device includes: a data verification module, electrically connected to the non-volatile memory array, configured to perform data verification on the test data to obtain a verification result in a first form; wherein the test data is obtained by the data verification module reading multiple input and output ports of the non-volatile memory array; a parallel input serial output shift register, electrically connected to the data verification module, configured to output a verification result in a second form through a single output port; and a comparison logic module, electrically connected to the parallel input serial output shift register, configured to perform data integrity verification on the test data according to the verification result in the second form.

[0017] In some embodiments, the testing device includes a processor and a memory storing program instructions, and the processor is configured to execute the above-mentioned testing method for non-volatile memory when running the program instructions.

[0018] In some embodiments, the test equipment includes: a test equipment body; and the above-mentioned test device for non-volatile memory installed in the test equipment body.

[0019] The test method, device, and test equipment for non-volatile memory provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the test phase of the disclosed embodiment, after the test data is read from the multiple input and output ports of the non-volatile memory array, the verification result of the first form after verifying the test data can be processed by a shift register with parallel input and serial output, and then the verification result of the second form can be output, so that the verification of the test data of the multiple input and output ports of the non-volatile memory array can be realized through a single output port of the shift register. Compared with verifying the test data of each input and output port separately, the time for data verification is shortened, thereby improving the test efficiency of the non-volatile memory.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of a testing device for a non-volatile memory provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0028] Figure 6 is an application schematic diagram of an embodiment of the present disclosure;

[0029] Figure 7 is a schematic diagram of another testing device for non-volatile memory provided by an embodiment of the present disclosure.

[0030] Reference numerals:

[0031] 10: data verification module; 20: parallel input serial output shift register;

[0032] 30: comparison logic module; 40: non-volatile memory array;

[0033] 200(300): Test device for non-volatile memory;

[0034] 700: processor; 701: memory;

[0035] 702: communication interface; 703: bus. DETAILED DESCRIPTION

[0036] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0037] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0038] Unless otherwise stated, the term "plurality" means two or more.

[0039] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0040] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0041] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0042] Combination Figure 1 As shown, the embodiment of the present disclosure provides a testing device 200 for a non-volatile memory, including a data verification module 10 , a parallel-input serial-output shift register 20 , and a comparison logic module 30 .

[0043] The data verification module 10 is electrically connected to the non-volatile memory array 40 and is configured to perform data verification on the test data to obtain a verification result of a first form. The test data is obtained by the data verification module reading multiple input and output ports of the non-volatile memory array 40.

[0044] The parallel-input serial-output shift register 20 is electrically connected to the data verification module 10 and is configured to output the verification result in the second form through a single output port.

[0045] The comparison logic module 30 is electrically connected to the parallel-input serial-output shift register 20 and is configured to perform data integrity verification on the test data according to the verification result of the second form.

[0046] By using the test device for non-volatile memory provided by the embodiment of the present disclosure, after the data verification module verifies the test data to obtain the verification result of the first form, the verification result of the second form is output through the single output port configured by the parallel input serial output shift register, and the data integrity of the test data is verified by the comparison logic module based on the verification result of the second form. The embodiment of the present disclosure realizes the efficient data transmission and integrity verification of the test data of the multi-input and output ports of the non-volatile memory array through the cooperation of multiple modules, which not only improves the test efficiency of the non-volatile memory, but also reduces the risk of test failure caused by human error or equipment failure.

[0047] Optionally, combined Figure 1As shown, the test device 200 for non-volatile memory also includes a command module 50. The command module 50 is electrically connected to the data verification module 10, and is configured to indicate data verification requirements and trigger data verification operations on test data. The data verification requirements include data verification types. The data verification types include cyclic redundancy check, parity check, or MD5 (checksum) check. Preferably, the data verification type is cyclic redundancy check.

[0048] Based on the hardware configuration of the above-mentioned test device for non-volatile memory, combined with Figure 2 As shown, the embodiment of the present disclosure provides a testing method for a non-volatile memory, comprising:

[0049] S01, a test device reads test data from a plurality of input and output ports of a non-volatile memory array in response to a read instruction, wherein the read instruction is used to indicate a data verification requirement and trigger a data verification operation of the test data.

[0050] S02, the testing device inputs the test data into the data verification module to perform verification processing on the test data and obtain a verification result in a first form.

[0051] S03, the testing device stores the verification result in the first form into the parallel-input serial-output shift register, and outputs the verification result in the second form through a single output port of the parallel-input serial-output shift register.

[0052] S04, the testing device performs data integrity verification on the test data according to the verification result of the second form.

[0053] According to the test method for non-volatile memory provided by the embodiment of the present disclosure, in the test phase, after reading test data from multiple input and output ports of a non-volatile memory array, a first form of verification result after verifying the test data can be processed by a parallel input and serial output shift register to output a second form of verification result, thereby enabling verification of the test data of multiple input and output ports of the non-volatile memory array through a single output port of the shift register. Compared with verifying the test data of each input and output port individually, the time for data verification is shortened, thereby improving the test efficiency of the non-volatile memory.

[0054] Optionally, combined Figure 3 As shown, the data verification module includes a cyclic redundancy check module. The test device inputs test data to the data verification module to perform verification processing on the test data, including:

[0055] S11, the test device obtains a cyclic redundancy check code, wherein the cyclic redundancy check code is generated by a cyclic redundancy check module according to a preset polynomial.

[0056] S12, the testing device inputs the test data into the cyclic redundancy check module to perform cyclic redundancy check processing on the test data through a cyclic redundancy check code.

[0057] In this way, after obtaining the cyclic redundancy check code, the embodiment of the present disclosure inputs the test data into the cyclic redundancy check module to perform a cyclic redundancy check on the test data through the cyclic redundancy check code to detect whether the test data has changed, which is beneficial to improving the test accuracy of the non-volatile memory.

[0058] Optionally, the parallel-input serial-output shift register processes the verification result of the first form in the following manner to obtain the verification result of the second form:

[0059] Under the low-level clock signal, the parallel-input serial-output shift register latches the verification data corresponding to the verification result of the first form.

[0060] Under a high-level clock signal, the parallel-input serial-output shift register serially shifts and outputs the verification data bit by bit through a single output port to obtain a verification result in a second form.

[0061] In this way, the parallel input serial output shift register latches the verification data corresponding to the verification result of the first form under the low-level clock signal, and then the verification data is serially shifted and outputted bit by bit through the single output port of the shift register under the high-level clock signal, thereby obtaining the verification result of the second form. In this way, the test data of the multiple input and output ports of the non-volatile memory array can be received at the same time, and the verification test of the test data of the multiple input and output ports of the non-volatile memory array can be implemented. Compared with verifying the test data of each input and output port separately, the time of data verification is shortened, thereby improving the test efficiency of the non-volatile memory.

[0062] Optionally, the verification result in the first form is parallel verification data, the verification result in the second form is serial verification data, and the verification result in the second form is generated by parallel-to-serial conversion of the verification result in the first form.

[0063] In this way, the parallel verification data can be converted into serial verification data through parallel-to-serial conversion, thereby realizing the verification test of the test data of the multi-input and output ports of the non-volatile memory array.

[0064] Optionally, the testing device performs data integrity verification on the test data according to the verification result of the second form, including:

[0065] The test device reads the calibration reference value.

[0066] If the verification result of the second form matches the verification reference value, the testing device determines that the test data passes the integrity verification.

[0067] In the event that the verification result of the second form does not match the verification reference value, the testing device determines that the test data has failed integrity verification and / or that the test data is corrupted.

[0068] In this way, after reading the verification reference value, the embodiment of the present disclosure compares the verification result of the second form with the verification reference value. If the two match, it indicates that the test data read by the multiple input and output ports have passed the integrity verification. If the two do not match, it indicates that the test data read by the multiple input and output ports have not passed the integrity verification and / or the test data has been damaged during the data transmission process. Thus, the integrity verification of multiple input and output ports is achieved through a single output port.

[0069] In a specific example, the testing device performs data integrity verification on the test data according to the verification result of the second form, including:

[0070] The test device reads the cyclic redundancy check reference value.

[0071] If the second form of the check result matches the cyclic redundancy check reference value, the test device determines that the test data passes the integrity verification.

[0072] In the event that the check result of the second form does not match the cyclic redundancy check reference value, the testing device determines that the test data has failed integrity verification and / or that the test data is corrupted.

[0073] Based on the hardware configuration of the above-mentioned test device for non-volatile memory, combined with Figure 4 As shown, the embodiment of the present disclosure also provides a testing method for a non-volatile memory, comprising:

[0074] S21, the test device reads test data from a plurality of input and output ports of the non-volatile memory array in response to a read instruction.

[0075] S22, the testing device inputs the test data into the data verification module to perform verification processing on the test data and obtain a verification result in a first form.

[0076] S23, the testing device stores the verification result in the first form into the parallel-input serial-output shift register, and outputs the verification result in the second form through a single output port of the parallel-input serial-output shift register.

[0077] S24, the testing device performs data integrity verification on the test data according to the verification result of the second form.

[0078] S25, the testing device verifies the data integrity of the test data according to the verification result, and outputs the verification result.

[0079] In this step, the test device performs data integrity verification on the test data according to the verification result and outputs the verification result, including: if the test data passes the integrity verification, the test device outputs a first indication signal to indicate that the integrity verification has passed; or, if the test data fails the integrity verification, the test device outputs a second indication signal to indicate that the integrity verification has not passed. The indication signal may be audio, text or image, and the indication signal includes the first indication signal or the second indication signal.

[0080] According to the test method for non-volatile memory provided by the embodiment of the present disclosure, in the test phase, after reading the test data from the multiple input and output ports of the non-volatile memory array, the first form of the verification result after the test data is verified can be processed by a shift register with parallel input and serial output and then output the second form of the verification result, so that the verification of the test data of the multiple input and output ports of the non-volatile memory array can be realized through a single output port of the shift register and the output operation of the verification result can be performed. Compared with verifying the test data of each input and output port separately, the time of data verification is shortened, thereby improving the test efficiency of the non-volatile memory. At the same time, after the data integrity of the test data is verified according to the verification result, the embodiment of the present disclosure outputs the verification result to provide timely feedback to the tester, thereby assisting the tester in determining whether further testing or replacement operation is required for the non-volatile memory.

[0081] Based on the hardware configuration of the above-mentioned test device for non-volatile memory, combined with Figure 5 As shown, the embodiment of the present disclosure also provides a testing method for a non-volatile memory, comprising:

[0082] S31, the test device reads test data from a plurality of input and output ports of the non-volatile memory array in response to a read instruction.

[0083] S32, the testing device inputs the test data into the data verification module to perform verification processing on the test data and obtain a verification result in a first form.

[0084] S33, the testing device stores the verification result in the first form into the parallel-input serial-output shift register, and outputs the verification result in the second form through a single output port of the parallel-input serial-output shift register.

[0085] S34, the testing device performs data integrity verification on the test data according to the verification result of the second form.

[0086] S35, the testing device monitors the status of the non-volatile memory array.

[0087] S36, in case of abnormal status, the test device pushes an alarm signal.

[0088] Using the test method for non-volatile memory provided by the embodiment of the present disclosure, in the test phase, after reading the test data from the multiple input and output ports of the non-volatile memory array, the first form of the verification result after verifying the test data can be processed by a parallel input and serial output shift register and then output a second form of the verification result, thereby simultaneously receiving the test data of the multiple input and output ports of the non-volatile memory array, and verifying the test data of the multiple input and output ports of the non-volatile memory array through a single output port of the shift register, which effectively improves the test efficiency of the non-volatile memory compared to verifying the test data of each input and output port separately. At the same time, the test equipment also monitors the status of the non-volatile memory array during the test phase, and pushes an alarm signal when the status is abnormal to prompt the tester to perform necessary operations in time.

[0089] It should be noted that the test device monitors the state of the non-volatile memory array and pushes an alarm signal when the state is abnormal, which can be executed simultaneously with the test device reading test data from multiple input and output ports of the non-volatile memory array in response to the read instruction, or can be executed after the test device reads test data from multiple input and output ports of the non-volatile memory array in response to the read instruction. This embodiment of the present disclosure is not specifically limited to this.

[0090] In practical applications, such as Figure 6 As shown, the test method for non-volatile memory specifically performs the following steps:

[0091] S41, the test device reads test data from a plurality of input and output ports of the non-volatile memory array in response to a read instruction.

[0092] S42, the testing device obtains a cyclic redundancy check code, wherein the cyclic redundancy check code is generated by a cyclic redundancy check module according to a preset polynomial.

[0093] S43, the testing device inputs the test data into the cyclic redundancy check module to perform cyclic redundancy check processing on the test data through a cyclic redundancy check code, and obtains parallel check data.

[0094] S44, the testing device stores the parallel verification data into the parallel input serial output shift register, and after parallel-to-serial conversion through the parallel input serial output shift register, outputs the serial verification data through a single output port.

[0095] S45, the testing device reads a cyclic redundancy check reference value and executes step S46 or step S47.

[0096] S46, when the check result of the second form matches the cyclic redundancy check reference value, the testing device determines that the test data passes the integrity verification.

[0097] S47, when the check result of the second form does not match the cyclic redundancy check reference value, the testing device determines that the test data has not passed the integrity verification and the test data is damaged.

[0098] Combination Figure 7 As shown, the embodiment of the present disclosure provides a test device 300 for non-volatile memory, including a processor (processor) 700 and a memory (memory) 701. Optionally, the device 300 may also include a communication interface (Communication Interface) 702 and a bus 703. Among them, the processor 700, the communication interface 702, and the memory 701 can communicate with each other through the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call the logic instructions in the memory 701 to execute the test method for non-volatile memory of the above embodiment.

[0099] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0100] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 700 executes the functional application and data processing by running the program instructions / modules stored in the memory 701, that is, the test method for non-volatile memory in the above embodiment is implemented.

[0101] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.

[0102] The embodiments of the present disclosure provide a test device, including: a test device body, and the above-mentioned test device 200 (300) for non-volatile memory. The test device 200 (300) for non-volatile memory is installed in the test device body. The installation relationship described here is not limited to placement inside the test device body, but also includes installation connections with other components of the test device, including but not limited to physical connections, electrical connections or signal transmission connections. It can be understood by those skilled in the art that the test device 200 (300) for non-volatile memory can be adapted to a feasible test device body, thereby realizing other feasible embodiments.

[0103] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned test method for a non-volatile memory.

[0104] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0105] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0106] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0107] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0108] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A testing method for a non-volatile memory, characterized in that: include: In response to a read instruction, reading test data from a plurality of input and output ports of the nonvolatile memory array; Inputting the test data into the data verification module to perform verification processing on the test data and obtain a first form of verification result; storing the verification result of the first form into the parallel-input serial-output shift register, and outputting the verification result of the second form through a single output port of the parallel-input serial-output shift register; The test data is verified for data integrity according to the verification result of the second form.

2. The testing method according to claim 1, characterized in that: The data verification module includes a cyclic redundancy check module; Input the test data to the data verification module to verify the test data, including: Obtaining a cyclic redundancy check code; wherein the cyclic redundancy check code is generated by a cyclic redundancy check module according to a preset polynomial; The test data is input to the cyclic redundancy check module to perform cyclic redundancy check processing on the test data through a cyclic redundancy check code.

3. The testing method according to claim 1, characterized in that: The parallel-input serial-output shift register processes the verification result of the first form in the following manner to obtain the verification result of the second form: Under the low-level clock signal, the parallel-input serial-output shift register latches the verification data corresponding to the verification result of the first form; Under a high-level clock signal, the parallel-input serial-output shift register serially shifts and outputs the verification data bit by bit through a single output port to obtain a verification result in a second form.

4. The testing method according to claim 1, characterized in that: The verification result of the first form is parallel verification data, and the verification result of the second form is serial verification data, and the verification result of the second form is generated by parallel-to-serial conversion of the verification result of the first form.

5. The testing method according to claim 1, characterized in that: The test data is verified for data integrity based on the second form of verification results, including: Read the calibration reference value; In the case where the verification result of the second form matches the verification reference value, determining that the test data passes the integrity verification; or, In the event that the verification result of the second form does not match the verification reference value, it is determined that the test data has failed the integrity verification and / or that the test data is damaged.

6. The testing method according to any one of claims 1 to 5, characterized in that: Also includes: After the test data is verified for data integrity according to the verification result, the verification result is output.

7. The testing method according to any one of claims 1 to 5, characterized in that: Also includes: monitoring the status of the nonvolatile memory array; In case of abnormal status, an alarm signal is pushed.

8. A testing device for a non-volatile memory, characterized in that: include: A data verification module is electrically connected to the non-volatile memory array and is configured to perform data verification on the test data to obtain a verification result of a first form; wherein the test data is obtained by the data verification module reading a plurality of input and output ports of the non-volatile memory array; A parallel-input serial-output shift register, electrically connected to the data verification module, and configured to output a verification result of a second form through a single output port; The comparison logic module is electrically connected to the parallel-input serial-output shift register and is configured to perform data integrity verification on the test data according to the verification result of the second form.

9. A testing device for a non-volatile memory, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the testing method for a non-volatile memory according to any one of claims 1 to 7 when running the program instructions.

10. A test device for a non-volatile memory, characterized in that: include: Test equipment body; The testing device for non-volatile memory as claimed in claim 8 or 9 is installed in the testing equipment body.

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