Method for improving warping of two-layer thin film silicon wafer
By depositing polysilicon and SiO2 films on the back of the silicon wafer and adjusting their thickness to offset stress, the problem of silicon wafer warping is solved, significantly improving the flatness of the silicon wafer and the accuracy of subsequent processes, and is suitable for the manufacturing of small-diameter silicon wafers.
Patent Information
- Application Number
- CN202411522845.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-25
AI Technical Summary
During semiconductor manufacturing, the warping of the two-layer thin-film silicon wafer is severe, affecting the flatness of the silicon wafer and the accuracy of subsequent processes. Existing improvement methods such as high-temperature annealing and multi-tube air intake processes have problems of high cost and complex operation.
By depositing polysilicon film and SiO2 film on the back of the substrate of the silicon wafer and adjusting its thickness, the compressive stress generated by the polysilicon film on the silicon wafer is offset by the tensile stress generated by the SiO2 film, thereby reducing the warpage of the silicon wafer.
It significantly reduces the warpage of the silicon wafer, improves the flatness of the silicon wafer, improves the accuracy and yield of the lithography and doping processes, and has a simple process and low cost, which is suitable for the manufacturing of small-diameter silicon wafers.
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Figure CN119517731A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor processing, and in particular to a method for improving the warpage of a two-layer thin film silicon wafer. Background Art
[0002] In the field of semiconductor manufacturing, the flatness of silicon wafers is crucial to the accuracy of subsequent processes, especially lithography and doping processes. As semiconductor devices develop towards high integration and high performance, the requirements for silicon wafer flatness are getting higher and higher, especially in the manufacturing process of large-size and thin-film silicon wafers, where warping is becoming increasingly significant. Warping not only affects the alignment accuracy of lithography, but also causes non-uniformity in the doping process, which in turn affects device performance.
[0003] In order to solve the self-doping problem of silicon wafers, a layer of silicon dioxide (SiO2) film is usually deposited on the back of the silicon wafer to form a back seal layer. This layer of film is mainly prepared by atmospheric pressure chemical vapor deposition (APCVD) process. However, the deposition of silicon dioxide film will cause the silicon wafer to warp and affect its flatness. To improve this phenomenon, a layer of polysilicon film is usually deposited on the back of the silicon wafer using low pressure chemical vapor deposition (LPCVD) process. These two layers of film have different stress effects on the silicon wafer. The silicon dioxide film applies tensile stress, while the polysilicon film applies compressive stress, which further aggravates the warpage.
[0004] Existing methods for improving warpage mainly include high-temperature annealing and multi-tube gas intake processes. However, high-temperature annealing requires that the silicon wafers have high single crystal quality, otherwise it is easy to cause defects in subsequent processes. The multi-tube gas intake process requires the modification of chemical vapor deposition equipment, which is complicated and costly to operate, especially in the manufacture of small-diameter silicon wafers (such as 4-inch to 6-inch silicon wafers), and its application is relatively limited. However, the market demand for small-diameter silicon wafers still exists, so a more economical and effective technology is needed to improve the warpage problem of silicon wafers after polysilicon and SiO2 film deposition, thereby improving the flatness of silicon wafers and improving the yield and reliability of subsequent processes. Summary of the invention
[0005] One purpose of the present application is to provide a method for improving the warping of a two-layer thin film silicon wafer, at least to solve the technical problem of the warping of a two-layer thin film silicon wafer.
[0006] To achieve the above objectives, some embodiments of the present application provide a method for improving the warping of a two-layer thin film silicon wafer: depositing a layer of polycrystalline silicon film and a layer of SiO2 film on the back side of the substrate of the silicon wafer; adjusting the thickness of the polycrystalline silicon film and the SiO2 film; and offsetting the compressive stress generated by the polycrystalline silicon film on the silicon wafer with the tensile stress generated by the SiO2 film on the silicon wafer.
[0007] Compared with the related art, the solution provided in the embodiment of the present application significantly reduces the warping of the silicon wafer and improves the flatness of the silicon wafer by optimizing the thickness and growth sequence of the polysilicon and SiO2 films, thereby improving the accuracy and yield of the lithography and doping processes in the semiconductor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0009] Figure 1 A schematic flow chart of a method for improving warpage of a two-layer thin film silicon wafer provided according to an embodiment of the present application;
[0010] Figure 2 A schematic diagram of the relationship between a silicon wafer curvature and a polysilicon film thickness provided according to an embodiment of the present application;
[0011] Figure 3 A schematic diagram of the relationship between a silicon wafer bending and a silicon dioxide film thickness provided according to an embodiment of the present application;
[0012] Figure 4 It is a box-line diagram of WARPBF before and after CVD provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0013] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0014] First embodiment
[0015] The present application embodiment relates to a method for improving the warpage of a two-layer thin film silicon wafer. Figure 1 As shown, the method may include the following steps:
[0016] S101, depositing a layer of polysilicon film and a layer of SiO2 film on the back side of the silicon wafer substrate;
[0017] S102, adjusting the thickness of the polysilicon film and the SiO2 film;
[0018] S103, offsetting the compressive stress generated by the polysilicon film on the silicon wafer and the tensile stress generated by the SiO2 film on the silicon wafer.
[0019] The following is a detailed description of each of the above steps.
[0020] For step S101, the polysilicon film is deposited by low pressure chemical vapor deposition (LPCVD) method, and the deposition thickness is set to The SiO2 film is deposited by atmospheric pressure chemical vapor deposition (APCVD) method, and its thickness is adjusted to to
[0021] For step S102, the thickness of the polysilicon film and the SiO2 film is adjusted to optimize the warpage. Experimental analysis shows that the thicker the SiO2 film is, the stronger the tensile stress is, which will cause the silicon wafer to warp convexly; on the contrary, the compressive stress generated by the polysilicon film will cause the silicon wafer to warp concavely. The thickness of the polysilicon film is kept at In this case, adjust the thickness of the SiO2 film to to Within the range of , the stress generated by the two films can be effectively offset, thereby reducing the warping of the silicon wafer.
[0022] In step S103, the compressive stress generated by the polysilicon film on the silicon wafer and the tensile stress generated by the SiO2 film on the silicon wafer are offset. When the thickness of SiO2 film increases to The warpage of the silicon wafer was significantly reduced by 4.7μm.
[0023] It is not difficult to find that, compared with the related art, in the solution provided by the embodiment of the present application, by precisely controlling the thickness of the polysilicon film and the SiO2 film, the compressive stress and tensile stress generated by the two offset each other, thereby effectively reducing the warpage of the silicon wafer and improving the flatness of the silicon wafer. This method not only simplifies the existing warpage control process, but also reduces production costs. It is particularly suitable for the manufacture of 4-inch to 6-inch silicon wafers, fills the technical gap in the existing process for warpage control of small-sized silicon wafers, and significantly improves the accuracy and yield of the lithography and doping processes. It has high practicality and promotion value.
[0024] Second embodiment
[0025] The second embodiment of the present application relates to a method for improving the warpage of a two-layer thin film silicon wafer. The second embodiment is an improvement made on the basis of the first embodiment, and the specific improvements are:
[0026] The back seal of polysilicon or SiO2 is an important process for preparing wafers. After the back seal, the wafer has a difference in film thickness of polysilicon or SiO2, which leads to a difference in stress. The magnitude of the stress leads to a significant increase in warpage. Severe warpage will increase the dissociation of the chip substrate or reduce the yield or even cause failure. Therefore, it is crucial to study the relationship between the film thickness and film growth sequence after the back seal on the warpage of the wafer. Based on the "stress-warpage" theory, the effect of the film thickness and growth sequence of polysilicon and SiO2 on the warpage was experimentally studied, and the effect of the film thickness of polysilicon and SiO2 on the warpage of the silicon wafer was fitted according to the experimental data, so as to design the film thickness of the film to optimize the warpage of the silicon wafer. On the one hand, the effect of the film thickness and growth sequence of polysilicon and SiO2 on the warpage enriches the theoretical data in this regard, and on the other hand, it provides guidance for the future warpage effect.
[0027] Film stress is usually divided into tensile stress and compressive stress. When a force is applied to lengthen the film, the stress it bears is tensile stress. Under the condition of force balance, the substrate is subjected to compressive stress, which causes the substrate and film to bend inward, forming a concave surface. Correspondingly, when a force is applied to shorten the film, the stress the film is subjected to is compressive stress, and the substrate and film will bend downward, forming a convex surface.
[0028] It has been confirmed through experiments that polysilicon thin film will make the final BOW value of silicon wafer become negative, and silicon wafer is subjected to compressive stress. Figure 2 The silicon dioxide film will make the silicon wafer BOW value become positive, and the silicon wafer will be subjected to tensile stress. Figure 3 Therefore, the forces exerted by these two films on the silicon wafer are opposite, so the warpage of the silicon wafer can be changed or optimized by designing the thickness of these two films.
[0029] The control group is the conventional film thickness combination. At this time, the BOW of the silicon wafer after CVD is positive, so the warpage of the silicon wafer is mainly caused by the silicon dioxide film, as shown in Table 1 below:
[0030]
[0031] Table 1 Conventional control group
[0032] Combined with the above conventional group results, in order to balance the deterioration of warpage caused by the thickness of the polysilicon film, the thickness of the silicon dioxide film is increased to reduce or optimize the warpage. The results are shown in Table 2 below:
[0033]
[0034] Table 2 Experimental groups
[0035] like Figure 4As shown in the figure, before and after CVD, different combinations of film thickness have a significant effect on the warpage of the silicon wafer, as described below: Before CVD treatment, the control group A-P9000-LP3000 has a relatively low warpage value of 12.786μm, showing a small warpage and good flatness before deposition. The other groups, such as A-P9000-LP5000 and A-P9000-LP7000, have warpages of 13.0241μm and 13.5169μm, respectively, showing slightly higher warpage values.
[0036] After CVD treatment, the warpage of each group increased, but the increase was different in different combinations: the warpage of the A-P9000-LP3000 group increased significantly, reaching 26.8796μm, indicating that under this combination condition, the warpage deteriorated significantly, indicating that the thickness of the SiO2 film under this combination was not enough to offset the stress generated by the polysilicon film, resulting in a significant increase in the warpage of the silicon wafer. The warpage of the A-P9000-LP5000 group increased moderately, reaching 12.5403μm after CVD, indicating that the warpage control effect of this group is better. This shows that when the thickness of the SiO2 film is At the same time, it can balance the stress to a certain extent and reduce the warping of the silicon wafer.
[0037] The warpage increase of the A-P9000-LP7000 group is the smallest, and the final value is 8.78814μm, indicating that the thickness of the SiO2 film is relatively large. When , the improvement effect of warpage is the best, indicating that increasing the thickness of SiO2 film can effectively offset the compressive stress caused by polysilicon film, thereby reducing the warpage.
[0038] According to the experimental results, it can be seen that by adjusting the thickness of the SiO2 film, especially when the thickness of the SiO2 film is The warpage of silicon wafers after CVD can be effectively reduced and the flatness of silicon wafers can be improved. This method reasonably distributes stress between polysilicon and SiO2 film so that the stress of the two offsets each other, thereby reducing the warpage of silicon wafers. Experimental results show that the warpage control effect of the A-P9000-LP7000 combination is the best and is suitable for semiconductor manufacturing processes that require high flatness.
[0039] In summary, the present application provides a method for improving the warpage of a two-layer thin film silicon wafer by optimizing the thickness of a polysilicon film and a SiO2 film. By rationally adjusting the thickness of the film and its stress relationship, the present invention effectively reduces the warpage of the silicon wafer, significantly improves the flatness of the silicon wafer, and improves the accuracy and reliability of key processes such as lithography and doping. At the same time, the present invention has a simple process and low cost, and is suitable for large-scale production, especially in the manufacture of 4-inch to 6-inch silicon wafers. It has broad application prospects.
[0040] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.
[0041] The flow chart or block diagram in the accompanying drawings shows the possible architecture, function and operation of the equipment, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated system for hardware that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0042] The scope of the present application is defined by the appended claims rather than the foregoing description, and all changes that fall within the meaning and range of equivalents of the claims are therefore intended to be embraced in the present application. Any reference signs in the claims should not be construed as limiting the claims involved. In addition, it is clear that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural.
[0043] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily mention changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims, and the above embodiments should be regarded as exemplary and non-restrictive.
Claims
1. A method for improving the warpage of a two-layer thin film silicon wafer, characterized in that: The method comprises: A layer of polysilicon film and a layer of SiO2 film are deposited on the back of the silicon wafer substrate; Adjusting the thickness of the polysilicon film and the SiO2 film; The compressive stress generated by the polysilicon film on the silicon wafer and the tensile stress generated by the SiO2 film on the silicon wafer are offset.
2. The method according to claim 1, characterized in that The thickness of the polysilicon film is The SiO2 film thickness is to within the range.
3. The method according to claim 2, characterized in that The thickness of the SiO2 film is When the warpage of the silicon wafer is reduced to 0.5μm.
4. The method according to claim 2, characterized in that: The thickness of the SiO2 film is When the warpage of the silicon wafer is reduced by 4.7μm.
5. The method according to claim 1, characterized in that The polysilicon film and the SiO2 film are deposited on the back of the silicon wafer substrate by chemical vapor deposition.
6. The method according to claim 5, characterized in that The chemical vapor deposition method is a combination of low-pressure chemical vapor deposition and normal-pressure chemical vapor deposition.
7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: After the polysilicon film and the SiO2 film are deposited, the silicon wafer is annealed.