Display driving device and forming method thereof

Abstract

The invention provides a display driving device and a forming method thereof, and the forming method comprises the steps: forming a first wafer, forming a low-voltage module on the first wafer, and enabling the low-voltage module to comprise an SRAM (Static Random Access Memory) for removing brightness unevenness and an SRAM for display; a second wafer is formed, a middle-high voltage module is formed on the second wafer, and the middle-high voltage module comprises a gate driver, a source driver and a one-time programmable memory; and bonding the first wafer and the second wafer. The middle-high voltage module and the low-voltage module are separated, formed on two wafers respectively and then bonded together, and the process between the middle-high voltage module and the low-voltage module is decoupled. And the high-voltage module can adopt a process with relatively loose nodes (larger node values), so that the cost is reduced. And the low-voltage module adopts a process with relatively harsh nodes (small node values), so that the line width is reduced, the requirements on the area and speed power consumption of the low-voltage module are met, and high resolution is realized. The cost is obviously reduced, low power consumption is ensured, and the size design is more flexible.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a display driver device and a forming method thereof. Background Art

[0002] The display driver IC (DDIC) is one of the main control components of the panel, also known as the "brain" of the panel. Its main function is to send drive signals and data to the display panel in the form of electrical signals. By controlling the brightness and color of the screen, image information such as letters and pictures can be presented on the screen.

[0003] The market demands a display driver product that combines high performance, low power consumption and low cost. The demand for low power consumption and high computing power of display driver devices mainly comes from the demand for low power consumption and high computing power of the digital part of the low-voltage module. To reduce the cost of display driver devices, the first solution of "including SRAM for demura removal and SRAM for display" is usually modified to the second solution of "retaining SRAM for demura removal and removing SRAM for display" on only one wafer. Since the first solution has SRAM for display, it does not need to be saved all the time, and the power consumption is lower. Since the second solution removes the SRAM for display, it requires static cycle reading, and the power consumption is higher. Although the cost is reduced by removing the SRAM for display by modifying the first solution to the second solution, the power consumption is higher; the market recognition is not high and the promotion progress is slow by sacrificing power consumption to reduce costs. Summary of the invention

[0004] The object of the present invention is to provide a display driver device and a method for forming the same. The present invention separates the medium- and high-voltage modules from the low-voltage modules and forms them on two wafers respectively and then bonds them together, thereby decoupling the processes between the medium- and high-voltage modules and the low-voltage modules. The high-voltage module can adopt a process with relatively loose nodes (larger node values), which reduces costs. The low-voltage module adopts a process with relatively strict nodes (smaller node values) to reduce the line width, meet the requirements for the area, speed and power consumption of the low-voltage module, and achieve high resolution. The present invention significantly reduces costs while ensuring low power consumption and more flexible size design.

[0005] The present invention provides a method for forming a display driver device, comprising:

[0006] S1, forming a first wafer, on which a low-voltage module is formed, the low-voltage module comprising: an SRAM for removing uneven brightness and an SRAM for display;

[0007] S2, forming a second wafer, on which a medium-high voltage module is formed, the medium-high voltage module comprising: a gate driver, a source driver and a one-time programmable memory;

[0008] S3. Bonding the first wafer and the second wafer.

[0009] Furthermore, the first wafer is formed using a 40nm or below node process.

[0010] Furthermore, the first wafer is formed using a 28nm or below node process.

[0011] Furthermore, the second wafer is formed using a 40nm or above node process.

[0012] Further, the first wafer includes a first dielectric layer and a plurality of first metal layers spaced apart in the first dielectric layer;

[0013] The second wafer includes a second substrate, a second dielectric layer, and a plurality of second metal layers spaced apart in the second dielectric layer;

[0014] In the bonding of step S3, hybrid bonding is performed by facing the first dielectric layer to the second dielectric layer and facing the first metal layer to the second metal layer.

[0015] Furthermore, after step S3, the forming method further includes:

[0016] thinning the back side of the second wafer;

[0017] forming an opening from the back side of the second wafer, the opening penetrating the second substrate and a portion of the thickness of the second dielectric layer to expose the interlayer metal layer in the second dielectric layer; filling the opening with an interconnect metal layer, the interconnect metal layer being electrically connected to the interlayer metal layer;

[0018] forming a first passivation layer, wherein the first passivation layer covers the back side of the second wafer;

[0019] forming a redistribution metal layer, wherein the redistribution metal layer is located on the surface of the first passivation layer and fills the first opening in the first passivation layer and is electrically connected to the interconnection metal layer;

[0020] forming a second passivation layer, wherein the second passivation layer covers the redistribution metal layer and the first passivation layer, and a second opening in the second passivation layer exposes the redistribution metal layer;

[0021] A pad or a conductive bump is formed in the second opening.

[0022] The present invention also provides a display driver device, comprising:

[0023] a first wafer and a second wafer bonded together;

[0024] A low-voltage module is formed on the first wafer, and the low-voltage module includes: an SRAM for removing uneven brightness and an SRAM for display;

[0025] A medium-high voltage module is formed on the second wafer, and the medium-high voltage module includes: a gate driver, a source driver and a one-time programmable memory.

[0026] Furthermore, the low-voltage module also includes: a mobile industry processor interface, an analog design module and a first isolation ring; the first isolation ring is arranged around the circumference edge of the low-voltage module.

[0027] Furthermore, the medium and high voltage module also includes: a grayscale transformation correction module and a second isolation ring; the second isolation ring is arranged around the circumference edge of the medium and high voltage module.

[0028] Furthermore, the medium and high voltage module includes: a medium voltage module and a high voltage module; the working voltage range of the low voltage module is: 0.9V~1.5V; the working voltage range of the medium voltage module is: 6V~8V; the working voltage range of the high voltage module is: 28V~32V.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides a display driver device and a forming method thereof, the forming method comprising: S1, forming a first wafer, a low-voltage module is formed on the first wafer, the low-voltage module comprises: an SRAM for removing uneven brightness and an SRAM for display; S2, forming a second wafer, a medium-high voltage module is formed on the second wafer, the medium-high voltage module comprises: a gate driver, a source driver and a one-time programmable memory;

[0031] S3. Bond the first wafer and the second wafer. The present invention separates the medium- and high-voltage modules from the low-voltage modules and forms them on two wafers respectively and then bonds them together, thereby decoupling the processes between the medium- and high-voltage modules and the low-voltage modules. The high-voltage module can adopt a process with relatively loose nodes (larger node values), which reduces costs. The low-voltage module adopts a process with relatively strict nodes (smaller node values) to reduce the line width, meet the requirements for the area, speed and power consumption of the low-voltage module, and achieve high resolution. The present invention significantly reduces costs while ensuring low power consumption and more flexible size design. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a flow chart of a method for forming a display driver device according to an embodiment of the present invention.

[0033] Figure 2A schematic diagram of a display driver device according to an embodiment of the present invention.

[0034] The reference numerals are as follows:

[0035] 10-first wafer; 12-first dielectric layer; 13-first metal layer; 20-second wafer; 21-second substrate; 22-second dielectric layer; 23-second metal layer; 24-interlayer metal layer; 25-interconnect metal layer; 26-first passivation layer; 27-redistribution metal layer; 28-second passivation layer; 29-conductive bumps. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0038] An embodiment of the present invention provides a method for forming a display driver device, such as Figure 1 As shown, including:

[0039] S1, forming a first wafer, on which a low-voltage module is formed, the low-voltage module comprising: an SRAM for removing uneven brightness and an SRAM for display;

[0040] S2, forming a second wafer, on which a medium-high voltage module is formed, the medium-high voltage module including: a gate driver, a source driver and a one-time programmable memory;

[0041] S3, bonding the first wafer and the second wafer.

[0042] The following is combined with Figure 2 Each step of the method for forming a display driver device according to an embodiment of the present invention is described in detail.

[0043] Step S1, forming a first wafer 10, on which a low-voltage module is formed, the low-voltage module comprising: SRAM for demura and SRAM for display, SRAM is a static random access memory, and the SRAM for display is a frame buffer.

[0044] Demura is a compensation technology for images. The demura function of the display panel is an important function related to the display of LCD TVs. After the display panel is manufactured, due to process reasons, its brightness uniformity is often not guaranteed, and Mura (uneven brightness) phenomenon is prone to occur. The specific state of uneven brightness shown by each display panel is also different. In order to overcome this problem and ensure that the brightness uniformity of each display panel is good, when manufacturing display panels, the LCD screen factory will perform demura (uneven brightness removal) debugging for each display panel separately, and debug the demura compensation data. The demura compensation data can be stored in the SRAM for uneven brightness removal (demura) of the first wafer 10.

[0045] The low voltage module may also include: a mobile industry processor interface (MIPI), an analog design module and a first isolation ring; the first isolation ring is arranged around the periphery of the low voltage module to isolate and protect the low voltage module. The first wafer 10 includes a first dielectric layer 12 and a plurality of first metal layers 13 spaced apart in the first dielectric layer. In one example, the first wafer 10 may be formed using a 40nm or less node process. In another example, the first wafer 10 may be formed using a 28nm or less node process.

[0046] Step S2, forming a second wafer 20, on which a medium-high voltage module is formed, the medium-high voltage module including: a gate driver (GIP), a source driver and a one-time programmable memory (OTP). The medium-high voltage module also includes: a grayscale transformation correction module (Gamma) and a second isolation ring. Gamma correction is a grayscale transformation, which is a transfer function introduced to overcome the nonlinear relationship of the human visual system to the brightness perception. The second isolation ring is arranged around the periphery of the medium-high voltage module to isolate and protect the medium-high voltage module. The second wafer 20 includes a second substrate 21, a second dielectric layer 22 and a plurality of second metal layers 23 spaced apart in the second dielectric layer 22; the second wafer 20 can be formed using a 40nm or above node process.

[0047] The present invention separates the medium and high voltage modules from the low voltage modules on two wafers. The process of the medium and high voltage modules is no longer restricted, and there is no need to use processes with nodes below 40nm (node ​​value, i.e., gate width is 40nm). The medium and high voltage modules can use mature processes above 40nm, and the product yield is high. The low voltage modules (including the low voltage digital part) can use the mature 28nm and more advanced process technology to obtain more advantageous power consumption.

[0048] The medium and high voltage modules include: medium voltage module and high voltage module; the working voltage range of the low voltage module is: 0.9V~1.5V; the working voltage range of the medium voltage module is: 6V~8V; the working voltage range of the high voltage module is: 28V~32V.

[0049] Step S3, bonding the first wafer 10 and the second wafer 20. Specifically, the first dielectric layer 12 faces the second dielectric layer 22, and the first metal layer 13 is mixedly bonded to the second metal layer 23.

[0050] After step S3, the forming method further includes:

[0051] The back side of the second wafer 20 is thinned; the back side of the second wafer is the surface of the second wafer 20 away from the first wafer 10 .

[0052] An opening is formed from the back of the second wafer, the opening penetrates the second substrate 21 and the second dielectric layer 22 of a part of the thickness to expose the interlayer metal layer 24 located in the second dielectric layer 22; the interconnection metal layer 25 is filled in the opening, and the interconnection metal layer 25 is electrically connected to the interlayer metal layer 24. A first passivation layer 26 is formed, and the first passivation layer 26 covers the back of the second wafer. A redistribution metal layer 27 is formed, and the redistribution metal layer 27 is located on the surface of the first passivation layer 26 and fills the first opening in the first passivation layer 26 and is electrically connected to the interconnection metal layer 25. A second passivation layer 28 is formed, and the second passivation layer 28 covers the redistribution metal layer 27 and the first passivation layer 26, and the second opening in the second passivation layer 28 exposes the redistribution metal layer 27. A pad or conductive bump 29 is formed in the second opening.

[0053] The bonded first wafer 10 and second wafer 20 are diced as needed to obtain display driver chips (DDIC).

[0054] The embodiment of the present invention further provides a display driver device, such as Figure 2 As shown, including:

[0055] A first wafer 10 and a second wafer 20 bonded together;

[0056] A low voltage module is formed on the first wafer 10, and the low voltage module includes: an SRAM for removing uneven brightness and an SRAM for display;

[0057] A medium-high voltage module is formed on the second wafer 20 , and the medium-high voltage module includes: a gate driver, a source driver and a one-time programmable memory.

[0058] The low voltage module also includes: a mobile industry processor interface, an analog design module and a first isolation ring; the first isolation ring is arranged around the peripheral edge of the low voltage module to achieve shielding isolation of the low voltage module.

[0059] The medium and high voltage module also includes: a grayscale transformation correction module (Gamma) and a second isolation ring; the second isolation ring is arranged around the periphery edge of the medium and high voltage module to achieve shielding isolation of the medium and high voltage module.

[0060] The medium and high voltage modules include: medium voltage module and high voltage module. The working voltage range of the low voltage module is 0.9V~1.5V; the working voltage range of the medium voltage module is 6V~8V; the working voltage range of the high voltage module is 28V~32V.

[0061] As the resolution increases, the design requirements for medium and high voltage modules remain the same, but the intellectual property cores for low voltage modules increase, and the demand for area, speed and power consumption requires the line width of low voltage modules to become smaller and smaller.

[0062] The present invention separates the medium-high voltage module and the low-voltage module and forms them on two wafers respectively and then bonds them together, thereby decoupling the processes between the medium-high voltage module and the low-voltage module. The high-voltage module can adopt a process with relatively loose nodes (larger node values), which reduces costs. The low-voltage module adopts a process with relatively strict nodes (smaller node values) to reduce the line width, meet the requirements for the area and speed power consumption of the low-voltage module, and achieve high resolution. The more stringent process nodes of the low-voltage module enable the display driver to integrate high-computing power intellectual property cores such as motion estimation, motion compensation and super-resolution, which can help mobile phone system manufacturers achieve more difficult requirements. The cost of the present invention is reduced by 30% to 40%; the low-voltage module includes: SRAM for brightness unevenness and SRAM for display. Since there is SRAM for display, it does not need to be saved all the time, and the power consumption is low. The present invention still maintains low power consumption and can integrate more high-computing power intellectual property cores.

[0063] The existing solution of making medium-high voltage modules and low-voltage modules on the same wafer requires the wells of high- and low-voltage devices to be isolated (usually using a deep N-well layer) and there are isolation size requirements between different deep N-well areas, which affects the chip size, especially in the SRAM area. The solution of separating the medium-high voltage module and the low-voltage module on two wafers and stacking and bonding them is not limited by this, and the size design is more flexible.

[0064] In summary, the present invention provides a display driver device and a method for forming the same, the method comprising: S1, forming a first wafer, a low-voltage module is formed on the first wafer, the low-voltage module comprises: SRAM for removing uneven brightness and SRAM for display; S2, forming a second wafer, a medium-high voltage module is formed on the second wafer, the medium-high voltage module comprises: a gate driver, a source driver and a one-time programmable memory; S3, bonding the first wafer and the second wafer. The present invention separates the medium-high voltage module and the low-voltage module and forms them on two wafers respectively and then bonds them together, decoupling the process between the medium-high voltage module and the low-voltage module. The high-voltage module can adopt a process with relatively loose nodes (larger node values) to reduce costs. The low-voltage module adopts a process with relatively strict nodes (smaller node values) to reduce the line width, meet the requirements for the area and speed power consumption of the low-voltage module, and achieve high resolution. The present invention significantly reduces costs while ensuring low power consumption and more flexible size design.

[0065] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the module disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0066] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a display driver device, characterized in that: include: S1, forming a first wafer, on which a low-voltage module is formed, the low-voltage module comprising: an SRAM for removing uneven brightness and an SRAM for display; S2, forming a second wafer, on which a medium-high voltage module is formed, the medium-high voltage module comprising: a gate driver, a source driver and a one-time programmable memory; S3. Bonding the first wafer and the second wafer.

2. The method for forming a display driver device according to claim 1, wherein: The first wafer is formed using a 40nm or below node process.

3. The method for forming a display driver device according to claim 2, wherein: The first wafer is formed using a 28nm or lower node process.

4. The method for forming a display driver device according to claim 1, wherein: The second wafer is formed using a 40nm or above node process.

5. The method for forming a display driver device according to claim 1, wherein: The first wafer includes a first dielectric layer and a plurality of first metal layers spaced apart in the first dielectric layer; The second wafer includes a second substrate, a second dielectric layer, and a plurality of second metal layers spaced apart in the second dielectric layer; In the bonding of step S3, hybrid bonding is performed by facing the first dielectric layer to the second dielectric layer and facing the first metal layer to the second metal layer.

6. The method for forming a display driver device according to claim 5, wherein: After step S3, the forming method further comprises: thinning the back side of the second wafer; forming an opening from the back side of the second wafer, the opening penetrating the second substrate and a portion of the thickness of the second dielectric layer to expose the interlayer metal layer in the second dielectric layer; filling the opening with an interconnect metal layer, the interconnect metal layer being electrically connected to the interlayer metal layer; forming a first passivation layer, wherein the first passivation layer covers the back side of the second wafer; forming a redistribution metal layer, wherein the redistribution metal layer is located on the surface of the first passivation layer and fills the first opening in the first passivation layer and is electrically connected to the interconnection metal layer; forming a second passivation layer, wherein the second passivation layer covers the redistribution metal layer and the first passivation layer, and a second opening in the second passivation layer exposes the redistribution metal layer; A pad or a conductive bump is formed in the second opening.

7. A display driver device, characterized in that: include: a first wafer and a second wafer bonded together; A low-voltage module is formed on the first wafer, and the low-voltage module includes: an SRAM for removing uneven brightness and an SRAM for display; A medium-high voltage module is formed on the second wafer, and the medium-high voltage module includes: a gate driver, a source driver and a one-time programmable memory.

8. The display driver device according to claim 7, wherein: The low-voltage module further comprises: a mobile industry processor interface, an analog design module and a first isolation ring; the first isolation ring is arranged around the peripheral edge of the low-voltage module.

9. The display driver device according to claim 7, wherein: The medium and high voltage module further includes: a grayscale transformation correction module and a second isolation ring; the second isolation ring is arranged around the circumference edge of the medium and high voltage module.

10. The display driver device according to claim 7, wherein: The medium and high voltage modules include: a medium voltage module and a high voltage module; the working voltage range of the low voltage module is: 0.9V~1.5V; the working voltage range of the medium voltage module is: 6V~8V; the working voltage range of the high voltage module is: 28V~32V.

Images