Semiconductor crystal grain structure with air gap and preparation method thereof

Abstract

The invention provides a semiconductor crystal grain structure. The semiconductor crystal grain structure comprises a substrate, a first supporting framework, a second supporting framework, a first conductor block, a second conductor block and a third conductor block, the first supporting framework and the second supporting framework are arranged on the base. The first conductor block is disposed on the first support frame, and the second conductor block is disposed on the second support frame. The third conductor block is disposed between the first conductor block and the second conductor block. The third conductor block is suspended on the substrate.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023114950333, filed on November 10, 2023, with the invention name of "Semiconductor grain structure with air gap and preparation method thereof". Application No. 2404732TW01 claims priority and benefits of U.S. formal application No. 18 / 237,015 filed on August 23, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor grain structure and a method for preparing the semiconductor grain structure, and more particularly to a semiconductor grain structure having an air gap for reducing capacitive coupling between a plurality of conductive features and a method for preparing the semiconductor grain structure. Background Art

[0003] Semiconductor dies are widely used in the electronics industry. Semiconductor dies may have relatively small sizes, multifunctional characteristics, and / or relatively low manufacturing costs. Semiconductor dies may be classified as any of semiconductor memory dies that store logic data, semiconductor logic dies that process logic data, and hybrid semiconductor dies that have both the functions of semiconductor memory dies and semiconductor logic dies.

[0004] A relatively high speed and relatively low voltage semiconductor die may satisfy the desired characteristics of an electronic die including the semiconductor die (eg, high speed and / or low power consumption). The semiconductor die may be relatively highly integrated. The reliability of the semiconductor die may be reduced due to the relatively high integration density of the semiconductor die.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] An embodiment of the present disclosure provides a semiconductor grain structure, comprising a substrate, a first supporting frame, a second supporting frame, a first conductor block, a second conductor block and a third conductor block. The first supporting frame and the second supporting frame are arranged on the substrate. The first conductor block is arranged on the first supporting frame, and the second conductor block is arranged on the second supporting frame. The third conductor block is arranged between the first conductor block and the second conductor block. The third conductor block is suspended on the substrate.

[0007] Another embodiment of the present disclosure provides a method for preparing a semiconductor grain structure, including forming a first supporting skeleton on the substrate; forming a first conductor block on the first supporting skeleton; after forming the first conductor block, forming a second supporting skeleton on the substrate; forming a second conductor block on the second supporting skeleton; forming a plurality of third conductor blocks suspended above the substrate; sequentially forming an energy removable layer and a cover dielectric layer above the substrate, wherein the first conductor block, the second conductor block and the third conductor block are separated from each other by the energy removable layer; and performing a heat treatment process to transform the energy removable layer into an air gap structure including an air gap and a liner layer surrounding the air gap.

[0008] Embodiments of semiconductor grain structures are provided in the present disclosure. The semiconductor grain structures include a plurality of air gaps, and a plurality of conductor blocks are separated from each other by the air gaps. Therefore, parasitic capacitance between a plurality of conductive contact points can be reduced. As a result, overall component performance (i.e., power consumption and resistance-capacitance (RC) delay) can be improved, and the yield of semiconductor components can be improved.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1 1 is a flow chart illustrating a method for preparing a semiconductor structure having a plurality of air gaps according to an embodiment of the present disclosure, wherein the air gaps are used to reduce capacitive coupling between conductive features such as wires and conductive lines.

[0012] Figure 2 2 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a semiconductor grain structure according to an embodiment of the present disclosure.

[0013] Figure 3 is a schematic cross-sectional view illustrating an intermediate stage of forming a carbon hard mask in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0014] Figure 4 is a schematic cross-sectional view illustrating an intermediate stage of forming a gap opening in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0015] Figure 5 is a schematic cross-sectional view illustrating an intermediate stage of forming a support skeleton in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0016] Figure 6 is a schematic cross-sectional view illustrating an intermediate stage of forming a conductor block in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0017] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage of a planarization process performed in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0018] Figure 8 is a schematic cross-sectional view illustrating an intermediate stage of performing a recess process in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0019] Fig. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a metal silicide layer in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0020] Fig.10 is a schematic cross-sectional view illustrating an intermediate stage of forming a first hard mask in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0021] Fig.11 is a schematic cross-sectional view illustrating an intermediate stage of an etching process performed in forming a semiconductor grain structure in some embodiments of the present disclosure.

[0022] Fig.12 is a schematic cross-sectional view illustrating an intermediate stage of an etching process performed in forming a semiconductor grain structure in some embodiments of the present disclosure.

[0023] Fig.13 is a schematic cross-sectional view illustrating an intermediate stage of a deposition process in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0024] Fig.14 is a schematic cross-sectional view illustrating an intermediate stage of forming a second supporting skeleton in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0025] Fig.15 is a schematic cross-sectional view illustrating an intermediate stage of forming a conductor block in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0026] Fig.16is a schematic cross-sectional view illustrating an intermediate stage of forming a second hard mask in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0027] Fig.17 is a schematic cross-sectional view illustrating an intermediate stage of removing a gap sub-layer in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0028] Fig.18 2 is a schematic cross-sectional view illustrating an intermediate stage of forming an energy removable layer and a capping dielectric layer in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0029] Fig.19 2 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of air gaps and a plurality of liner layers in forming a semiconductor grain structure according to some embodiments of the present disclosure.

[0030] Fig. 20 is a circuit schematic illustrating an exemplary integrated circuit including an array of memory cells, such as a memory element, according to some embodiments of the present disclosure.

[0031] Fig.21 is a schematic cross-sectional view illustrating a semiconductor grain structure according to another embodiment of the present disclosure.

[0032] Fig. 22 2 is a schematic cross-sectional view illustrating a semiconductor grain structure according to different embodiments of the present disclosure.

[0033] The reference numerals are described as follows:

[0034] 10: Preparation method

[0035] 30: Memory unit

[0036] 31: Field Effect Transistor

[0037] 33: Capacitor

[0038] 35: Drain

[0039] 37: Source

[0040] 39: Gate

[0041] 100: Semiconductor grain structure

[0042] 101: Base

[0043] 103: Silicon-containing wire

[0044] 105: Gap sublayer

[0045] 105A: Gap opening

[0046] 107: Hard Mask

[0047] 109: Carbon Hard Mask

[0048] 109A: Mask opening

[0049] 111: First support frame

[0050] 113: Conductor block

[0051] 113A: Conductor block

[0052] 113B: Conductor block

[0053] 113C: Conductor block

[0054] 113D: Metal silicide layer

[0055] 115: First hard mask

[0056] 117: Carbon Hard Mask

[0057] 117A: Mask opening

[0058] 119: Second support frame

[0059] 120: Conductor block

[0060] 120D: Metal silicide layer

[0061] 121: Second hard mask

[0062] 123: Energy Removable Layer

[0063] 125: Cover dielectric layer

[0064] 127: Air Gap

[0065] 129: Padding layer

[0066] 130: Air gap structure

[0067] 200: Semiconductor grain structure

[0068] 213: Conductor block

[0069] 213a: Conductive layer

[0070] 213b: Barrier layer

[0071] 220: Conductor block

[0072] 220a: Conductive layer

[0073] 220b: Barrier layer

[0074] 300: Semiconductor grain structure

[0075] 313: Conductor block

[0076] 313a: First contact point

[0077] 313b: Second contact point

[0078] 313c: Third contact point

[0079] 313d: Fourth contact point

[0080] 313e: Interstitial

[0081] 320: Conductor block

[0082] 320a: First contact point

[0083] 320b: Second contact point

[0084] 320c: Third contact point

[0085] 320d: Fourth contact point

[0086] 320e: Interstitial

[0087] 100D: Memory Components

[0088] BL: Bit Line

[0089] S11: Steps

[0090] S13: Steps

[0091] S15: Steps

[0092] S17: Steps

[0093] S19: Steps

[0094] S21: Steps

[0095] S23: Steps

[0096] T1: Thickness

[0097] T2: Thickness

[0098] T3: Thickness

[0099] T4: Thickness

[0100] WL: character line

[0101] Z: Direction DETAILED DESCRIPTION

[0102] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0103] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0104] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0105] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0106] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0107] In the present disclosure, a semiconductor die generally refers to a die that can operate by utilizing semiconductor characteristics, and an electro-optic die, a light-emitting display die, a semiconductor circuit, and an electronic die are all included in the category of semiconductor die.

[0108] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0109] Figure 11 is a flow chart illustrating a method 10 for preparing a semiconductor structure having a plurality of air gaps according to an embodiment of the present disclosure, wherein the air gaps are used to reduce capacitive coupling between conductive features such as wires and conductors. The preparation method 10 can be performed as a plurality of steps. It should be understood that the preparation method 10 can be performed in any order and can include the same, more, or fewer steps. It should be understood that the preparation method 10 can be performed by one or more pieces of semiconductor manufacturing equipment or manufacturing tools. In some embodiments, the preparation method 10 includes steps S11, S13, S15, S17, S19, S21, and S23. The following is a flowchart of the method 10 in conjunction with the drawings. Figure 1 Steps S11 to S23 are described in detail.

[0110] In some embodiments, please refer to Figures 2 to 5 ,exist Figure 1 In step S11 of the manufacturing method 10 shown, a plurality of manufacturing processes are performed to form a first supporting frame 111 on a substrate 101 .

[0111] In some embodiments, the substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 101 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP.

[0112] In some embodiments, the substrate 101 includes an epitaxial layer. For example, the substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0113] In some embodiments, the substrate 101 can be a variety of materials, including sapphire, silicon, gallium nitride, germanium or silicon carbide, but not limited thereto. The substrate 101 can be silicon on insulator (SOI). In some embodiments of the present disclosure, the substrate 101 is silicon. The crystal orientation of the substantially single crystal substrate 101 can be any one of (100), (111) or (110) on the Miller index. Other crystal orientations are also possible. The crystal orientation of the substrate 101 can be cut off. In some embodiments of the present disclosure, the substrate 101 is (100) silicon having a crystalline substrate surface region with cubic crystallinity. In another embodiment, for a (100) silicon substrate 101, the semiconductor surface can be miscut or offset, for example, 2-10 degrees toward (110). In another embodiment, the substrate 101 is (111) silicon having a crystalline substrate surface region with hexagonal crystallinity.

[0114] Figure 2 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a semiconductor grain structure 100 in an embodiment of the present disclosure. In some embodiments, a plurality of silicon-containing wires 103, such as polysilicon wires, may be disposed or grown above a substrate 101. The silicon-containing wires 103 may include a pattern twice the final pitch (e.g., the pitch is the width of a metal wire plus the spacing between two metal wires) and may be covered with a hard mask 107. The hard mask 107 may include SiN. The silicon-containing wires 103 may be patterned on SiN, SiC, or aluminum oxide. A gap sublayer 105 (e.g., silicon oxide) may be fabricated on the silicon-containing wires 103. It should be understood that a buffer layer (not shown) may be disposed between the silicon-containing wires 103 and the substrate 101. An appropriate buffer layer may be provided according to the material type of the substrate 101.

[0115] Figure 3 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a carbon hard mask 109 in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, the carbon hard mask 109 is formed on the gap sub-layer 105 by a deposition process, and then a mask opening 109A is formed in the carbon hard mask 109 by lithography patterning.

[0116] Figure 4 1 is a cross-sectional view illustrating an intermediate stage of forming a gap sub-opening 105A in a semiconductor grain structure 100 according to some embodiments of the present disclosure. In some embodiments, an etching process is performed to transfer the mask opening 109A into the gap sub-opening 105A of the gap sub-layer 105 .

[0117] Figure 51 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a first support skeleton 111 in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, the first support skeleton 111 can be manufactured by using a spin coating technique. The material of the first support skeleton 111 can be a spin-coated metal oxide (tungsten oxide, hafnium oxide, or zirconium oxide) deposited only to a critical height. The first support skeleton 111 can be a spin-coated dielectric having Si-C-Si (e.g., not Si-O-Si) in the skeleton and being properly cured to withstand hydrofluoric (HF) acid. In another embodiment, a non-conformal SiN, SiC, or SiCN can be used (e.g., instead of a spin coating), which can leave a thin etch stop layer on the oxide spacer and can help protect the metal barrier layer from HF stripping during subsequent air gap formation.

[0118] Figure 6 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a conductor block 113 in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, the carbon hard mask 109 is removed (e.g., the carbon hard mask 109 is ashed) and the conductor block 113 fills multiple regions between the gap sub-layers 105. The conductor block 113 can be a recessable material, such as cobalt (Co), copper (Cu), ruthenium (Ru), or amorphous silicon (a-Si) (e.g., a-Si that is later silicidized to form CoSi or NiSi).

[0119] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage of a planarization process performed in forming a semiconductor grain structure in some embodiments of the present disclosure. Figure 1 In step S13 of the manufacturing method 10 shown, a first conductor block is formed on the first supporting skeleton. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process 1 is performed to remove a portion of the conductor block 113, so that the gap sub-layer 105 is exposed. In some embodiments, after the planarization process, a plurality of conductor blocks 113A are embedded in the gap sub-layer 105, wherein each top of the plurality of conductor blocks 113A is substantially the same as the top of the gap sub-layer 105. In other words, each top of the plurality of conductor blocks 113A is coplanar with the top of the gap sub-layer 105.

[0120] Figure 8 1 is a cross-sectional schematic diagram illustrating an intermediate stage of performing a recess process in forming the semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, a portion of the plurality of conductor blocks 113A is removed by a recess process such as an etch-back process to form a plurality of conductor blocks 113B embedded in the gap sub-layer 105, wherein each top of the plurality of conductor blocks 113B is lower than the top of the gap sub-layer 105.

[0121] Fig. 9 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a metal silicide layer 113D in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, when the conductor block 113C is a-Si, a metal can be deposited on the conductor block 113C and annealed to form a metal silicide layer 113D above the conductor block 113C. In some embodiments, metal nickel (Ni) can be deposited and annealed to form nickel silicide (NiSi), or metal cobalt (Co) can be deposited and annealed to form cobalt silicide (CoSi).

[0122] Fig.10 1 is a cross-sectional view illustrating an intermediate stage of forming a first hard mask 115 in forming a semiconductor die 100 in some embodiments of the present disclosure. In some embodiments, a deposition process is performed to form the first hard mask 115 on the metal silicide layer 113D, and then a planarization process is performed on the first hard mask 115. In some embodiments, the first hard mask 115 may include SiC, SiOC, ZrO 2 , HfO 2 Or W oxide. In some embodiments, the first hard mask 115 can be one or more of a dielectric, a carbide, or a metal carbide. After forming the first hard mask 115, the conductor block 113C covered with the first hard mask 115 and the metal silicide layer 113D can be referred to as a metal line or a wire.

[0123] Fig.11 1 is a cross-sectional view illustrating an intermediate stage of performing an etching process in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. In some embodiments, the hard mask 107 is removed to expose the silicon-containing line 103 by an etching process such as a dry etching process, so as to selectively remove the hard mask 107 while retaining the silicon-containing line 103 on the substrate 101.

[0124] Fig.12 1 is a cross-sectional view illustrating an intermediate stage of an etching process in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. In some embodiments, the silicon-containing line 103 is etched away to expose multiple portions of the substrate 101 while retaining the spacer sublayer 105 on the substrate 101.

[0125] Fig.13 1 is a cross-sectional view illustrating an intermediate stage of performing a deposition process in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. In some embodiments, a deposition process is performed to deposit a material of the spacer sublayer 105 on at least a plurality of exposed portions of the substrate 101 and the first hard mask 115 .

[0126] Fig.141 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a second support skeleton in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. Figure 1 In step S15 of the manufacturing method 10 shown in FIG. 1 , a second support frame 119 is formed on the substrate 101. In some embodiments, similar to Figure 3-5 In the manufacturing process described in the above, a carbon hard mask 117 is formed on the spacer sub-layer 105 by a deposition process, and then a mask opening 117A is formed in the carbon hard mask 117 by lithography patterning. In some embodiments, an etching process is performed to transfer the mask opening 117A to a spacer sub-opening of the spacer sub-layer 105 to expose a portion of the substrate 101. Subsequently, a support frame 119 is formed on the exposed portion of the substrate 101.

[0127] Fig.15 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a conductor block 120 in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. Figure 1 In step S17 of the manufacturing method 10 shown in FIG. 1 , a second conductor block 120 is formed on the second support frame 119. In some embodiments, similar to Figures 6 to 9 The carbon hard mask 117 is removed (e.g., the carbon hard mask 117 is ashed) and the conductor blocks 120 fill the multiple regions between the gap sub-layers 105. The conductor blocks 120 can be a recessable material, such as cobalt (Co), copper (Cu), ruthenium (Ru), or amorphous silicon (a-Si) (e.g., a-Si that is later silicidized to form CoSi or NiSi).

[0128] In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductor block 120, so as to expose the gap sub-layer 105. In some embodiments, after the planarization process, the conductor block 120 is embedded in the gap sub-layer 105, wherein the top of the conductor block 120 is substantially the same as the top of the gap sub-layer 105. In some embodiments, a recessing process such as an etch-back process is then performed to remove a portion of the conductor block 120, wherein the top of the conductor block 120 is substantially the same as the top of the gap sub-layer 105.

[0129] In some embodiments, when the conductor block 120 is a-Si, a metal may be deposited and annealed to form a metal silicide layer 120D over the conductor block 120. In some embodiments, metal nickel (Ni) may be deposited and annealed to form nickel silicide (NiSi), or metal cobalt (Co) may be deposited and annealed to form cobalt silicide (CoSi).

[0130] Fig.161 is a cross-sectional view illustrating an intermediate stage of forming a second hard mask 121 in forming a semiconductor grain structure 100 in some embodiments of the present disclosure. In some embodiments, a deposition process is performed to form the second hard mask 121 on the metal silicide layer 120D, and then a planarization process is performed on the second hard mask 121. In some embodiments, the second hard mask 121 may include SiC, SiOC, ZrO 2 , HfO 2 Or W oxide. In some embodiments, the second hard mask 121 can be one or more of a dielectric, a carbide, or a metal carbide. After forming the second hard mask 121, the conductor block 120 and the metal silicide layer 120D covered with the second hard mask 121 can be referred to as a metal line or a wire.

[0131] Fig.17 1 is a cross-sectional schematic diagram illustrating an intermediate stage of removing the gap sub-layer 105 in forming the semiconductor grain structure 100 according to some embodiments of the present disclosure. Figure 1 In step S19 of the manufacturing method 10 shown, a plurality of suspended conductor blocks are formed above the substrate, and the plurality of suspended conductor blocks are connected to the first conductor block and the second conductor block. In some embodiments, the gap sublayer 105 is removed to expose the substrate 101. In some embodiments, hydrofluoric acid (HF) cleaning can be performed to remove the gap sublayer 105 without etching the first support skeleton 111 and the second support skeleton 119. The first group of conductor blocks 113C and conductor blocks 120 (e.g., metal wires, wires) are disposed on the first support skeleton 111 and the second support skeleton 119, while the second group of conductor blocks 113C and conductor blocks 120 (e.g., metal wires, wires) are suspended above the substrate 101 between the first support skeleton 111 and the second support skeleton 119.

[0132] Fig.18 is a cross-sectional schematic diagram illustrating an intermediate stage of forming an energy removable layer 123 and a cap dielectric layer 125 in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. Figure 1 In step S21 of the manufacturing method 10 shown, an energy removable layer and a capping dielectric layer are sequentially formed on the substrate. In some embodiments, according to some embodiments, the energy removable layer 123 and the capping dielectric layer 125 are sequentially formed on the substrate 101 .

[0133] In some embodiments, a material of the energy removable layer 123 includes a thermally decomposable material. In some other embodiments, the material of the energy removable layer 123 includes a photodecomposable material, an electron beam decomposable material, or other applicable energy decomposable materials. Specifically, in some embodiments, the material of the energy removable layer 123 includes a substrate and a decomposable pore-forming material that is substantially removed upon exposure to an energy source (e.g., heat).

[0134] In some embodiments, the substrate includes hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO 2 ), and the decomposable pore-forming material includes a pore-forming organic compound, which can provide porosity for the space originally occupied by the energy removable layer 123 in subsequent processes.

[0135] In addition, the cap dielectric layer 125 includes silicon oxide, silicon nitride, silicon oxynitride or a multilayer thereof. In some embodiments, the cap dielectric layer 125 includes a low-k dielectric material. In addition, the manufacturing technology of the energy removable layer 123 and the cap dielectric layer 125 may include a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable processes.

[0136] Fig.19 1 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of air gaps 127 and a plurality of liner layers 129 in forming a semiconductor grain structure 100 according to some embodiments of the present disclosure. Figure 1 In step S23 of the preparation method 10 shown, a heat treatment process is performed to transform the energy removable layer into a plurality of air gaps surrounded by a plurality of liner layers. In some embodiments, a heat treatment process is performed to transform the energy removable layer 123 into an air gap structure 130, and the air gap structure 130 includes an air gap 127 and a liner layer 129 surrounding the air gap 127. In some embodiments, the heat treatment process is used to remove the decomposable porogen material of the energy removable layer 123 to generate a plurality of pores, and the substrate of the energy removable layer 123 is accumulated at a plurality of edges of the energy removable layer 123 to form the liner layer 129. After the decomposable porogen material is removed, the pores are filled with air, so that the air gaps 127 are obtained inside the remaining portion of the energy removable layer 123. In some embodiments, the air gaps 127 may be a vacuum (e.g., the gas in the plurality of air gaps is evacuated). In some embodiments, the air gaps 127 may include an inert gas (e.g., nitrogen, helium, argon, air, etc.).

[0137] In some other embodiments, the heat treatment process can be replaced by a phototreatment process, an electron beam treatment process, a combination thereof, or other suitable energy treatment processes. For example, ultraviolet (UV) light or laser can be used to remove the decomposable pore-forming material of the energy-removable layer 123, and then the air gap 127 can be obtained.

[0138] Fig. 20 is a circuit schematic diagram illustrating an exemplary integrated circuit including an array of memory cells 30, such as a memory device 100D, in some embodiments of the present disclosure. In some embodiments, the memory device 100D includes a dynamic random access memory (DRAM) device. In some embodiments, the memory device 100D includes a plurality of memory cells 30, and the plurality of memory cells 30 are arranged in a grid pattern and include a plurality of rows and a plurality of columns. The number of memory cells 30 may vary depending on system requirements and manufacturing technology.

[0139] In some embodiments, each memory cell 30 includes an access element and a storage element. The access element is configured to provide controlled access to the storage element. Specifically, according to some embodiments, the access element is a field effect transistor (FET) 31 and the storage element is a capacitor 33. In each memory cell 30, the field effect transistor 31 includes a drain 35, a source 37, and a gate 39. One terminal of the capacitor 33 is electrically connected to the source 37 of the field effect transistor 31, and the other terminal of the capacitor 33 can be electrically connected to ground. In addition, in each memory cell 30, the gate 39 of the field effect transistor 31 is electrically connected to a word line WL, and the drain 35 of the field effect transistor 31 is electrically connected to a bit line BL.

[0140] The above description mentions that the terminal of the field effect transistor 31 electrically connected to the capacitor 33 is the source 37, and the terminal of the field effect transistor 31 electrically connected to the bit line BL is the drain 35. However, during read and write operations, the terminal of the field effect transistor 31 electrically connected to the capacitor 33 may be the drain, and the terminal of the field effect transistor 31 electrically connected to the bit line BL may be the source. That is, either terminal of the field effect transistor 31 may be the source or the drain, depending on how the voltages applied to the source, the drain, and the gate control the field effect transistor 31.

[0141] By controlling the voltage at the gate 39 via the word line WL, a potential can be generated across the field effect transistor 31 so that charge can flow from the drain 35 to the capacitor 33. Therefore, the charge stored in the capacitor 33 can be interpreted as binary data in the memory cell 30. For example, a positive charge stored in the capacitor 33 above a threshold voltage can be interpreted as a binary "1". If the charge in the capacitor 33 is below the threshold value, the binary value "0" is stored in the memory cell 30.

[0142] The bit line BL is configured to read data from the memory cell 30 and write data to the memory cell 30. The word line WL is configured to activate the field effect transistor (FET) 31 to access a particular row of the memory cells 30. Therefore, the memory device 100D also includes a peripheral area, which may include an address buffer, a column decoder, and a row decoder. The column decoder and the row decoder selectively access the memory cells 30 in response to a plurality of address signals provided to the address buffer during read, write, and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or other type of memory controller.

[0143] Please refer to Fig.19 and Fig. 20 , the air gap 127 is formed in the region of the memory cell 30 of the memory element 100D (ie, the pattern-dense region), while no air gap is formed in the surrounding region of the memory element 100D (ie, the pattern-sparse region such as the row decoder and the column decoder).

[0144] The present disclosure provides some embodiments of a semiconductor grain structure 100. The semiconductor grain structure 100 includes a plurality of air gaps 127, and the conductor block 113C and the conductor block 120 are separated from each other by the air gaps 127. Therefore, the parasitic capacitance between the plurality of conductive contact points can be reduced. As a result, the overall device performance can be improved (i.e., power consumption and resistance-capacitance (RC) delay can be reduced), and the yield of the semiconductor device can be improved.

[0145] The semiconductor grain structure 100 is provided for the purpose of illustration. However, the present disclosure is not limited thereto. In other embodiments, the conductor blocks 113 and the conductor blocks 120 of the semiconductor grain structure 100 may be replaced by other structures.

[0146] Please refer to Fig.21 and Fig. 22 . Fig.21 is a schematic cross-sectional view illustrating a semiconductor grain structure 200 according to another embodiment of the present disclosure. Fig. 22 FIG. 3 is a cross-sectional schematic diagram illustrating a semiconductor grain structure 300 according to different embodiments of the present disclosure.

[0147] like Fig.21As shown, the semiconductor grain structure 200 is similar to the semiconductor grain structure 100, and includes a substrate 101, a plurality of conductor blocks 213, a plurality of metal silicide layers 113D, a plurality of conductor blocks 220, a plurality of metal silicide layers 120D, a plurality of first hard masks 115, a plurality of second hard masks 121, a first supporting skeleton 111, a second supporting skeleton 119, an energy removable layer 123 and a cover dielectric layer 125.

[0148] In some embodiments, the substrate 101, the metal silicide layer 113D, the metal silicide layer 120D, the first hard mask 115, the second hard mask 121, the first support frame 111, the second support frame 119, the energy removable layer 123, and the cap dielectric layer 125 of the semiconductor grain structure 200 are the same as those of the semiconductor grain structure 100. In addition, the manufacturing process of the above elements in the semiconductor grain structure 200 is the same as the manufacturing process of these elements in the semiconductor grain structure 100. Therefore, the details of these elements will not be repeated here.

[0149] like Fig.21 As shown, one of the conductor blocks 213 is disposed above the first supporting skeleton 111 , and one of the conductor blocks 220 is disposed above the second supporting skeleton 119 .

[0150] Each conductor block 213 is disposed in the energy removable layer 123 and protrudes from the upper surface of the energy removable layer 123. An upper surface of each conductor block 213 is covered by the corresponding metal silicide layer 113D. Each sidewall of an upper portion of each conductor block 213 is surrounded by the cap dielectric layer 125.

[0151] Each conductor block 213 includes a conductive layer 213a and a barrier layer 213b. The barrier layer 213b has a U-shape and contacts the energy removable layer 123, the cap dielectric layer 125, and the corresponding metal silicide layer 113D. The conductive layer 213a is disposed in the U-shaped barrier layer 213b. In some embodiments, the conductive layer 213a has a rectangular cross-section.

[0152] The barrier layer 213b has a bottom and two side portions, and the bottom connects one of the side portions to the other side portion. In some embodiments, a thickness T1 of the bottom is greater than a thickness T2 of each side portion.

[0153] In some embodiments, the barrier layer 213 b includes titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer 213 a includes tungsten (W).

[0154] Each conductor block 220 is disposed in the energy removable layer 123 and protrudes from the upper surface of the energy removable layer 123. An upper surface of each conductor block 220 is covered by the corresponding metal silicide layer 120D. Each sidewall of a top of each conductor block 220 is surrounded by the cap dielectric layer 125.

[0155] Each conductor block 220 includes a conductive layer 220a and a barrier layer 220b. The barrier layer 220b has a U-shape and contacts the energy removable layer 123, the cap dielectric layer 125, and the corresponding metal silicide layer 120D. The conductive layer 220a is disposed in the U-shaped barrier layer 220b. In some embodiments, the conductive layer 220a has a rectangular cross-section.

[0156] The barrier layer 220b has a bottom and two side portions, and the bottom connects one of the side portions to the other side portion. In some embodiments, a thickness T3 of the bottom is greater than a thickness T4 of each side portion.

[0157] In some embodiments, the barrier layer 220 b includes titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer 220 a includes tungsten (W).

[0158] In some embodiments, conductor block 213 is identical to conductor block 220. In such embodiments, thickness T1 is equal to thickness T3, and thickness T2 is equal to thickness T4.

[0159] In some embodiments, the conductor block 213 and the conductor block 220 are gapless conductor blocks, that is, there are no air gaps or vacuum gaps in the conductor block 213 and the conductor block 220 .

[0160] For the formation of the conductor block 213, please refer to Figures 5 to 7 In some embodiments, after removing the carbon hard mask 109, a barrier material is formed to fill the plurality of regions between the gap sub-layers 105 and cover the top of the gap sub-layers 105. The barrier material includes Ti, TiN or a combination thereof. It should be understood that the profile of the barrier material is the same as Figure 6 The conductor block 113 is shown. Next, a planarization process is performed to remove the barrier material above the gap sub-layer 105 and expose the gap sub-layer 105. In some embodiments, the planarization process is a CMP process. The barrier material remaining after the planarization process has the same Figure 7 The conductor block 113A is shown with the same profile.

[0161] Please refer to Figure 8 A portion of the barrier material between the spacer sub-layers 105 is removed by a recess process such as an etch-back process to form a plurality of barrier materials embedded in the spacer sub-layers 105. A top of the barrier material after the recess process is lower than a top of the spacer sub-layer 105.

[0162] Before forming the metal silicide layer 113D, the barrier material is etched to form a barrier layer 213b. In some embodiments, a lithography process is performed on the barrier material. The side of the barrier layer 213b is shielded during the lithography process, while other portions are not shielded so as to be etched. After forming the barrier layer 213b, the conductive layer 213a is formed in the barrier layer 213b. After forming the conductive layer 213a, a plurality of conductor blocks 213 are formed.

[0163] In alternative embodiments, the barrier layer 213b may include other methods. In such embodiments, no barrier material is formed. Instead, after removing the carbon hard mask 109, the barrier layer 213b may include an anisotropic deposition process between the spacer sublayers 105. Due to the anisotropic deposition process, the thickness T1 of the bottom of the barrier layer 213b may be greater than the thickness T2 of the side of the barrier layer 213b.

[0164] For the formation of the conductor block 220, please refer to Fig.14 . In some embodiments, the carbon hard mask 117 is removed, and a barrier material is formed to fill multiple areas between the gap sub-layers 105 and cover the top of the gap sub-layer 105. The barrier material includes Ti, TiN or a combination thereof. Next, a planarization process can be performed to remove the barrier material above the gap sub-layer 105 and expose the gap sub-layer 105. In some embodiments, the planarization process is a CMP process. A portion of the barrier material between the gap sub-layers 105 is removed by a recess process such as an etch-back process to form multiple barrier materials embedded in the gap sub-layer 105. A top of the barrier material after the recess process is lower than a top of the gap sub-layer 105.

[0165] Before forming the metal silicide layer 120D, the barrier material is etched to form the barrier layer 220b. In some embodiments, a lithography process is performed on the barrier material. The sides of the barrier layer 220b are shielded during the lithography process, while other portions are not shielded to be etched. After forming the barrier layer 220b, the conductive layer 220a is formed in the barrier layer 220b. After forming the conductive layer 220a, the conductor block 220 is formed.

[0166] In alternative embodiments, the barrier layer 220b may include other methods. In such embodiments, no barrier material is formed. Instead, after removing the carbon hard mask 117, the barrier layer 220b may include an anisotropic deposition process between the gap sub-layers 105. Due to the anisotropic deposition process, the thickness T3 of the bottom of the barrier layer 220b may be greater than the thickness T4 of the side of the barrier layer 220b.

[0167] Then, Fig.21The energy removable layer 123 of the semiconductor grain structure 200 is transformed into Fig.19 The air gap 127 and the liner layer 129 are shown. In some embodiments, a heat treatment process is performed to transform the energy removable layer 123 into an air gap structure 130, and the air gap structure 130 includes the air gap 127 and the liner layer 129 surrounding the air gap 127. In some embodiments, the heat treatment process is used to remove the decomposable porogenous material of the energy removable layer 123 to generate pores, and the matrix of the energy removable layer 123 is accumulated at the edge of the energy removable layer 123 to form the liner layer 129. After the decomposable porogenous material is removed, the pores are filled with air, so that the air gap 127 is obtained inside the remaining part of the energy removable layer 123. In some embodiments, the air gap 127 can be a vacuum (e.g., the gas in the air gap is evacuated). In some embodiments, the air gap 127 can include an inert gas (e.g., nitrogen, helium, argon, air, etc.).

[0168] In some other embodiments, the heat treatment process can be replaced by a phototreatment process, an electron beam treatment process, a combination thereof, or other suitable energy treatment processes. For example, an ultraviolet light or laser can be used to remove the decomposable pore-forming material of the energy removable layer 123 and obtain the air gap 127.

[0169] In some embodiments, the semiconductor grain structure 200 is, for example, Fig. 20 The memory element 100D shown is a portion of a DRAM.

[0170] Please refer to Fig. 22 The semiconductor grain structure 300 is similar to the semiconductor grain structure 100 and includes a substrate 101, a plurality of conductor blocks 313, a plurality of metal silicide layers 113D, a plurality of conductor blocks 320, a plurality of metal silicide layers 120D, a plurality of first hard masks 115, a plurality of second hard masks 121, a first support frame 111, a second support frame 119, an energy removable layer 123, and a cap dielectric layer 125.

[0171] In some embodiments, the substrate 101, the metal silicide layer 113D, the metal silicide layer 120D, the first hard mask 115, the second hard mask 121, the first support frame 111, the second support frame 119, the energy removable layer 123, and the cap dielectric layer 125 of the semiconductor grain structure 300 are the same as those of the semiconductor grain structure 100. In addition, the manufacturing process of the above elements in the semiconductor grain structure 300 is the same as the manufacturing process of these elements in the semiconductor grain structure 100. Therefore, the details of these elements will not be repeated here.

[0172] like Fig. 22As shown, one of the conductor blocks 313 is disposed above the first supporting skeleton 111 , and one of the conductor blocks 320 is disposed above the second supporting skeleton 119 .

[0173] Each conductor block 313 is disposed in the energy removable layer 123 and protrudes from the upper surface of the energy removable layer 123. An upper surface of each conductor block 313 is covered by the corresponding metal silicide layer 113D. Each sidewall of a top of each conductor block 313 is surrounded by the cap dielectric layer 125.

[0174] Each conductor block 313 includes a first contact point 313a, a second contact point 313b, a third contact point 313c, a fourth contact point 313d and two spacers 313e. The first contact point 313a, the second contact point 313b, the third contact point 313c and the fourth contact point 313d are stacked in sequence and sandwiched between the spacers 313e. The first contact point 313a, the second contact point 313b, the third contact point 313c and the fourth contact point 313d have substantially the same width, so each spacer 313e has a straight side surface that contacts the first contact point 313a, the second contact point 313b, the third contact point 313c and the fourth contact point 313d.

[0175] One of the conductor blocks 313 is disposed above the first supporting frame 111 and contacts the first supporting frame 111. The first contact points 313a of the remaining conductor blocks 313 contact the energy removable layer 123.

[0176] exist Fig. 22 In the embodiment, an upper surface of the third contact point 313 c is lower than the top of the energy removable layer 123 . In other words, a lower surface of the fourth contact point 313 d is lower than the energy removable layer 123 .

[0177] In some embodiments, the first contact point 313a includes a conductive material, such as doped polysilicon, metal, metal nitride or metal silicide. In some embodiments, the second contact point 313b includes doped polysilicon. In some embodiments, the third contact point 313c includes a conductive material, such as tungsten, aluminum, copper, nickel or cobalt. In some embodiments, the fourth contact point 313d includes a conductive material, such as tungsten, aluminum, copper, nickel or cobalt. In some embodiments, the third contact point 313c and the fourth contact point 313d may include the same material. In some embodiments, the spacer 313e includes silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide.

[0178] Each conductor block 320 is disposed in the energy removable layer 123 and protrudes from the upper surface of the energy removable layer 123. An upper surface of each conductor block 320 is covered by the corresponding metal silicide layer 120D. Each sidewall of a top of each conductor block 320 is surrounded by the cap dielectric layer 125.

[0179] Each conductor block 320 includes a first contact point 320a, a second contact point 320b, a third contact point 320c, a fourth contact point 320d, and two spacers 320e. The first contact point 320a, the second contact point 320b, the third contact point 320c, and the fourth contact point 320d are stacked in sequence and sandwiched between the spacers 320e. The first contact point 320a, the second contact point 320b, the third contact point 320c, and the fourth contact point 320d have substantially the same width, so each spacer 320e has a straight side surface that contacts the first contact point 320a, the second contact point 320b, the third contact point 320c, and the fourth contact point 320d.

[0180] One of the conductor blocks 320 is disposed above the second supporting frame 119 and contacts the second supporting frame 119. The first contact points 320a of the remaining conductor blocks 320 contact the energy removable layer 123.

[0181] exist Fig. 22 In the embodiment, an upper surface of the third contact point 320c is lower than the top of the energy removable layer 123. In other words, a lower surface of the fourth contact point 320d is lower than the energy removable layer 123.

[0182] In some embodiments, the first contact 320a includes a conductive material, such as doped polysilicon, metal, metal nitride or metal silicide. In some embodiments, the second contact 320b includes doped polysilicon. In some embodiments, the third contact 320c includes a conductive material, such as tungsten, aluminum, copper, nickel or cobalt. In some embodiments, the fourth contact 320d includes a conductive material, such as tungsten, aluminum, copper, nickel or cobalt. In some embodiments, the third contact 320c and the fourth contact 320d may include the same material. In some embodiments, the spacer 320e includes silicon oxide, silicon nitride, silicon oxynitride or silicon oxynitride.

[0183] In some embodiments, conductor block 313 is identical to conductor block 320 .

[0184] For the formation of the conductor block 313, please refer to Figure 5In some embodiments, after removing the carbon hard mask 109, the first contact 313a is deposited into the plurality of regions between the gap sub-layers 105. Next, the second contact 313b is deposited over the first contact 313a, the third contact 313c is deposited over the second contact 313b, and the fourth contact 313d is disposed over the third contact 313c. It should be understood that the materials of the first contact 313a, the second contact 313b, the third contact 313c, and the fourth contact 313d may be deposited on the upper surface of the gap sub-layer 105 and removed after forming the fourth contact 313d by a planarization process such as a CMP process.

[0185] After forming the fourth contact 313d, an etching process is performed to remove the side portions of the contacts 313a, 313b, 313c, 313d, wherein the side portions are in contact with the spacer sublayer 105. During the etching process, the side portions are masked. A photolithography process may be used to mask the side portions.

[0186] The spacer 313 e is formed in the area originally occupied by the respective side portions of the contact points 313 a - 313 d , and the conductor block 313 is formed.

[0187] For the formation of the conductor block 320, please refer to Fig.14 In some embodiments, after removing the carbon hard mask 117, the first contact 320a is deposited into the area between the gap sub-layers 105. Next, the second contact 320b is deposited over the first contact 320a, the third contact 320c is deposited over the second contact 320b, and the fourth contact 320d is disposed over the third contact 320c. It should be understood that the materials of the first contact 313a, the second contact 313b, the third contact 313c, and the fourth contact 313d may be deposited on the upper surface of the gap sub-layer 105 and removed after forming the fourth contact 313d by a planarization process such as a CMP process.

[0188] After forming the fourth contact 320d, an etching process is performed to remove the side portions of the contacts 320a-320d, wherein the side portions are in contact with the spacer sublayer 105. During the etching process, the side portions are masked. A photolithography process may be used to mask the side portions.

[0189] The spacer 320 e is formed in the area originally occupied by the sides of the contact points 320 a - 320 d , and the conductor block 320 is formed.

[0190] Then Fig. 22 The semiconductor grain structure 300 shown has an energy removable layer 123 transferred to the Fig.19The air gap 127 and the liner layer 129 are shown. In some embodiments, a heat treatment process is performed to transform the energy removable layer 123 into an air gap structure 130, and the air gap structure 130 includes an air gap 127 and a liner layer 129 surrounding the air gap 127. In some embodiments, the heat treatment process is used to remove the decomposable porogen material of the energy removable layer 123 to generate pores, and the matrix of the energy removable layer 123 is accumulated at the edge of the energy removable layer 123 to form the liner layer 129. After the decomposable porogen material is removed, the pore is filled with air, so that the air gap 127 is obtained inside the remaining part of the energy removable layer 123. In some embodiments, the air gap 127 can be a vacuum (e.g., the gas in the air gap is evacuated). In some embodiments, the air gap 127 can include an inert gas (e.g., nitrogen, helium, argon, air, etc.).

[0191] In some other embodiments, the heat treatment process can be replaced by a phototreatment process, an electron beam treatment process, a combination thereof, or other suitable energy treatment processes. For example, ultraviolet light or laser can be used to remove the decomposable pore-forming material of the energy removable layer 123, and then the air gap 127 can be obtained.

[0192] In some embodiments, the semiconductor grain structure 300 is, for example, Fig. 20 The memory element 100D shown is a portion of a DRAM.

[0193] An embodiment of the present disclosure provides a semiconductor grain structure, comprising a substrate, a first supporting frame, a second supporting frame, a first conductor block, a second conductor block and a third conductor block. The first supporting frame and the second supporting frame are arranged on the substrate. The first conductor block is arranged on the first supporting frame, and the second conductor block is arranged on the second supporting frame. The third conductor block is arranged between the first conductor block and the second conductor block. The third conductor block is suspended on the substrate.

[0194] Another embodiment of the present disclosure provides a method for preparing a semiconductor grain structure, including forming a first supporting skeleton on the substrate; forming a first conductor block on the first supporting skeleton; after forming the first conductor block, forming a second supporting skeleton on the substrate; forming a second conductor block on the second supporting skeleton; forming a plurality of third conductor blocks suspended above the substrate; sequentially forming an energy removable layer and a cover dielectric layer above the substrate, wherein the first conductor block, the second conductor block and the third conductor block are separated from each other by the energy removable layer; and performing a heat treatment process to transform the energy removable layer into an air gap structure including an air gap and a liner layer surrounding the air gap.

[0195] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0196] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor grain structure, comprising: a base; A first supporting frame is disposed on the base; a second supporting frame, disposed on the base; A first conductor block is arranged on the first supporting frame; A second conductor block is arranged on the second supporting frame; A plurality of third conductor blocks are disposed between the first conductor block and the second conductor block, wherein the plurality of third conductor blocks are suspended on the substrate.

2. The semiconductor grain structure according to claim 1, further comprising: an air gap structure, disposed on the substrate and between the first conductor block and the second conductor block, The plurality of third conductor blocks are suspended on the air gap structure.

3. The semiconductor grain structure as claimed in claim 2, wherein the air gap structure comprises: One air gap; as well as A liner layer surrounds the air gap.

4. The semiconductor grain structure as claimed in claim 2, wherein the first conductive block comprises: a first contact point; a second contact point disposed on the first contact point; a third contact point, disposed on the second contact point; a fourth contact point disposed on the third contact point; A plurality of spacers, wherein the first contact point, the second contact point, the third contact point and the fourth contact point are sandwiched between the plurality of spacers. 5 . The semiconductor grain structure as claimed in claim 4 , wherein the first contact point and the plurality of spacers contact the first supporting framework.

6. The semiconductor grain structure according to claim 4, further comprising: a first metal silicide disposed on the first conductive block, wherein the first metal silicide contacts the fourth contact point and the plurality of spacers; as well as A first hard mask is disposed on the first metal silicide.

7. The semiconductor grain structure according to claim 6, further comprising: A capping dielectric layer is disposed above the first hard mask, wherein the capping dielectric layer contacts the first hard mask, the first metal silicide, the spacers and the air gap structure.

8. The semiconductor grain structure according to claim 4, wherein The first contact point includes doped polysilicon, metal, metal nitride or metal silicide, The second contact includes doped polysilicon, The third contact includes tungsten, aluminum, copper, nickel or cobalt, and The fourth contact includes tungsten, aluminum, copper, nickel or cobalt. 9 . The semiconductor grain structure as claimed in claim 4 , wherein the spacers comprise silicon oxide, silicon nitride, silicon oxynitride or silicon oxynitride. 10 . The semiconductor grain structure as claimed in claim 4 , wherein a top surface of the third contact point is lower than a top surface of the air gap structure. 11 . The semiconductor grain structure as claimed in claim 4 , wherein the first conductive block, the second conductive block and the plurality of spacers are separated from each other by the air gap structure.

12. A method for preparing a semiconductor grain structure, comprising: forming a first supporting frame on a substrate; forming a first conductor block on the first supporting frame; After forming the first conductor block, forming a second supporting framework on the substrate; forming a second conductor block on the second supporting frame; forming a plurality of third conductor blocks suspended above the substrate; forming an energy removable layer and a cover dielectric layer in sequence over the substrate, wherein the first conductor block, the second conductor block and the plurality of third conductor blocks are separated from each other by the energy removable layer; as well as A thermal treatment process is performed to transform the energy removable layer into an air gap structure including an air gap and a liner layer surrounding the air gap.

13. The preparation method according to claim 12, wherein forming the first support skeleton comprises: performing an anisotropic deposition to form a barrier layer of the first conductor block, wherein the barrier layer has a U-shape; as well as A conductive layer is formed in the barrier layer. 14 . The manufacturing method as claimed in claim 13 , wherein the barrier layer comprises a bottom and two side portions, wherein the bottom connects one of the side portions to the other side portion. 15 . The preparation method as claimed in claim 14 , wherein a first thickness of the bottom portion is greater than a second thickness of the side portion.

16. The manufacturing method according to claim 12, wherein forming the first conductive block comprises: sequentially forming a first contact point, a second contact point, a third contact point and a fourth contact point; removing a plurality of side portions of the first contact point, the second contact point, the third contact point, and the fourth contact point; as well as A plurality of spacers are formed in the regions originally occupied by the plurality of side portions. 17 . The preparation method as claimed in claim 16 , wherein the plurality of spacers and the first contact point contact the first support frame. 18 . The manufacturing method according to claim 16 , wherein a top surface of the third contact point is lower than a top surface of the air gap structure.

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