Packaging structure, preparation method thereof and display device

Abstract

The invention provides a packaging structure, a preparation method thereof and a display device. The packaging structure comprises a substrate which comprises a first surface, a second surface, a groove and a plurality of through holes; the opening of the groove is positioned on the first surface; the groove comprises a plurality of communicated cavities, the cavities comprise a first cavity and a second cavity, the first cavity is located on the side, close to the second surface, of the second cavity, and the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface; the plurality of through holes comprise a first through hole and a second through hole, the first through hole penetrates to the surface, close to the groove, of the substrate corresponding to the first cavity, and the second through hole penetrates to the surface, close to the groove, of the substrate corresponding to the second cavity; a first conductive structure filling the through hole; the chips comprise a first chip and a second chip, and the first chip is located in the first cavity and electrically connected with the first conductive structure in the first through hole; the second chip is located in the second cavity and electrically connected with the first conductive structure in the second through hole.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging structure and a preparation method thereof and a display device. Background Art

[0002] The recent trend in the semiconductor industry is to make cheap semiconductor products compact, thin, light, fast, multifunctional and efficient, so as to have high reliability. At present, in order to cater to the above trend, chips are stacked in a packaging structure. In the packaging structure in which the chips are stacked, multiple chips need to be electrically connected to each other. At present, the chips are mainly electrically connected to each other using through electrodes that penetrate the chips. However, the above packaging structure is not easy to implement, has low yield and high cost. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a packaging structure and a preparation method thereof and a display device, which solve the problems in the prior art that the packaging structure is difficult to implement, has a low yield or a high cost.

[0004] In a first aspect, the present application provides a packaging structure, which includes: A substrate, comprising a first surface, a second surface arranged opposite to the first surface, a groove and a plurality of through holes; the opening of the groove is located on the first surface; the groove comprises a plurality of connected cavities, the plurality of cavities comprising a first cavity and a second cavity, the first cavity is located on a side of the second cavity close to the second surface, the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface; the plurality of through holes comprises a first through hole and a second through hole, the first through hole penetrates to a surface of the substrate corresponding to the first cavity close to the groove, and the second through hole penetrates to a surface of the substrate corresponding to the second cavity close to the groove; a first conductive structure filling the through hole; The chips include a first chip and a second chip. The first chip is located in a first cavity and electrically connected to a first conductive structure in a first through hole. The second chip is located in a second cavity and electrically connected to the first conductive structure in a second through hole.

[0005] In one embodiment, the groove further includes a third cavity, a fourth cavity, ... an Nth cavity, the i+1th cavity is located on the side of the ith cavity close to the second surface, the orthographic projection of the i+1th cavity on the second surface covers the orthographic projection of the ith cavity on the second surface, N is an integer greater than or equal to 3, and i is an integer between 1 and N in sequence; Preferably, the chip further comprises a third chip, a fourth chip, ... an Nth chip, and the i-th chip is located in the i-th cavity; Preferably, the orthographic projection of the (i+1)th chip on the second surface covers the orthographic projection of the i-th chip on the second surface; Preferably, the plane where the chip is located is parallel to the second surface; Preferably, the N chips are spaced apart in a direction perpendicular to the second surface; Preferably, the through hole further includes a third through hole, a fourth through hole, ... an Nth through hole, the ith through hole is connected to the ith cavity, and the first conductive structure located in the ith through hole is electrically connected to the ith chip.

[0006] In one embodiment, along a direction perpendicular to the second surface, the centroid of the i-th cavity and the centroid of the substrate are located on the same straight line; Preferably, along a direction perpendicular to the second surface, a surface of the substrate close to the groove has a stepped structure; Preferably, the through hole extends in a direction perpendicular to the second surface; Preferably, the through hole penetrates the second surface; Preferably, the substrate comprises glass.

[0007] In one embodiment, the invention further comprises: a second conductive structure, the first conductive structure being electrically connected to the chip via the second conductive structure; Preferably, the second conductive structure comprises a solder ball.

[0008] In one embodiment, the device further comprises: a dielectric layer and a third conductive structure, wherein the dielectric layer is located on a side close to the second surface of the substrate, the third conductive structure is located in the dielectric layer, and the first conductive structure is electrically connected to the third conductive structure; Preferably, the dielectric layer includes M sub-dielectric layers, the i+1th sub-dielectric layer is located on the side of the i-th sub-dielectric layer away from the substrate, the third conductive structure includes a plurality of first portions arranged at intervals, the first portion is located in the M-th sub-dielectric layer and on the surface of the M-1-th sub-dielectric layer away from the substrate, the number of first conductive structures corresponding to any one chip is at least one, one first conductive structure is electrically connected to one first portion, M is an integer greater than or equal to 3, and i is an integer between 1 and M in sequence; Preferably, M is equal to the number of chips; Preferably, the third conductive structure further includes a second portion and a third portion, the second portion electrically connected to the first conductive structure corresponding to the i-th chip is located on a surface of the |iM|-th sub-dielectric layer away from the substrate, the third portion is located between the first portion and the second portion, and the first portion is electrically connected to the second portion through the third portion; Wherein, when i is M, the second portion electrically connected to the first conductive structure corresponding to the Mth chip is located on the second surface; when i is 1, the second portion electrically connected to the first conductive structure corresponding to the first chip coincides with the first portion, and the first portion extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure; when i is any value from 2 to M-1, the second portion extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure; Preferably, it further comprises: a fourth conductive structure, located on a side of the dielectric layer away from the substrate, the fourth conductive structure being electrically connected to the third conductive structure; Preferably, the fourth conductive structure is electrically connected to the first portion; Preferably, the fourth conductive structure comprises a solder ball.

[0009] In one embodiment, the front sides of the plurality of chips are arranged toward the second surface; Preferably, the types of the multiple chips are the same or different; Preferably, the type of chip includes a memory chip and / or a logic chip; Preferably, the types of chips include memory chips and logic chips, and the memory chip is located on a side of the logic chip close to the second surface.

[0010] A second aspect of the present application provides a method for preparing a packaging structure, comprising: A groove is provided in the substrate, wherein the opening of the groove is located on the first surface of the substrate; the groove includes a plurality of connected cavities, wherein the plurality of cavities include a first cavity and a second cavity, wherein the first cavity is located on a side of the second cavity close to the second surface, wherein the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface, and the first surface and the second surface are arranged opposite to each other; A plurality of through holes are provided in the substrate, the plurality of through holes comprising a first through hole and a second through hole, the first through hole penetrates to a surface of the substrate close to the groove corresponding to the first cavity, and the second through hole penetrates to a surface of the substrate close to the groove corresponding to the second cavity; filling a first conductive structure in the through hole; Multiple chips are embedded in multiple cavities respectively; the chips include a first chip and a second chip, the first chip is located in the first cavity and electrically connected to the first conductive structure in the first through hole; the second chip is located in the second cavity and electrically connected to the first conductive structure in the second through hole.

[0011] In one embodiment, filling the first conductive structure in the through hole includes: filling the first conductive structure in the through hole by electroplating and / or printing; Preferably, after filling the first conductive structure in the through hole and before embedding the plurality of chips in the plurality of cavities respectively, the method further comprises: Preparing a dielectric layer on a side of the second surface facing away from the first surface; Preferably, after preparing a dielectric layer on the side of the second surface facing away from the first surface and before respectively embedding a plurality of chips in the plurality of cavities, the method further comprises: preparing a third conductive structure in the dielectric layer; Preferably, preparing the third conductive structure in the dielectric layer comprises: Preparing a first sub-dielectric material layer on the second surface, and patterning the first sub-dielectric material layer to obtain a first sub-dielectric layer, wherein the first sub-dielectric layer has a plurality of first openings; A second portion is prepared in the first opening, and a first conductive structure corresponding to the first chip is electrically connected to the second portion; An i-th sub-dielectric material layer is prepared on a surface of the first sub-dielectric layer facing away from the substrate, and the i-th sub-dielectric material layer is patterned to obtain an i-th sub-dielectric layer, wherein the i-th sub-dielectric layer has a plurality of i-th openings, and a second portion is prepared in the i-th opening, wherein the second portion extends in a direction perpendicular to the second surface and is electrically connected to a first conductive structure corresponding to an |iN|th chip, where N is an integer greater than or equal to 3, and i is an integer between 2 and N-1; An N-th sub-dielectric material layer is prepared on a surface of the N-1-th sub-dielectric layer facing away from the substrate, and the N-th sub-dielectric material layer is patterned to obtain an N-th sub-dielectric layer, wherein the N-th sub-dielectric layer has a plurality of N-th openings, and a first portion is prepared in the N-th opening, and the first portion corresponding to the first chip extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure.

[0012] In one embodiment, after filling the first conductive structure in the through hole and before embedding the plurality of chips in the plurality of cavities respectively, the method further includes: Prepare a second conductive structure on a side of the first conductive structure facing away from the second surface; Preferably, preparing the second conductive structure on the side of the first conductive structure away from the second surface comprises preparing the second conductive structure on the side of the first conductive structure away from the second surface by at least one of electroplating, printing or ball planting; Preferably, embedding a plurality of chips in a plurality of cavities respectively comprises: The front side of the chip faces the second surface and is soldered to the second conductive structure.

[0013] A third aspect of the present application provides a terminal device, including the above-mentioned packaging structure, or including the packaging structure prepared by the above-mentioned preparation method.

[0014] According to the packaging structure provided in the embodiment of the present application, the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface, and the size of the second chip that can be accommodated in the second cavity is greater than or equal to the size of the first chip that can be accommodated in the first cavity; the second cavity is located on the side of the first cavity away from the second surface, and the first cavity and the second cavity are connected, so that the second chip is located on the side of the first chip away from the second surface, so that the second chip is stacked on the first chip; a plurality of through holes are opened in the substrate and conductive structures are filled in the through holes, which is conducive to realizing electrical connection of the chip without opening holes in the chip, so that the packaging structure is easy to implement, with low cost and high yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the packaging structure in one embodiment of the present application.

[0016] Figure 2 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0017] Figure 3 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0018] Figure 4 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0019] Figure 5 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0020] Figure 6 This is a schematic flow chart of a method for preparing a packaging structure in one embodiment of the present application.

[0021] Figures 7 to 14 This is a schematic diagram of the preparation process of a packaging structure in one embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0024] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0025] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0026] The first aspect of the present application provides a packaging structure, referring to Figure 1The structural schematic diagram of the packaging structure shown in the figure, the packaging structure includes: a substrate 100, including a first surface 110, a second surface 120 arranged opposite to the first surface 110, a groove 130 and a plurality of through holes 140; the opening of the groove 130 is located on the first surface 110; the groove 130 includes a plurality of connected cavities 131, the plurality of cavities 131 include a first cavity 1311 and a second cavity 1312, the first cavity 1311 is located on the side of the second cavity 1312 close to the second surface 120, and the orthographic projection of the second cavity 1312 on the second surface 120 covers the orthographic projection of the first cavity 1311 on the second surface 120; the plurality of through holes 140 include a first cavity 1311 and a second cavity 1312. Hole 141 and a second through hole 142, the first through hole 141 penetrates to the surface of the substrate 100 corresponding to the first cavity 1311 close to the groove 130, and the second through hole 142 penetrates to the surface of the substrate 100 corresponding to the second cavity 1312 close to the groove 130; a first conductive structure 200, filling the through hole 140; a plurality of chips 300, the chip 300 includes a first chip 310 and a second chip 320, the first chip 310 is located in the first cavity 1311, and is electrically connected to the first conductive structure 200 in the first through hole 141; the second chip 320 is located in the second cavity 1312, and is electrically connected to the first conductive structure 200 in the second through hole 142.

[0027] According to the packaging structure provided by the embodiment of the present application, the orthographic projection of the second cavity 1312 on the second surface 120 covers the orthographic projection of the first cavity 1311 on the second surface 120, and the size of the second chip 320 that can be accommodated by the second cavity 1312 is greater than or equal to the size of the first chip 310 that can be accommodated by the first cavity 1311; the second cavity 1312 is located on the side of the first cavity 1311 away from the second surface 120, and the first cavity 1311 and the second cavity 1312 are connected, so that the second chip 320 is located on the side of the first chip 310 away from the second surface 120, so that the second chip 320 is stacked with the first chip 310, and chips 300 of different sizes can be integrated together, which is beneficial to reducing the packaging area and volume; multiple through holes 140 are opened in the substrate 100 and the first conductive structure 200 is filled in the through holes 140, which is beneficial to realize the electrical connection of the chip, without opening holes in the chip, so that the packaging structure is easy to implement, with low cost and high yield.

[0028] It should be noted that the surface of the substrate 100 close to the groove 130 corresponding to the first cavity 1311 includes a surface perpendicular to the second surface 120 and a surface parallel to the second surface 120; the surface of the substrate 100 close to the groove 130 corresponding to the second cavity 1312 includes a surface perpendicular to the second surface 120 and a surface parallel to the second surface 120.

[0029] It can be understood that the first through hole 141 penetrates to the surface of the substrate 100 corresponding to the first cavity 1311 and close to the groove 130, which can be understood in a broad sense, for example, the first through hole 141 penetrates from the side wall of the substrate 100 to the surface of the substrate 100 corresponding to the first cavity 1311 and close to the groove 130, and for another example, the first through hole 141 penetrates from the second surface 120 to the surface of the substrate 100 corresponding to the first cavity 1311 and close to the groove 130. It should be noted that the side wall of the substrate 100 is perpendicular to the second surface 120.

[0030] It can be understood that the second through hole 142 penetrates to the surface of the substrate 100 corresponding to the second cavity 1312 and close to the groove 130, which can be understood in a broad sense, for example, the second through hole 142 penetrates from the side wall of the substrate 100 to the surface of the substrate 100 corresponding to the second cavity 1312 and close to the groove 130, and for another example, the second through hole 142 penetrates from the second surface 120 to the surface of the substrate 100 corresponding to the second cavity 1312 and close to the groove 130. It should be noted that the side wall of the substrate 100 is perpendicular to the second surface 120.

[0031] In one embodiment, referring to Figure 2 In the schematic diagram of the package structure shown, the groove 130 further includes a third cavity 1313, a fourth cavity 1314, ..., an Nth cavity 131N, the i+1th cavity is located on the side of the ith cavity close to the second surface 120, the orthographic projection of the i+1th cavity on the second surface 120 covers the orthographic projection of the ith cavity on the second surface 120, N is an integer greater than or equal to 3, for example, N can be 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.; i is an integer between 1 and N in sequence. Therefore, the number of cavities in the package structure is large, and more chips can be accommodated, which is conducive to reducing the package area and volume.

[0032] It is understandable that, in actual use, the number of cavities can be flexibly selected according to actual conditions.

[0033] In one embodiment, referring to Figure 2 As shown in the schematic diagram of the package structure, the chip 300 further includes a third chip 330, a fourth chip 340, ..., an Nth chip 3N0, and the i-th chip is located in the i-th cavity. Thus, it is convenient to stack multiple chips and reduce the package area and volume.

[0034] In one embodiment, the orthographic projection of the (i+1)th chip on the second surface covers the orthographic projection of the (i)th chip on the second surface 120. Thus, the size of the (i+1)th chip is larger than that of the (i)th chip, which is beneficial to stacking chips of different sizes, reducing the area of ​​the packaging structure, and realizing device miniaturization.

[0035] Exemplarily, the distance between the surface of the Nth chip away from the second surface and the second surface is equal to the distance between the first surface and the second surface, or the distance between the first surface and the second surface is slightly greater than the distance between the surface of the Nth chip away from the second surface and the second surface.

[0036] In one embodiment, the plane where the chip 300 is located is parallel to the second surface 120 .

[0037] In one embodiment, N chips 300 are spaced apart in a direction a perpendicular to the second surface 120. Thus, there is a certain distance between the multiple chips 300, which is beneficial to the subsequent electrical connection between the chip 300 and the first conductive structure 200 and reduces the manufacturing difficulty.

[0038] In one embodiment, the through hole 140 further includes a third through hole 143, a fourth through hole 144, ... an Nth through hole 14N, the i-th through hole is connected to the i-th cavity, and the first conductive structure 200 located in the i-th through hole is electrically connected to the i-th chip. Thus, the chip 300 can realize the electrical connection between the chip 300 and other structures or realize the electrical connection between different chips 300 through the first conductive structure 200, for example, it is convenient for the subsequent chip 30 to be electrically connected to the third conductive structure through the first conductive structure 200, without opening a hole in the chip 300, which is easy to realize, and is conducive to reducing costs and improving yield.

[0039] In one embodiment, along the direction perpendicular to the second surface 120, the centroid of the i-th cavity and the centroid of the substrate 100 are located on the same straight line. Thus, the substrate 100 is a symmetrical structure, and the chip 300 in the substrate 100 is also symmetrical about the symmetry axis of the substrate 100, which is beneficial to improve the stability of the packaging structure, and is more conducive to manufacturing and improving product yield.

[0040] In one embodiment, along the direction perpendicular to the second surface 120, the surface of the substrate 100 close to the groove 130 has a stepped structure. Therefore, when the chip 300 is placed in the cavity 131, the chip 300 can be placed on the step, and a through hole 140 is opened at the step corresponding to the chip 300, so that the through hole 140 can be opened in the substrate 100 to realize the electrical connection between the chip 300 and the first conductive structure 200, and then the electrical connection between different chips 300 or between the chip 300 and other structures can be realized through the first conductive structure 200, without opening a through hole in the chip 300, simplifying the preparation process of the packaging structure and reducing the production cost; and placing the chip 300 on the step is conducive to avoiding direct contact between different chips 300, and can also improve the stability of the placement of the chip 300, which is conducive to improving the yield of the packaging structure. In one embodiment, the through hole 140 extends in a direction perpendicular to the second surface 120, and the through hole 140 penetrates the second surface 120, so that the first conductive structure 200 extends in a direction perpendicular to the second surface 120, which is beneficial to wiring on the side of the second surface 120 of the substrate 100 away from the chip 300, simplifying the wiring difficulty and reducing the process cost.

[0041] In one embodiment, the substrate comprises glass, whereby the glass substrate has strong rigidity, strong bearing capacity, strong stability of the packaging structure, and low cost of the glass.

[0042] In one embodiment, referring to Figure 3 The schematic diagram of the package structure shown in FIG. 1 further includes: a second conductive structure 400, and the first conductive structure 200 is connected to the chip 300 via the second conductive structure 400. Therefore, the electrical connection between the first conductive structure 200 and the chip 300 is better.

[0043] In one embodiment, the second conductive structure 400 includes solder balls, so that the electrical connection between the first conductive structure 200 and the chip 300 is better. Exemplarily, there are intervals between different chips 300, which is conducive to the production of solder balls and reduces the difficulty of the process.

[0044] In one embodiment, referring to Figure 4 The schematic diagram of the package structure shown in the figure further includes: a dielectric layer 500 and a third conductive structure 600. The dielectric layer 500 is located on the side of the second surface 120 away from the first surface 110. The third conductive structure 600 is located in the dielectric layer 500. The first conductive structure 200 is electrically connected to the third conductive structure 600. Thus, the third conductive structure 600 leads the first conductive structure 200 out, and the electrical connection between the chips 300 and the chips 300, or between the chips 300 and other structures can be achieved through the third conductive structure 600.

[0045] For example, refer to Figure 5The schematic diagram of the structure of the package structure shown in the figure, the dielectric layer 500 includes M layers of sub-dielectric layers 510, and along the direction away from the substrate 100, the sub-dielectric layers 510 are the first layer of sub-dielectric layer 510, the second layer of sub-dielectric layer 510, ... the Mth layer of sub-dielectric layer 510, the third conductive structure 600 includes a plurality of first portions 610 arranged at intervals, the first portion 610 is located on the Mth layer of sub-dielectric layer 510 and on the surface of the M-1th layer of sub-dielectric layer 510 away from the substrate 100, the number of first conductive structures 200 corresponding to any chip 300 is at least one, one first conductive structure 200 is electrically connected to one first portion 610, M is an integer greater than or equal to 3, and i is an integer between 1 and M in turn. The first conductive structure 200 corresponding to the chip 300 refers to: the surface of the substrate 100 close to the i-th cavity where the i-th chip is located, which is penetrated by the first conductive structure 200, and the first conductive structure 200 is the first conductive structure 200 corresponding to the i-th chip.

[0046] In one embodiment, the third conductive structure 600 also includes a second part 620 and a third part 630, the second part 620 electrically connected to the first conductive structure 200 corresponding to the i-th chip is located on the surface of the |iM|-th dielectric layer 510 facing away from the substrate 100, the third part 630 is located between the first part 610 and the second part 620, and the first part 610 and the second part 620 are electrically connected through the third part 630; wherein, when i is M, the second part 620 electrically connected to the first conductive structure 200 corresponding to the M-th chip is located on the second surface 120; when i is 1, the second part 620 electrically connected to the first conductive structure 200 corresponding to the 1st chip coincides with the first part 610, and the first part 610 extends in a direction perpendicular to the second surface 120 and is electrically connected to the first conductive structure 200; when i is any value from 2 to M-1, the second part 620 extends in a direction perpendicular to the second surface 120 and is electrically connected to the first conductive structure 200. It should be noted that the structures of the above dielectric layer 500 and the third conductive structure 600 are only used to explain the present application and cannot be understood as a limitation of the present application. In actual situations, the number of layers of the sub-dielectric layer 510 may be the same as or different from the number of chips 300.

[0047] Exemplarily, M is equal to the number of chips 300 .

[0048] In one embodiment, referring to Figure 5 The schematic diagram of the package structure shown in the figure, the package structure also includes: a fourth conductive structure 700, located on the side of the dielectric layer 500 away from the substrate 100, and the fourth conductive structure 700 is electrically connected to the third conductive structure 600. Thus, it is convenient to realize the electrical connection between the package structure and other structures. Exemplarily, the fourth conductive structure 700 is electrically connected to the first part 610.

[0049] In one embodiment, the fourth conductive structure 700 includes solder balls, thereby facilitating electrical connection between the package structure and other structures.

[0050] In one embodiment, the front sides of the plurality of chips 300 are arranged toward the second surface 120. This facilitates wiring on the side of the second surface 120 away from the substrate 100, simplifies the wiring process, reduces the manufacturing cost, and improves the yield.

[0051] It is understandable that the front side of the chip 300 refers to the active side, that is, the side with the circuit.

[0052] In one embodiment, the types of the multiple chips are the same or different; preferably, the types of the chips include memory chips and / or logic chips. Thus, chips with different functions can be integrated together, so that the packaging structure has diversified functions.

[0053] In one embodiment, the types of chips include memory chips and logic chips, and the memory chips are located on the side of the logic chips close to the second surface. Thus, the size of the memory chips is relatively small, and the sizes of the memory chips and the logic chips are relatively large, which is conducive to integrating the chips with the above-mentioned different functions together, reducing the volume and area of ​​the packaging structure, and making the packaging structure have diversified functions.

[0054] Exemplarily, the materials of the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure and the dielectric layer are conventional materials. For example, the first conductive structure may be silver, the second conductive structure may be silver, the third conductive structure may be silver, the fourth conductive structure may be silver, the dielectric layer may be polyimide, etc. These are not improvements of the present application and will not be elaborated on here.

[0055] The second aspect of the present application provides a method for preparing a packaging structure, referring to Figure 6 The preparation method of the packaging structure shown includes the following steps.

[0056] S100: a groove is formed in the substrate, wherein the opening of the groove is located on the first surface of the substrate. Figure 7 .

[0057] It should be noted that the substrate and the first surface are consistent with the above description and will not be described in detail here.

[0058] It should be noted that the groove is consistent with the previous description and will not be described in detail here.

[0059] In one embodiment, the groove includes a plurality of connected cavities, the plurality of cavities include a first cavity and a second cavity, the first cavity is located on the side of the second cavity close to the second surface, the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface, and the first surface and the second surface are arranged opposite to each other.

[0060] It should be noted that the first cavity, the second cavity, and the second surface are consistent with the previous description and will not be elaborated herein.

[0061] Exemplarily, the method of forming the groove in the substrate includes, but is not limited to, forming the groove by laser scribing, forming the groove by photolithography, or forming the groove by mechanical means.

[0062] S200: a plurality of through holes are formed in the substrate, the plurality of through holes comprising a first through hole and a second through hole, the first through hole penetrates to a surface of the substrate corresponding to the first cavity close to the groove, and the second through hole penetrates to a surface of the substrate corresponding to the second cavity close to the groove, for details, see Figure 8 and 9 .

[0063] It should be noted that Figure 8 is a schematic diagram of the top view structure of the obtained substrate, Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure of the substrate along the AA' direction.

[0064] It should be noted that the through hole, the first through hole and the second through hole are consistent with the previous description and will not be described in detail here.

[0065] Exemplarily, the method of opening a through hole in the substrate includes, but is not limited to, opening a hole by laser scribing, opening a hole by photolithography, or opening a hole mechanically.

[0066] S300: Fill the first conductive structure in the through hole, see Fig.10 .

[0067] It should be noted that the first conductive structure is consistent with the above description and will not be elaborated herein.

[0068] In one embodiment, filling the first conductive structure in the through hole includes: filling the first conductive structure in the through hole by electroplating and / or printing.

[0069] In one embodiment, after the first conductive structure is filled in the through hole and before the plurality of chips are respectively embedded in the plurality of cavities, the method further includes the following steps: preparing a dielectric layer on the side of the second surface facing away from the first surface, as shown in FIG. Fig.11 .

[0070] It should be noted that the dielectric layer is consistent with the previous description and will not be described in detail here.

[0071] Exemplarily, the dielectric layer may be prepared by coating, pasting, etc., which will not be elaborated herein.

[0072] In one embodiment, after preparing a dielectric layer on the side of the second surface facing away from the first surface, before embedding multiple chips in the multiple cavities, the following steps are further included: preparing a third conductive structure in the dielectric layer, specifically referring to Fig.12 .

[0073] It should be noted that the third conductive structure is consistent with the above description and will not be elaborated herein.

[0074] In one embodiment, preparing the third conductive structure in the dielectric layer includes: preparing a first layer of sub-dielectric material layer on the second surface, patterning the first layer of sub-dielectric material layer to obtain a first layer of sub-dielectric layer, wherein the first layer of sub-dielectric layer has a plurality of first openings; preparing a second portion in the first opening, wherein the first conductive structure corresponding to the first chip is electrically connected to the second portion; preparing an i-th layer of sub-dielectric material layer on the surface of the first layer of sub-dielectric layer facing away from the substrate, patterning the i-th layer of sub-dielectric material layer to obtain an i-th layer of sub-dielectric layer, wherein the i-th layer of sub-dielectric layer has a plurality of i-th openings, wherein the i-th layer of sub-dielectric layer has a plurality of i-th openings. A second portion is prepared in the opening, the second portion extends in a direction perpendicular to the second surface and is electrically connected to a first conductive structure corresponding to the |iM|th chip, M is an integer greater than or equal to 3, and i is an integer between 2 and M-1 in sequence; an Mth sub-dielectric material layer is prepared on a surface of the M-1th sub-dielectric layer facing away from the substrate, the Mth sub-dielectric material layer is patterned to obtain an Mth sub-dielectric layer, the Mth sub-dielectric layer has a plurality of Mth openings, a first portion is prepared in the Mth opening, the first portion corresponding to the 1st chip extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure.

[0075] In one embodiment, after the first conductive structure is filled in the through hole, before the plurality of chips are respectively embedded in the plurality of cavities, the method further includes: preparing a second conductive structure on a side of the first conductive structure away from the second surface, as shown in FIG. Fig.13 .

[0076] It should be noted that the second conductive structure is consistent with the above description and will not be described in detail here.

[0077] In one embodiment, preparing the second conductive structure on the side of the first conductive structure away from the second surface includes preparing the second conductive structure on the side of the first conductive structure away from the second surface by at least one of electroplating, printing or ball planting.

[0078] In a specific embodiment, after preparing the second conductive structure on the side of the first conductive structure away from the second surface, before respectively embedding the plurality of chips in the plurality of cavities, the method further includes: preparing a fourth conductive structure on the side of the dielectric layer away from the substrate, the fourth conductive structure being electrically connected to the third conductive structure, and referring to Fig.13 .

[0079] It should be noted that the fourth conductive structure is consistent with the above description and will not be described in detail here.

[0080] Exemplarily, the order of manufacturing the second conductive structure and the fourth conductive structure in the manufacturing process is not limited, and the second conductive structure may be manufactured first and then the fourth conductive structure, or the fourth conductive structure may be manufactured first and then the second conductive structure.

[0081] S400: Embed multiple chips in multiple cavities, see Fig.14 .

[0082] It should be noted that the chip is consistent with the previous description and will not be described in detail here.

[0083] In one embodiment, the chip includes a first chip and a second chip, the first chip is located in the first cavity and electrically connected to the first conductive structure in the first through hole; the second chip is located in the second cavity and electrically connected to the first conductive structure in the second through hole.

[0084] In one embodiment, embedding multiple chips in multiple cavities respectively includes: placing the front side of the chip facing the second surface and welding the chip to the second conductive structure. Thus, the process of stacking the chips is relatively simple, and there is no need to open holes in the chips, which reduces the manufacturing difficulty and improves the manufacturing yield.

[0085] A third aspect of the present application provides a terminal device, which includes the above-mentioned packaging structure, or includes the packaging structure prepared by the above-mentioned preparation method.

[0086] It should be noted that the above-mentioned terminal device can be a desktop computer, a tablet computer, a high-computing-power calculator, etc.

[0087] It should be noted that, in addition to the packaging structure described above, the terminal device may also include structures that a conventional terminal device should have, such as a display panel, a touch panel, a housing, etc., which will not be elaborated here.

[0088] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0089] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A packaging structure, characterized in that: include: A substrate, comprising a first surface, a second surface arranged opposite to the first surface, a groove and a plurality of through holes; The opening of the groove is located on the first surface; The groove includes a plurality of connected cavities, the plurality of cavities include a first cavity and a second cavity, the first cavity is located on the side of the second cavity close to the second surface, and the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface; the plurality of through holes include a first through hole and a second through hole, the first through hole penetrates to the surface of the substrate corresponding to the first cavity close to the groove, and the second through hole penetrates to the surface of the substrate corresponding to the second cavity close to the groove; A first conductive structure filling the through hole; A plurality of chips include a first chip and a second chip, wherein the first chip is located in the first cavity and electrically connected to the first conductive structure in the first through hole; and the second chip is located in the second cavity and electrically connected to the first conductive structure in the second through hole.

2. The packaging structure according to claim 1, characterized in that: The groove also includes a third cavity, a fourth cavity...an Nth cavity, the i+1th cavity is located on the side of the i-th cavity close to the second surface, the orthographic projection of the i+1th cavity on the second surface covers the orthographic projection of the i-th cavity on the second surface, N is an integer greater than or equal to 3, and i is an integer between 1 and N.

3. The packaging structure according to claim 2, characterized in that: The chips also include a third chip, a fourth chip, ... an Nth chip, and the i-th chip is located in the i-th cavity.

4. The packaging structure according to claim 3, characterized in that: The orthographic projection of the (i+1)th chip on the second surface covers the orthographic projection of the i-th chip on the second surface; and / or, the plane where the chip is located is parallel to the second surface; And / or, the N chips are spaced apart in a direction perpendicular to the second surface.

5. The packaging structure according to claim 3 or 4, characterized in that: The through holes further include a third through hole, a fourth through hole, ..., an Nth through hole, the ith through hole is connected to the ith cavity, and the first conductive structure located in the ith through hole is electrically connected to the ith chip.

6. The packaging structure according to claim 2, characterized in that: Along a direction perpendicular to the second surface, the centroid of the i-th cavity and the centroid of the substrate are located on the same straight line; And / or, along a direction perpendicular to the second surface, a surface of the substrate close to the groove has a stepped structure.

7. The packaging structure according to claim 6, characterized in that: The through hole extends in a direction perpendicular to the second surface.

8. The packaging structure according to claim 7, characterized in that: The through hole penetrates to the second surface; And / or, the substrate comprises glass.

9. The packaging structure according to claim 1, characterized in that: Also includes: A second conductive structure, wherein the first conductive structure is electrically connected to the chip through the second conductive structure.

10. The packaging structure according to claim 9, characterized in that: The second conductive structure includes a solder ball.

11. The packaging structure according to claim 1, characterized in that: Also includes: A dielectric layer and a third conductive structure, wherein the dielectric layer is located on a side close to the second surface of the substrate, the third conductive structure is located in the dielectric layer, and the first conductive structure is electrically connected to the third conductive structure.

12. The packaging structure according to claim 11, characterized in that: The dielectric layer includes M layers of sub-dielectric layers, the i+1th sub-dielectric layer is located on the side of the i-th sub-dielectric layer away from the substrate, the third conductive structure includes a plurality of first portions arranged at intervals, the first portions are located in the M-th sub-dielectric layer and on the surface of the M-1-th sub-dielectric layer away from the substrate, the number of the first conductive structures corresponding to any one of the chips is at least one, one first conductive structure is electrically connected to one first portion, M is an integer greater than or equal to 3, and i is an integer between 1 and M in sequence.

13. The packaging structure according to claim 12, characterized in that: M is equal to the number of chips.

14. The packaging structure according to claim 12, characterized in that: The third conductive structure further includes a second portion and a third portion, the second portion electrically connected to the first conductive structure corresponding to the i-th chip is located on a surface of the |iM|-th sub-dielectric layer away from the substrate, the third portion is located between the first portion and the second portion, and the first portion and the second portion are electrically connected via the third portion; Among them, when i is M, the second part electrically connected to the first conductive structure corresponding to the Mth chip is located on the second surface; when i is 1, the second part electrically connected to the first conductive structure corresponding to the 1st chip coincides with the first part, and the first part extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure; when i is any value between 2 and M-1, the second part extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure.

15. The packaging structure according to any one of claims 11 to 14, characterized in that: Also includes: The fourth conductive structure is located on a side of the dielectric layer away from the substrate, and the fourth conductive structure is electrically connected to the third conductive structure.

16. The packaging structure according to claim 15, characterized in that: The fourth conductive structure is electrically connected to the first portion; And / or, the fourth conductive structure includes a solder ball.

17. The packaging structure according to claim 1, characterized in that: The front sides of the plurality of chips are arranged toward the second surface; and / or, the types of the plurality of chips are the same or different; And / or, the type of the chip includes a memory chip and / or a logic chip; And / or, the types of the chips include a memory chip and a logic chip, and the memory chip is located on a side of the logic chip close to the second surface.

18. A method for preparing a packaging structure, characterized in that: include: A groove is formed in the substrate, wherein an opening of the groove is located on the first surface of the substrate; The groove includes a plurality of connected cavities, the plurality of cavities include a first cavity and a second cavity, the first cavity is located on a side of the second cavity close to the second surface, the orthographic projection of the second cavity on the second surface covers the orthographic projection of the first cavity on the second surface, and the first surface and the second surface are arranged opposite to each other; A plurality of through holes are provided in the substrate, the plurality of through holes comprising a first through hole and a second through hole, the first through hole penetrating a surface of the substrate corresponding to the first cavity close to the groove, and the second through hole penetrating a surface of the substrate corresponding to the second cavity close to the groove; filling a first conductive structure in the through hole; A plurality of chips are respectively embedded in the plurality of cavities; the chips include a first chip and a second chip, the first chip is located in the first cavity and electrically connected to the first conductive structure in the first through hole; the second chip is located in the second cavity and electrically connected to the first conductive structure in the second through hole.

19. The preparation method according to claim 18, characterized in that: Filling the first conductive structure in the through hole includes: filling the first conductive structure in the through hole by electroplating and / or printing.

20. The preparation method according to claim 18 or 19, characterized in that: After the first conductive structure is filled in the through hole and before the multiple chips are respectively embedded in the multiple cavities, the method further includes: A dielectric layer is formed on a side of the second surface facing away from the first surface.

21. The preparation method according to claim 20, characterized in that: After preparing a dielectric layer on a side of the second surface facing away from the first surface and before respectively embedding a plurality of chips in the plurality of cavities, the method further includes: A third conductive structure is prepared in the dielectric layer.

22. The preparation method according to claim 21, characterized in that: Preparing a third conductive structure in the dielectric layer includes: Preparing a first sub-dielectric material layer on the second surface, and patterning the first sub-dielectric material layer to obtain a first sub-dielectric layer, wherein the first sub-dielectric layer has a plurality of first openings; preparing a second portion in the first opening, the first conductive structure corresponding to the first chip being electrically connected to the second portion; An i-th sub-dielectric material layer is prepared on a surface of the first sub-dielectric layer away from the substrate, and the i-th sub-dielectric material layer is patterned to obtain an i-th sub-dielectric layer, wherein the i-th sub-dielectric layer has a plurality of i-th openings, and the second portion is prepared in the i-th opening, wherein the second portion extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure corresponding to the |iM|th chip, where M is an integer greater than or equal to 3, and i is an integer between 2 and M-1; An M-th sub-dielectric material layer is prepared on a surface of the M-1 sub-dielectric layer facing away from the substrate, and the M-th sub-dielectric material layer is patterned to obtain an M-th sub-dielectric layer, wherein the M-th sub-dielectric layer has a plurality of M-th openings, and a first portion is prepared in the M-th opening, and the first portion corresponding to the first chip extends in a direction perpendicular to the second surface and is electrically connected to the first conductive structure.

23. The preparation method according to claim 18, characterized in that: After the first conductive structure is filled in the through hole and before the multiple chips are respectively embedded in the multiple cavities, the method further includes: A second conductive structure is prepared on a side of the first conductive structure facing away from the second surface.

24. The preparation method according to claim 23, characterized in that: The preparing the second conductive structure on the side of the first conductive structure away from the second surface includes preparing the second conductive structure on the side of the first conductive structure away from the second surface by at least one of electroplating, printing or ball planting.

25. The preparation method according to claim 23 or 24, characterized in that: Embedding a plurality of chips in the plurality of cavities respectively comprises: The front side of the chip faces the second surface and is soldered to the second conductive structure.

26. A terminal device, characterized in that: A packaging structure comprising any one of claims 1 to 17, or a packaging structure prepared by the preparation method of any one of claims 18 to 25.

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