Layout method of power devices in multi-phase interleaving parallel circuit

Abstract

The invention provides a layout method of high-side and low-side power devices in a multi-phase interleaving parallel circuit, aiming at the multi-phase interleaving parallel circuit formed by monolithic integrated multi-phase power devices, symmetrical packaging and PCB (Printed Circuit Board) design are adopted, and the consistency of parasitic parameters of each phase of circuit is kept; the high-side crystal grains and the low-side crystal grains can also be stacked by adopting a Si interposer or PCB (Printed Circuit Board) scheme or a bonding scheme, so that the parasitic parameters between the high-side monolithic integrated multiphase power device and the low-side monolithic integrated multiphase power device are further reduced while the consistency of the parasitic parameters is maintained, the problem of non-uniform current of each phase caused by inconsistent parasitic parameters of each phase circuit is solved, and the reliability of the device is improved. And meanwhile, the high-frequency characteristic of the interleaved parallel circuit system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit integration, and more specifically, to a layout method of high-side and low-side power devices in a multi-phase interleaved parallel circuit. Background Art

[0002] With the rapid development of data centers, especially the development of artificial intelligence technology, XPU core chips are getting larger and larger, and the computing power and power consumption are getting stronger and stronger. The requirements for power supply converters are also gradually increasing: (1) The output current is large and the load current changes quickly, requiring the converter to have high efficiency under different load conditions; (2) The output voltage is low, and in order to avoid voltage ripple interfering with the logic of digital circuits, the converter output voltage ripple is required to be low; (3) XPU has a greater area requirement, and the converter volume needs to be reduced, mainly by reducing the volume of passive components.

[0003] To solve the above problems, circuit designers proposed a multi-phase interleaved parallel converter design, such as Figure 1 shown.

[0004] Although interleaved parallel converters have the advantages of high current and low ripple output, how to ensure balanced current distribution in each phase branch is also an issue that cannot be ignored. The imbalance of phase current will cause different current stresses of components in each phase branch, resulting in a reduction in the service life of the converter and even causing the power supply system to be paralyzed due to converter collapse. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present invention provides a layout method for high-side and low-side power devices in a multi-phase interleaved parallel circuit, which solves the problem of phase current imbalance caused by inconsistent parasitic parameters of each phase circuit in the multi-phase interleaved parallel circuit.

[0006] The present invention provides a layout method of high-side and low-side power devices in a multi-phase interleaved parallel circuit, wherein the multi-phase interleaved parallel circuit comprises a high-side multi-phase power device and a low-side multi-phase power device, wherein the high-side multi-phase power device is integrated on a high-side die, and the low-side multi-phase power device is integrated on a low-side die, and the layout method comprises:

[0007] The high-side multi-phase power device and the low-side multi-phase power device are respectively distributed in a row on the high-side die and the low-side die, so that the parasitic parameters of each phase circuit of the multi-phase interleaved parallel circuit remain consistent; or,

[0008] The high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Si interposer solution, a PCB solution, or a bonding solution.

[0009] Based on the above technical solution, the present invention can also make the following improvements.

[0010] Optionally, the high-side multi-phase power device and the low-side multi-phase power device each include a plurality of power devices, and the high-side multi-phase power device and the low-side multi-phase power device are respectively distributed in a row on the high-side die and the low-side die, so that the parasitic parameters of each phase circuit of the multi-phase interleaved parallel circuit remain consistent, including:

[0011] Distributing the high-side multi-phase power devices in a row on the high-side die, and distributing the low-side multi-phase power devices in a row on the low-side die;

[0012] The high-side multi-phase power device and the low-side multi-phase power device are packaged separately;

[0013] Leading out the source electrodes of the power devices of each phase on the high side to one side of the high side packaging frame for arrangement, and leading out the gate electrodes and drain electrodes of the power devices of each phase on the high side to the other side of the high side packaging frame for arrangement; and leading out the drain electrodes of the power devices of each phase on the low side to one side of the low side packaging frame for arrangement, and leading out the source electrodes and gate electrodes of the power devices of each phase on the low side to the other side of the low side packaging frame for arrangement;

[0014] The package body of the high-side chip and the low-side chip are placed side by side on a PCB board, and the SW ends of the high-side chip and the low-side chip are electrically connected. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

[0015] Optionally, one side of the high-side packaging frame where the source electrodes of the power devices of each phase on the high side are located is close to one side of the low-side packaging frame where the drain electrodes of the power devices of each phase on the low side are located.

[0016] Optionally, the high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Siinterposer solution, a PCB solution, or a bonding solution, including:

[0017] Distributing the high-side multi-phase power devices in multiple rows and columns on the high-side die, and distributing the low-side multi-phase power devices in multiple rows and columns on the low-side die;

[0018] The high-side die and the low-side die are stacked up and placed on the upper and lower sides of a Siinterposer or a PCB board, and the SW ends of the high-side die and the low-side die are electrically connected in a vertical direction in space. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

[0019] Optionally, stacking the high-side die and the low-side die on the upper and lower sides of a Siinterposer or a PCB board comprises:

[0020] The high-side die and the low-side die are wafer-level packaged, the high-side die is placed on the lower side or upper side of the Si interposer or PCB board, and the low-side die is placed on the upper side or lower side of the Si interposer or PCB board;

[0021] The SW ends between the source electrodes of the power devices of each phase in the high-side die and the drain electrodes of the power devices of each phase in the low-side die are electrically connected through TSVs on the Siinterposer or through holes on the PCB board.

[0022] Optionally, the SW terminals between the source of each phase power device in the high-side die and the drain of each phase power device in the low-side die are electrically connected through TSV on the Siinterposer or through holes on the PCB board, further comprising:

[0023] Connecting the gate of each phase power device in the high-side die to the upper surface of the Siinterposer or the PCB board through the through hole of the Siinterposer or the PCB board;

[0024] The drain of each phase power device in the high-side grain is connected to its own substrate through interconnecting metal, connected to the upper surface of Siinterposer or PCB board through the through hole of Siinterposer or PCB board, and connected to VIN port; and the source of each phase power device in the low-side grain is connected to its own substrate through interconnecting metal, led out to the area away from the grain stacking interface through the metal routing on the upper surface of Si interposer or PCB board, and connected to GND port.

[0025] Optionally, the high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Siinterposer solution, a PCB solution, or a bonding solution, including:

[0026] Distributing the high-side multi-phase power devices in multiple rows and columns on the high-side die, and distributing the low-side multi-phase power devices in multiple rows and columns on the low-side die;

[0027] The low-side grain and the high-side grain are stacked up and down, and the SW ends between the low-side grain and the high-side grain are bonded together, and the SW end refers to the endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

[0028] Optionally, the SW ends of the low-side die and the high-side die are bonded together, comprising:

[0029] The SW ends between the low-side crystal grain and the high-side crystal grain are bonded together by Cu / Cu welding or Au / Sn welding.

[0030] Optionally, the layout method further includes:

[0031] Leading out the gate and drain of each phase power device of the high-side grain to the surface of the high-side grain, away from the bonding interface area, through RDL, and bonding the gate of each phase power device in the low-side grain to the reserved electrode on the surface of the high-side grain by Cu / Cu welding or Au / Sn welding, leading out to the surface of the high-side grain, and leading out to the surface of the high-side grain, away from the bonding interface area, through the RDL of the high-side grain;

[0032] The drain of each phase power device in the high-side grain is connected to the substrate through the interconnecting metal, led out to the area away from the bonding interface through RDL, and connected to the VIN port; and the source of each phase power device in the low-side grain is connected to the substrate through the interconnecting metal, the electrode is bonded to the reserved electrode on the surface of the high-side grain through Cu / Cu welding or Au / Sn welding, led to the surface of the high-side grain, and then the electrode is led out to the area away from the bonding interface through RDL, and connected to the GND port.

[0033] The present invention provides a layout method for high-side and low-side power devices in a multi-phase interleaved parallel circuit. For a multi-phase interleaved parallel circuit composed of monolithically integrated multi-phase power devices, a symmetrical package and PCB design are adopted to maintain the consistency of parasitic parameters of each phase circuit. A Siinterposer or PCB solution, or a bonding solution, can also be adopted to stack high-side grains and low-side grains, and while maintaining the consistency of parasitic parameters, the parasitic parameters between the high-side and low-side monolithically integrated multi-phase power devices are further reduced, so as to solve the problem of uneven current of each phase caused by inconsistent parasitic parameters of each phase circuit, and at the same time improve the high-frequency characteristics of the interleaved parallel circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a circuit diagram of a multi-phase interleaved parallel DC / DC converter;

[0035] Figure 2 It is the schematic diagram of multi-phase interleaved parallel monolithic integration;

[0036] Figure 3 Schematic diagram for comparing the output voltage ripple of the interleaved parallel circuit and the current waveform flowing through the inductors of each phase, wherein Figure (a) is a schematic diagram for comparing the output voltage ripple of the interleaved parallel circuit and the current waveform flowing through the inductors of each phase when the parasitic parameters of the circuits of each phase are consistent, as well as an enlarged diagram in steady state (the inset on the right side of Figure (a)); Figure (b) is a schematic diagram for comparing the output voltage ripple of the interleaved parallel circuit and the current waveform flowing through the inductors of each phase when the parasitic parameters of the circuits of each phase are inconsistent, as well as an enlarged diagram in steady state (the inset on the right side of Figure (b));

[0037] Figure 4 A schematic diagram of a PCB layout of 4 rows and 2 columns of 8-phase parallel monolithic integrated Si-based GaN power switch tubes and the connection of the high / low side package chip SW terminals (1, 4 to 8);

[0038] Figure 5 Schematic diagram of the layout and packaging of high-side and low-side power devices in a multi-phase interleaved parallel circuit of the first embodiment of the present invention, wherein Figure (a) is a front top view of the packaging of the high-side grain, Figure (b) is a front top view of the packaging of the low-side grain, Figure (c) is a schematic diagram of the high-side grain and the corresponding packaging pins when it is packaged, Figure (d) is a schematic diagram of the low-side grain and the corresponding packaging pins when it is packaged, Figure (e) is a schematic diagram of the pins after the high-side grain is packaged, Figure (f) is a schematic diagram of the pins after the low-side grain is packaged, and Figure (g) is a schematic diagram of the arrangement of placing the high and low-side grains on a PCB board and connecting the source of each switch device in the high-side grain with the drain of each switch device in the low-side grain through PCB routing;

[0039] Figure 6 Schematic diagram of the layout and packaging of high-side and low-side power devices in a multi-phase interleaved parallel circuit of Embodiment 2 of the present invention, wherein FIG. (a) is a schematic diagram of the high-side grain M2 metal layout and the M2 surface Cu / Snpillar layout, FIG. (b) is a schematic diagram of the low-side grain M2 metal and the M2 surface Cu / Snpillar layout, FIG. (c) is a schematic diagram of Siinterposer or PCB board wiring and through-holes, FIG. (d) is a top view schematic diagram of the high and low-side grains being respectively placed below and above the Siinterposer or PCB board, and FIG. (e) is a schematic diagram of the AA' and BB' cross-sections in FIG. (d);

[0040] Figure 7This is a schematic diagram of the layout and packaging of high-side and low-side power devices in a multi-phase interleaved parallel circuit of Example 3 of the present invention, wherein Figure (a) is a schematic diagram of the layout of the high-side grain M2 metal and the surface Cu electrode, Figure (b) is a schematic diagram of the layout of the low-side grain M2 metal and the surface Cu electrode, Figure (c) is a top view of the high and low side grains bonded together, and Figure (d) is a schematic diagram of the AA' and BB' cross-sections in Figure (c). DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] For staggered parallel converters, the main reasons for the uneven current between phases are: first, fluctuations in the device manufacturing process lead to inconsistent on-resistance of power devices, tolerance of inductance values, etc.; second, differences in duty cycle of each phase; third, parasitic parameters of each phase branch. For the first reason, the fluctuations in the power device manufacturing process can be solved by integrating multiple phase devices in parallel; for the second reason, in a system using a digital controller, the difference in duty cycle of each phase is small and can be ignored. For the third reason, on the one hand, the parameters of each phase branch need to be designed as symmetrically as possible at the beginning of the design so that the parasitic parameters of each phase are consistent. At the same time, the parasitic parameters introduced need to be reduced as much as possible through PCB layout and packaging.

[0043] The implementation method of the monolithic integration of multi-phase devices in parallel is as follows: the multi-phase device is composed of two monolithic integrated grains, the high-side device of the multi-phase parallel connection is integrated on one grain, and the low-side device of the multi-phase parallel connection is integrated on one grain, which are respectively referred to as the high-side grain and the low-side grain below. Then the high-side grain and the low-side grain are packaged separately, and then the source of the high-side device in parallel of each phase is connected to the drain of the low-side device in parallel of each phase through PCB routing (SW end). Figure 2 As shown, it is a schematic diagram of multi-phase staggered parallel monolithic integration, and the half-bridge structure consists of a high-side die and a low-side die.

[0044] For the above integration method, although the fluctuation of device performance caused by manufacturing process fluctuations between power devices can be reduced, the symmetry of the final PCB layout will also be reduced. The reasons are as follows: First, since multiple switching devices are integrated on the same die, when the electrodes of each switching device are led to the packaging frame, there will be fluctuations in the length of the connection line, especially the connection distance between the source electrode of the high-side device and the drain electrode of the low-side device and the packaging frame. Secondly, taking the DFN package as an example, the electrodes after packaging will be distributed around the package body. When the packaged high-side multi-phase parallel power switch tube integrated chip and the low-side multi-phase parallel power switch tube integrated chip are placed on the PCB board, and the source electrode of the high-side multi-phase power switch tube is connected to the corresponding low-side multi-phase power switch tube drain electrode together using PCB routing, the PCB routing distance will also be inconsistent. Therefore, the parasitic parameters of the gate and SW ends of each phase circuit will fluctuate greatly. The fluctuation of the parasitic parameters of each phase will cause an imbalance in the current between phases, making the current stress of the branch components of each phase different, affecting the stability of the circuit system.

[0045] like Figure 3 As shown, this is a schematic diagram of the simulation results of a four-phase interleaved parallel circuit. Figure 3 (a) is a schematic diagram of the output voltage ripple and the current waveform flowing through each phase inductor when the four-phase parasitic parameters are consistent. The inserted figure on the right side of Figure (a) is a partial enlarged diagram of the waveform in the steady state after the output voltage Vout reaches the rated value. It can be seen that when the four-phase parasitic parameters are consistent, the current flowing through each phase inductor is very consistent and the output voltage ripple is small. Figure (b) shows the output voltage ripple and the current waveform flowing through each phase inductor when the parasitic parameters of the first phase of the four phases are different from those of the other three phases (the first phase parasitic is small, and the other three phase parasitics are large but equal). The inserted figure on the right side of Figure (b) is a partial enlarged diagram of the waveform in the steady state of the output voltage Vout. It can be seen that when the parasitic parameters between phases are inconsistent, the output voltage ripple becomes larger, and the current uniformity flowing through the inductors of each phase becomes worse, especially during the output voltage rising period, the current flowing through the first phase inductor significantly deviates from other phases. The significant fluctuation of this current will trigger the protection circuit, making the circuit unable to work normally.

[0046] The high-side / low-side die that integrates multiple rows and columns of parallel power switch tubes on a single chip adopts conventional QFN / DFN packaging. The distances from the source of each parallel power switch tube on the high side and the drain of each parallel power switch tube on the low side to the package frame are different. Even if the distances are kept consistent, after the die is packaged, the source of each power switch tube in the high-side die and the drain of each power switch tube in the low-side die will be distributed around the package body. When the packaged chip is placed on the PCB board and the source of each high-side power switch tube and the drain of each low-side power switch tube are connected together (SW end), the PCB trace length will be different. Figure 4As shown, there is a PCB layout with 8-phase package routing in 4 rows and 2 columns and the SW ends of the high / low side package chips (the source of each phase switch device of the high-side die and the drain of each phase switch device of the low-side die are connected together and called the SW end) (taking Si-based GaN power devices as an example). Figure 4 Medium, S1 HS 、S2 HS 、S3 HS 、S4 HS 、S5 HS 、S6 HS 、S7 HS 、S8 HS Respectively represent the source of the high-side first to eighth phase switching devices. HS , G2 HS , G3 HS 、G4 HS 、G5 HS 、G6 HS 、G7 HS and G8 HS They represent the gates of the high-side first to eighth phase switch devices. For the high-side die, the two-phase switch devices share a drain, that is, the drain D1 of the high-side first phase switch device and the drain D2 of the second phase switch device are shared. Figure 4 The middle mark is D1 / 2, and the drain D3 of the high-side third-phase switch device and the drain D4 of the fourth-phase switch device are shared. Figure 4 The middle mark is D3 / 4, and the drain D5 of the fifth phase switch device on the high side is shared with the drain D6 of the sixth phase switch device. Figure 4 The middle mark is D5 / 6, the drain D7 of the seventh phase switch device on the high side is shared with the drain D8 of the eighth phase switch device, Figure 4 The middle mark is D7 / 8. S1~S8 represent the first phase to the eighth phase switch devices, S11 represents the first phase high-side switch device, S12 represents the second phase low-side switch device, Si1 represents the i-th phase high-side switch device, Si2 represents the i-th phase low-side switch device, i=1,2,...,8. SW1~SW8 represent the endpoint where the source of the high-side first phase switch device and the drain of the low-side first phase switch device are connected to the endpoint where the source of the high-side eighth phase switch device and the drain of the low-side eighth phase switch device are connected. The drains of all phase switches in the high-side crystal are interconnected and connected to the substrate of the high-side crystal, and then connected to the VIN pin on the PCB board.

[0047] D1 LS 、D2 LS 、D3 LS 、D4 LS 、D5 LS 、D6 LS 、D7 LS 、D8LS Respectively represent the drains of the low-side first to eighth phase switch devices, G1 LS , G2 LS 、G3 LS 、G4 LS 、G5 LS 、G6 LS 、G7 LS 、G8 LS The gate electrodes of the first to eighth phase switching devices of the low side are represented respectively. The switching devices of two phases in the low side die share the source electrode, that is, the source electrode S1 of the first phase switching device of the low side and the source electrode S2 of the second phase switching device are shared. Figure 4 The middle mark is S1 / 2, the source S3 of the low-side third-phase switch device and the source S4 of the fourth-phase switch device are shared. Figure 4 The middle mark is S3 / 4, the source S5 of the low-side fifth-phase switch device and the source S6 of the sixth-phase switch device are shared. Figure 4 The middle mark is S5 / 6, the source S7 of the seventh phase switch device on the low side is shared with the source S8 of the eighth phase switch device, Figure 4 The source electrodes of all phase switches in the low-side die are interconnected and connected to the substrate of the low-side die, and then to the GND pin on the PCB.

[0048] It can be seen that this packaging method can ensure that the connection distance from the same electrode to the packaging frame is consistent. However, when the packaged die is placed on the PCB board, only the parasitic parameters of the 4-phase circuit can be guaranteed to be consistent (phases 5 to 8). The SW end connection wires of the remaining 4 phases (phases 1 to 4) are wound and the spacing distance becomes farther ( Figure 3 Only the SW terminal connections of the 1st and 4th phases are shown), and the parasitics become inconsistent with the 5th to 8th phases.

[0049] according to Figure 4 The layout and packaging method of the monolithic integrated multi-row and multi-column Si-based GaN power device chip with several phases connected in parallel has asymmetry between the phases, resulting in inconsistent parasitic parameters of the phases, causing the problem of uneven current in the multi-phase staggered parallel circuit. In addition, this method will also cause the connection spacing to be too long, the parasitic parameters of each phase are large, and the high-frequency characteristics of the staggered parallel circuit system are affected.

[0050] Therefore, for a circuit system that uses monolithic integration of multi-phase power devices to form an interleaved parallel connection, it is necessary to make reasonable designs in the device layout, packaging process, and PCB layout to improve symmetry, reduce parasitic differences between circuits of each phase, and at the same time reduce parasitic parameters as much as possible to improve the high-frequency characteristics of the circuit system.

[0051] In this regard, the present invention provides a layout method for high-side and low-side power devices in a multi-phase interleaved parallel circuit. For the interleaved parallel circuit composed of monolithically integrated multi-phase parallel devices, symmetrical packaging and PCB design are adopted to maintain the consistency of parasitic parameters of each phase circuit; Siinterposer packaging or PCB packaging scheme, or bonding scheme can also be adopted to stack high-side grains and low-side grains up and down, while maintaining the consistency of parasitic parameters, the parasitic parameters between the high-side and low-side monolithic integrated multi-phase devices are further reduced, the problem of uneven current of each phase caused by inconsistent parasitic parameters of each phase is solved, and the high-frequency characteristics of the interleaved parallel circuit system are improved.

[0052] The present invention provides a layout method for high-side and low-side power devices in a multi-phase interleaved parallel circuit, which mainly includes:

[0053] Distributing the high-side multi-phase power devices and the low-side multi-phase power devices in a row on the high-side die and the low-side die respectively, so that the parasitic parameters of each phase circuit of the multi-phase interleaved parallel circuit remain consistent; or,

[0054] The high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Si interposer solution, a PCB solution, or a bonding solution.

[0055] It is understandable that in order to solve the defects of packaging in the prior art, the arrangement of high-side multi-phase power devices and low-side multi-phase power devices is improved, which is mainly divided into two arrangements.

[0056] In the first arrangement, exemplarily, the high-side multi-phase power device and the low-side multi-phase power device each include a plurality of parallel power devices, and the high-side multi-phase power device and the low-side multi-phase power device are respectively distributed in a row on the high-side die and the low-side die, so that the parasitic parameters of the high-side and low-side power device parts of each phase circuit in the multi-phase interleaved parallel circuit are consistent, including:

[0057] Distributing the high-side multi-phase power devices in a row on the high-side die, and distributing the low-side multi-phase power devices in a row on the low-side die;

[0058] Packaging the high-side multi-phase power device and the low-side multi-phase power device respectively;

[0059] Leading out the source electrodes of each phase power device on the high side to one side of the high side packaging frame and arranging them, and leading out the gate electrodes and drain electrodes of each phase power device on the high side to the other side of the high side packaging frame and arranging them; and leading out the drain electrodes of each phase power device on the low side to one side of the low side packaging frame and arranging them, and leading out the source electrodes and gate electrodes of each phase power device on the low side to the other side of the low side packaging frame and arranging them;

[0060] The package body of the high-side grain and the package body of the low-side grain are placed side by side on a PCB board, and the SW ends of the high-side grain and the low-side grain are electrically connected. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

[0061] It is understandable that the high-side multi-phase power device includes a plurality of power devices connected in parallel, and the low-side multi-phase power device includes a plurality of power devices connected in parallel, wherein the power devices are generally switching devices.

[0062] In this embodiment, the high-side multiphase switch devices and the low-side multiphase switch devices are arranged in a row on the high-side die and the low-side die, respectively. Figure 5 In (a) and (b), Figure (a) shows a top view of the high-side die before packaging, and Figure (b) shows a top view of the low-side die before packaging, wherein the high-side die drains D1 / D2 and D3 / D4 are connected together and connected to the substrate, and the low-side die sources S1 / S2 and S3 / S4 are connected together and connected to the substrate. Among them, the switching devices of each phase in the high-side die are two-phase common drains, that is, D1 and D2 are common drains, D3 and D4 are common drains, and so on. The switching devices of each phase in the low-side die are two-phase common sources, that is, S1 and S2 are common sources, S3 and S4 are common sources, and so on.

[0063] Here, it should be noted that in the traditional solution, the high-side multi-phase switching devices and the low-side multi-phase switching devices are arranged in multiple rows and columns. In this embodiment, the switching devices of all phases on the high side are arranged in one column. Similarly, the switching devices of all phases on the low side are also arranged in one column. The high-side grains and the low-side grains are packaged separately, and the source electrodes of each power device on the high side are led out to one side of the high-side packaging frame, and the gate electrode and drain electrode of each power device are led out on the other side. Similarly, the drain electrode of each power device on the low side is led out to the side of the low-side packaging frame opposite to the side where the source electrode is led out of the high-side packaging frame, and the gate electrode and source electrode are led out to the other side of the low-side packaging frame. See respectively. Figure 5(c), (d), (e) and (f) in the figure, where (c) and (d) are schematic diagrams of the RDL layers deposited on the chip when the high-side die and the low-side die are packaged as Fan-Out, respectively, for leading the chip's PAD to the corresponding package pins, (e) is a schematic diagram of the pins after the high-side die is packaged, and (f) is a schematic diagram of the pins after the low-side die is packaged.

[0064] After the high-side die and the low-side die are packaged, the high-side die and the low-side die packages are placed on the PCB board respectively. The high-side die and the low-side die packages are placed side by side on the PCB board, and the SW ends of the two are electrically connected, such as Figure 5 As shown in (g), the endpoint formed by connecting the source electrode of each phase power device on the high side and the drain electrode of each phase power device on the low side is called the SW terminal. (g) is a schematic diagram of the arrangement of placing high and low side chips on a PCB board and connecting the source SXHS (X=1,2,3...) of each switch device in the high side chip with the drain DXLS (X=1,2,3...) of each switch device in the low side chip through PCB traces.

[0065] In this embodiment, the parallel power tubes integrated with several phases are designed to be arranged in a single row, so that the connection distance from the electrodes of each power switch tube to the package frame can be kept consistent. In addition, the source electrodes of each power tube on the high side are led out to the same side of the package body, and the drain electrodes of each power tube on the low side are led out to the other side of the package body (the side opposite to the high-side source electrode). This can ensure that the connection length of the SW end of each phase circuit is consistent when the two packaged chips are placed on the PCB board, thereby ensuring the consistency of the parasitic parameters of each phase, eliminating the problem of uneven current in each phase caused by inconsistent parasitic parameters, and improving the reliability and stability of the multi-phase staggered parallel circuit. In this embodiment, only the arrangement of the high and low side power devices in parallel of each phase is illustrated, and the arrangement of the inductance and capacitance of each phase is not illustrated. In this embodiment, the SW end electrode can be led to the back of the PCB board by means of a through hole on the PCB board below the SW end, and the inductance and capacitance in each phase can be placed on the back of the PCB board for arrangement.

[0066] In the second arrangement, the high-side die and the low-side die are stacked up and down, and a certain scheme is adopted to connect the high-side multi-phase power device on the high-side die and the low-side multi-phase power device on the low-side die.

[0067] The first connection method of the high-side die and the low-side die is exemplarily to stack the high-side die and the low-side die up and down, and connect the high-side multi-phase power device and the low-side multi-phase power device based on the Siinterposer scheme or the PCB scheme or the bonding scheme, including:

[0068] Distributing the high-side multi-phase power devices in multiple rows and columns on the high-side die, and distributing the low-side multi-phase power devices in multiple rows and columns on the low-side die;

[0069] The high-side die and the low-side die are stacked up and placed on the upper and lower sides of a Siinterposer or a PCB board, and the SW ends of the high-side die and the low-side die are electrically connected in a vertical direction in space. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

[0070] The high-side die and the low-side die are stacked and placed on the upper and lower sides of a Siinterposer or a PCB board, comprising:

[0071] The high-side die and the low-side die are wafer-level packaged, the high-side die is placed on the lower side or upper side of the Si interposer or PCB board, and the low-side die is placed on the upper side or lower side of the Si interposer or PCB board;

[0072] The SW ends between the source electrodes of the power devices of each phase in the high-side die and the drain electrodes of the power devices of each phase in the low-side die are electrically connected through TSVs on the Siinterposer or through holes on the PCB board.

[0073] Specifically, for a chip integrating multi-phase parallel power switch tubes with multiple rows and columns, the high-side die and the low-side die can be packaged at the wafer level, such as Cu / Sn solder joints on the surface of each electrode, and the SW ends of the high-side die and the low-side die are electrically connected together through Siinterposer or PCB board. The high-side die is placed on the lower side of Siinterposer or PCB board, and the low-side die is placed on the upper side of Siinterposer or PCB board; or the high-side die is placed on the upper side of Siinterposer or PCB board, and the low-side die is placed on the lower side of Siinterposer or PCB board.

[0074] The SW ends of the source SX (X=1, 2, 3...) of the switching devices of each phase in the high-side die and the drain DX (X=1, 2, 3...) of the switching devices of each phase in the low-side die are electrically connected together through the TSV on the Siinterposer or the through-hole on the PCB board. The layout of this embodiment can shorten the connection of the SW ends of the high-side die and the low-side die while ensuring the consistency of the parasitic parameters of each phase circuit, thereby reducing the parasitic effect.

[0075] In addition, the gate GXHS (X=1, 2, 3...) of each power device of the high-side die is also connected to the upper surface of the Siinterposer or PCB board through the through-hole of the Si interposer or PCB board. Among them, the drain of each phase power device in the high-side die and the source of each phase power device in the low-side die have been connected together by interconnecting metal, and connected to their respective substrates, connected to the upper surface of the Siinterposer or PCB board through the through-hole of the Si interposer or PCB board, and finally connected to VIN and GND respectively. The wiring on the upper and lower sides of the Siinterposer or PCB board can be exactly the same. Figure 6 As shown, there are 4 rows and 2 columns of 8 phases of high-side and low-side die layout, Siinterposer or PCB board wiring layout and cross-sectional diagram. Among them, the high-side die is placed on the lower side of the Siinterposer or PCB board, and the low-side die is placed on the upper side of the Siinterposer or PCB board.

[0076] in, Figure 6 Figure (a) is a schematic diagram of the layout of the high-side grain M2 metal and the surface Cu / Snpillar; Figure (b) is a schematic diagram of the layout of the low-side grain M2 metal and the surface Cu / Snpillar, Figure (c) is a schematic diagram of the Siinterposer or PCB board wiring and through-holes, Figure (d) is a top-down schematic diagram of the high-side grain and the low-side grain placed under and above the Siinterposer or PCB board respectively, and Figure (e) is a schematic diagram of the AA' and BB' cross-sections in Figure (d), wherein AA' and BB' are cross-sectional views cut along the dotted lines.

[0077] The second connection method of the high-side die and the low-side die is, exemplarily, to stack the high-side die and the low-side die up and down, and connect the high-side die and the low-side die by bonding.

[0078] Exemplarily, the high-side multi-phase power devices are distributed in multiple rows and columns on the high-side grains, and the low-side multi-phase power devices are distributed in multiple rows and columns on the low-side grains; the low-side grains and the high-side grains are stacked up and down, and the SW ends between the low-side grains and the high-side grains are bonded together, and the SW end refers to the endpoint formed by connecting the source electrode of each phase power device on the high side and the drain electrode of each phase power device on the low side.

[0079] Specifically, in the present embodiment, the high-side die and the low-side die are directly bonded together by Die to Wafer (D2W) or Die to Die (D2D). D2W (Die to Wafer) refers to the process of bonding individual chips to a target wafer one by one. The larger the wafer size, the more advantageous and cost-effective it is to use D2W stacking. D2W is usually the main choice for hybrid bonding because it supports different chip sizes, different wafer types, and known good chips. Die-to-Die bonding is the bonding between two chips, which can be equal or unequal in size.

[0080] In this embodiment, the low-side grain can be placed above the high-side grain, or the low-side grain can be placed below the high-side grain, and the low-side grain and the high-side grain can be stacked up and down, wherein the chip area placed below should be larger than the chip area placed above, and the extra chip area around is used to place the lead-out electrode. The SW end between the high-side grain and the low-side grain is bonded together by Cu / Cu bonding or Au / Sn welding, and is led out to the surface of the high-side grain through the RDL of the high-side grain. This layout method can further shorten the connection between the SW end of the high-side grain and the low-side grain while ensuring the consistency of the parasitic parameters of each phase circuit, thereby reducing the parasitic effect.

[0081] In addition, the gate GXHS (X=1, 2, 3…) and drain of each phase power device of the high-side grain are directly led out to the surface of the high-side grain through RDL (Redistribution Layer). After the gate GXLS (X=1, 2, 3…) of each phase power device of the low-side grain is bonded to the reserved point on the high-side grain, it is also led out to the surface of the high-side grain through the RDL of the high-side grain. Among them, the drain of each switching device of the high-side grain and the source of each switching device of the low-side grain have been connected together by interconnecting metal, and connected to their respective substrates, and finally led out to the VIN and GND electrode ports on the surface of the high-side grain. Figure 7 As shown, the high-side die and low-side die layout of 8 switch devices in 4 rows and 2 columns, as well as a top view and a cross-sectional schematic diagram of representative positions after bonding together.

[0082] Figure 7 (a) is a schematic diagram of the layout of the metal and surface Cu electrodes of the high-side grain M2, (b) is a schematic diagram of the layout of the metal and surface Cu electrodes of the low-side grain M2, (c) is a top-down schematic diagram of the high-side grain and the low-side grain bonded together, and (d) is a schematic diagram of the AA' and BB' cross-sections in (c).

[0083] The present invention provides a layout method for high-side and low-side power devices in a multi-phase interleaved parallel circuit. For a multi-phase interleaved parallel circuit formed by a monolithically integrated multi-phase parallel switch tube, a symmetrical package and PCB design are adopted to maintain the consistency of parasitic parameters of each phase circuit; a Siinterposer or PCB solution, or a bonding solution can also be adopted to stack high-side grains and low-side grains, while maintaining the consistency of parasitic parameters, further reducing the parasitic parameters between the high-side and low-side monolithically integrated multi-phase switch tubes, solving the problem of uneven current of each phase caused by inconsistent parasitic parameters of each phase, and improving the high-frequency characteristics of the interleaved parallel circuit system.

[0084] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0085] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0086] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for laying out high-side and low-side power devices in a multi-phase interleaved parallel circuit, characterized in that: The multi-phase interleaved parallel circuit includes a high-side multi-phase power device and a low-side multi-phase power device, the high-side multi-phase power device is integrated on the high-side die, and the low-side multi-phase power device is integrated on the low-side die, and the layout method includes: The high-side multi-phase power device and the low-side multi-phase power device are respectively distributed in a row on the high-side die and the low-side die, so that the parasitic parameters of each phase circuit in the multi-phase interleaved parallel circuit remain consistent; or, The high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Si interposer solution, a PCB solution, or a bonding solution.

2. The layout method according to claim 1, characterized in that: The high-side multi-phase power device and the low-side multi-phase power device each include a plurality of power devices, and the high-side multi-phase power device and the low-side multi-phase power device are respectively distributed in a row on the high-side die and the low-side die, so that the parasitic parameters of each phase circuit in the multi-phase interleaved parallel circuit remain consistent, including: Distributing the high-side multi-phase power devices in a row on the high-side die, and distributing the low-side multi-phase power devices in a row on the low-side die; Packaging the high-side multi-phase power device and the low-side multi-phase power device respectively; Leading out the source electrodes of each phase power device on the high side to one side of the high side packaging frame and arranging them, and leading out the gate electrodes and drain electrodes of each phase power device on the high side to the other side of the high side packaging frame and arranging them; and leading out the drain electrodes of each phase power device on the low side to one side of the low side packaging frame and arranging them, and leading out the source electrodes and gate electrodes of each phase power device on the low side to the other side of the low side packaging frame and arranging them; The package body of the high-side grain and the package body of the low-side grain are placed side by side on a PCB board, and the SW ends of the high-side grain and the low-side grain are electrically connected. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

3. The layout method according to claim 2, characterized in that: One side of the high-side packaging frame where the source electrodes of the high-side power devices of each phase are located is close to one side of the low-side packaging frame where the drain electrodes of the low-side power devices of each phase are located.

4. The layout method according to claim 1, characterized in that: The high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Siinterposer solution, a PCB solution, or a bonding solution, including: Distributing the high-side multi-phase power devices in multiple rows and columns on the high-side die, and distributing the low-side multi-phase power devices in multiple rows and columns on the low-side die; The high-side die and the low-side die are stacked up and placed on the upper and lower sides of a Siinterposer or a PCB board, and the SW ends of the high-side die and the low-side die are electrically connected in a vertical direction in space. The SW end refers to an endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

5. The layout method according to claim 4, characterized in that: The high-side die and the low-side die are stacked and placed on the upper and lower sides of a Siinterposer or a PCB board, comprising: The high-side die and the low-side die are wafer-level packaged, the high-side die is placed on the lower side or upper side of the Si interposer or PCB board, and the low-side die is placed on the upper side or lower side of the Si interposer or PCB board; The SW ends between the source electrodes of the power devices of each phase in the high-side die and the drain electrodes of the power devices of each phase in the low-side die are electrically connected through TSVs on the Siinterposer or through holes on the PCB board.

6. The layout method according to claim 5, characterized in that: The SW ends between the source of each phase power device in the high-side die and the drain of each phase power device in the low-side die are electrically connected through TSV on the Siinterposer or through holes on the PCB board, and further comprising: Connecting the gate of each phase power device in the high-side die to the upper surface of the Siinterposer or the PCB board through the through hole of the Siinterposer or the PCB board; The drain of each phase power device in the high-side grain is connected to its own substrate through interconnecting metal, connected to the upper surface of Siinterposer or PCB board through the through hole of Siinterposer or PCB board, and connected to VIN port; and the source of each phase power device in the low-side grain is connected to its own substrate through interconnecting metal, led out to the area away from the grain stacking interface through the metal routing on the upper surface of Siinterposer or PCB board, and connected to GND port.

7. The layout method according to claim 1, characterized in that: The high-side die and the low-side die are stacked up and down, and the high-side multi-phase power device and the low-side multi-phase power device are connected based on a Siinterposer solution, a PCB solution, or a bonding solution, including: Distributing the high-side multi-phase power devices in multiple rows and columns on the high-side die, and distributing the low-side multi-phase power devices in multiple rows and columns on the low-side die; The low-side grain and the high-side grain are stacked up and down, and the SW ends between the low-side grain and the high-side grain are bonded together, and the SW end refers to the endpoint formed by connecting the source electrode of each phase power device of the high side and the drain electrode of each phase power device of the low side together.

8. The layout method according to claim 7, characterized in that: The SW ends of the low-side die and the high-side die are bonded together, comprising: The SW ends between the low-side crystal grain and the high-side crystal grain are bonded together by Cu / Cu welding or Au / Sn welding.

9. The layout method according to claim 8, characterized in that: The layout method further includes: Leading out the gate and drain of each phase power device of the high-side grain to the surface of the high-side grain, away from the bonding interface area, through RDL, and bonding the gate of each phase power device in the low-side grain to the reserved electrode on the surface of the high-side grain by Cu / Cu welding or Au / Sn welding, leading out to the surface of the high-side grain, and leading out to the surface of the high-side grain, away from the bonding interface area, through the RDL of the high-side grain; The drain of each phase power device in the high-side grain is connected to its own substrate through interconnecting metal, led out to a region away from the bonding interface through RDL, and connected to the VIN port; and the source of each phase power device in the low-side grain is connected to its own substrate through interconnecting metal, the electrode is bonded to the reserved electrode on the surface of the high-side grain through Cu / Cu welding or Au / Sn welding, led to the surface of the high-side grain, and then the electrode is led out to a region away from the bonding interface through RDL, and connected to the GND port.

Images