Optimization method of multi-phase filter based on FPGA (Field Programmable Gate Array)
By optimizing the structure of the multiphase filter in FPGA and using the filter coefficient group rotation to perform filtering calculations, the problem of large resource consumption of FPGA multiplier is solved, and resource saving for the equivalent function of traditional multiphase filters is achieved.
Patent Information
- Application Number
- CN202411370538.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-02-25
AI Technical Summary
When FPGA implements multiphase filters, the multiplier resource consumption is large and it is difficult to meet the needs of signal processing.
By optimizing the structure of the multiphase filter, filtering calculations are performed using the rotation of the filter coefficient group to reduce the use of multiplier. The specific steps include setting a multiphase filter according to bandwidth requirements, derive the filter coefficients, and using two matrices in the FPGA for convolutional operations, completing the filtering and outputting the result.
On the premise of ensuring consistency of input and output rates and filtering effects, the multiplier resources used by the optimized multiphase filter are only 1/M of the traditional multiphase filter, which significantly saves the multiplier resources of the FPGA.
Smart Images
Figure CN119519659A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of signal processing, and in particular relates to an optimization method for a polyphase filter based on FPGA. Background Art
[0002] FPGA has the advantages of fast communication and data processing speed and high parallelism. It has unique advantages in radar, sonar, and image processing. However, due to the limited multiplier resources of FPGA, ordinary filters consume a lot of multiplier resources in filtering processing. Therefore, how to save multiplier resources to meet signal processing requirements has become an important link. Polyphase filtering is widely used in the radar field, has good filtering effect, and is mostly implemented using FPGA. Traditional polyphase filters have lower power consumption than conventional FIR filters, which is also the advantage of polyphase filters, but they have no obvious advantages in terms of multiplier resources. Summary of the invention
[0003] In view of this, the present invention provides an optimization method for a polyphase filter based on FPGA. The present invention designs a polyphase filter with a corresponding bandwidth in FPGA according to requirements, realizes real-time signal output by optimizing the polyphase filter structure, and greatly saves the multiplier resource overhead of FPGA.
[0004] The specific technical scheme of the present invention is:
[0005] An optimization method for a polyphase filter based on FPGA comprises the following steps:
[0006] S101: setting a corresponding polyphase filter according to bandwidth requirements, and deriving filter coefficients of the polyphase filter; wherein the order N of the polyphase filter is an integer multiple of the decimation rate M;
[0007] S102: Perform filtering calculation in the polyphase filter by rotating the filter coefficient groups, specifically:
[0008] S103: setting two matrices with M rows and N / M columns; one matrix is used to store filter coefficients, and the other matrix is used to store signals to be filtered;
[0009] S104: When a signal to be filtered of a clock cycle arrives, a group of N / M order filtering is completed on the signal to be filtered based on the convolution of two matrix rows, and after all M groups are completed, the obtained results are accumulated and output to obtain filtered data.
[0010] Furthermore, the first matrix storing the filter coefficients includes M rows of filter coefficients arranged as follows:
[0011] h_i=a(i+M×r)
[0012] Where a represents the complete filter coefficients; a is divided into M groups, h_i represents a group of filter coefficients; i = 0, 1 ... M-1; r = 0, 1 ... N / M-1; N represents the filter order; M represents the decimation value of the polyphase filter.
[0013] Furthermore, in the second matrix for storing the signal to be filtered, the signal to be filtered is stored from the row array X0 to the row array XM-1 in a circular rotation manner, rotates once per clock, and returns to X0 to continue rotating after reaching XM-1.
[0014] Furthermore, the real-time data of the signal to be filtered is stored in each row array of the matrix in a first-in-first-out manner.
[0015] Furthermore, at the next clock after the first row array of the first matrix is stored, the first row array of the first matrix is convolved with the first row array of the second matrix, and the second row array is stored in the first matrix in a rotational loop; at the next clock, the second row array of the first matrix is convolved with the second row array of the second matrix according to the rotational loop order of the row array of the first matrix and the rotational loop order of the second matrix, and the third row array is stored in the first matrix in a rotational loop manner... After M convolutions, all convolution results are accumulated, and the accumulated results are output as filtered signals.
[0016] Furthermore, the method of convolving the row array of the first matrix with the row array of the second matrix is specifically as follows:
[0017] Convolve X0 with hM-1, convolve X1 with hM-2, and so on, convolve XM-1 with h0.
[0018] The beneficial effects of the present invention are:
[0019] (1) Under the premise of ensuring that the input and output rates and the filtering effect are consistent with those of the traditional polyphase filter, the method of the present invention reduces the multiplier resources of the FPGA when implementing the polyphase filter by establishing an optimized polyphase filter structure. The multiplier resources used by the optimized polyphase filter are 1 / M (M is the decimation value) of the traditional polyphase filter.
[0020] (2) The method of the present invention is easy to implement in engineering and can be applied in the field of signal processing technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0022] Figure 1 is the amplitude-frequency response diagram of the filter;
[0023] Figure 2 is a structural diagram of a conventional polyphase filter, which is used as a comparison object of the present invention;
[0024] Figure 3 A structural diagram of the optimized polyphase filter proposed by the method of the present invention;
[0025] Figure 4 It is the input data graph, which serves as the input for method validation;
[0026] Figure 5 It is the FFT transformation diagram of the input data, which can reflect the data amplitude more intuitively;
[0027] Figure 6 It is the data graph after filtering, which is used as the comparison standard of filtering effect;
[0028] Figure 7 It is the FFT transform diagram of the filtered data;
[0029] Figure 8 This is a data diagram after filtering by the optimized polyphase filter based on FPGA of the method of the present invention, which can be used as a verification of feasibility;
[0030] Fig. 9 The data export diagram after filtering by the optimized polyphase filter based on FPGA;
[0031] Fig.10 This is a resource consumption diagram of an optimized polyphase filter based on FPGA, which can be used as a verification of the effect of the specific implementation method of the present invention. DETAILED DESCRIPTION
[0032] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0033] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0034] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0036] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0037] In one embodiment of the present invention, a method for optimizing a polyphase filter based on FPGA is provided, comprising the following steps:
[0038] S101: setting a corresponding polyphase filter according to bandwidth requirements, and deriving filter coefficients of the polyphase filter; wherein the order N of the polyphase filter is an integer multiple of the decimation rate M;
[0039] S102: Perform filtering calculation in the polyphase filter by rotating the filter coefficient groups, specifically:
[0040] S103: setting two matrices with M rows and N / M columns; one matrix is used to store filter coefficients, and the other matrix is used to store signals to be filtered;
[0041] S104: When a signal to be filtered of a clock cycle arrives, a group of N / M order filtering is completed on the signal to be filtered based on the convolution of two matrix rows, and after all M groups are completed, the obtained results are accumulated and output to obtain filtered data.
[0042] In this embodiment, the first matrix storing the filter coefficients includes M rows of filter coefficients arranged as follows:
[0043] h_i=a(i+M×r)
[0044] Where a represents the complete filter coefficients; a is divided into M groups, h_i represents a group of filter coefficients; i = 0, 1 ... M-1; r = 0, 1 ... N / M-1; N represents the filter order; M represents the decimation value of the polyphase filter.
[0045] In this embodiment, in the second matrix for storing the signal to be filtered, the signal to be filtered is stored from the row array X0 to the row array XM-1 in a circular rotation manner, rotating once per clock, and returning to X0 to continue rotating after reaching XM-1;
[0046] The real-time data of the signal to be filtered is stored in each row array of the matrix in a first-in-first-out manner.
[0047] In this embodiment, at the next clock after the first row array of the first matrix is stored, the first row array of the first matrix is convolved with the first row array of the second matrix, and the second row array is stored in the first matrix in a rotation cycle; at the next clock, according to the rotation cycle order of the row array of the first matrix and the rotation cycle order of the second matrix, the second row array of the first matrix is convolved with the second row array of the second matrix, and the third row array is stored in the first matrix in a rotation cycle manner... After M convolutions, all convolution results are accumulated, and the accumulated results are output as filtered signals.
[0048] In this embodiment, the method of convolving the row array of the first matrix with the row array of the second matrix is specifically as follows:
[0049] Convolve X0 with hM-1, convolve X1 with hM-2, and so on, convolve XM-1 with h0.
[0050] The optimization method of the polyphase filter based on FPGA in this embodiment is specifically implemented in the following steps:
[0051] (I) Determine the low-pass filter coefficients
[0052] Use MATLAB to design a 100Khz bandwidth, 40-order low-pass filter, and save the obtained coefficients in text format for output. The amplitude-frequency response diagram of the filter is as follows: Figure 1 shown.
[0053] 2. Design of optimized polyphase filter
[0054] The traditional polyphase filter requires the same number of multipliers as the normal filter order when implemented, and the equation is as follows:
[0055] h_i=a(i+M×r)
[0056] Where i = 0, 1…M-1; h_i represents a set of filter coefficients (r = 0, 1…N / M-1). N represents the filter order, and M represents the decimation value of the polyphase filter. At the input end, Xn rotates in the direction of the arrow, rotates once per clock, reaches h0(n) and then returns to hM-1(n) to continue rotating, completing a cycle of rotation and outputting a yn, such as Figure 2 shown.
[0057] The optimized polyphase filter uses the filter coefficient group rotation method to replace multiple groups of filters. Figure 3 As shown, two matrices are set (the matrices have M rows and N / M columns), and the coefficients and data are stored respectively. When a clock cycle arrives, a group of N / M order filtering is completed (convolution of two matrix rows). After all M groups are completed, the results are accumulated and output to obtain yn.
[0058] This method can reduce the use of multipliers. Compared with the traditional polyphase filter, the number of multipliers used is 1 / M of the original. Under the condition of limited FPGA resources, the function equivalent to the traditional polyphase filter can be achieved.
[0059] (III) Data simulation verification
[0060] The traditional polyphase filter and the optimized polyphase filter are implemented based on Verilog language, and MATLAB is used to generate simulation waveforms. The MATLAB simulation results and the filtering results after the data read in by Vivado and passed through two sets of filters are compared.
[0061] Use MATLAB to generate superposition signals with 40Khz amplitude of 1023 and 200Khz amplitude of 1023, such as Figure 4 As shown, the generated data is transformed by FFT to obtain the spectrum analysis diagram as shown Figure 5 The generated data is stored in text format for subsequent program data reading.
[0062] Based on MATLAB, the data is passed through a designed low-pass filter with a bandwidth of 100Khz and a coefficient of 40 orders, and finally the filtered data is obtained. The data is decimalized by 1 / 5 to obtain the following results: Figure 6 As shown. Performing FFT on the filtered data shows that the 200Khz signal is significantly attenuated, as shown Figure 7 shown.
[0063] When the decimation rate is 1 / 5, the FPGA uses the optimized polyphase filter structure and imports the same data. The filter simulation results are as follows: Figure 8 As shown, in order to facilitate the comparison of data after simulation, the FPGA simulation data is saved as text and imported into MATLAB and the data graph is drawn as shown in Fig. 9 As shown in Figure 2, it can be seen that the polyphase filters of FPGA and MATLAB have the same filtering effect.
[0064] The ordinary polyphase filter needs 40 multipliers to realize the above filtering function, while the optimized polyphase filter only needs 8 multipliers. Fig.10 The figure shows the resource consumption of the FPGA after implementing the optimized polyphase filter, where eight DSP modules are used as filter coefficient multipliers and one DSP module is used as an accumulator.
[0065] It can be seen that compared with the traditional polyphase filter, the number of multipliers used is 1 / M, which greatly saves FPGA multiplier resources.
[0066] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. An optimization method for a polyphase filter based on FPGA, characterized in that: The following steps are involved: S101: setting a corresponding polyphase filter according to bandwidth requirements, and deriving filter coefficients of the polyphase filter; wherein the order N of the polyphase filter is an integer multiple of the decimation rate M; S102: Perform filtering calculation in the polyphase filter by rotating the filter coefficient groups, specifically: Set two matrices with M rows and N / M columns; one matrix is used to store the coefficients of the filter, and the other matrix is used to store the signal to be filtered; S103: When a signal to be filtered of a clock cycle arrives, a group of N / M order filtering is performed on the signal to be filtered based on the convolution of two matrix rows, and after all M groups are completed, the obtained results are accumulated and output to obtain filtered data.
2. The optimization method of the polyphase filter based on FPGA according to claim 1, characterized in that: The first matrix storing the filter coefficients includes M rows of filter coefficients arranged as follows: h_i=a(i+M×r) Where a represents the complete filter coefficients; a is divided into M groups, h_i represents a group of filter coefficients; i = 0, 1 ... M-1; r = 0, 1 ... N / M-1; N represents the filter order; M represents the decimation value of the polyphase filter.
3. The optimization method of the polyphase filter based on FPGA according to claim 2, characterized in that: In the second matrix for storing the signal to be filtered, the signal to be filtered is stored from the row array X0 to the row array XM-1 in a circular rotation manner, rotating once per clock, and returning to X0 to continue rotating after reaching XM-1.
4. The optimization method of the polyphase filter based on FPGA according to claim 3, characterized in that: The real-time data of the signal to be filtered is stored in each row array of the matrix in a first-in-first-out manner.
5. The optimization method of the polyphase filter based on FPGA according to claim 4, characterized in that: At the next clock after the first row array of the first matrix is stored, the first row array of the first matrix is convolved with the first row array of the second matrix, and the second row array is stored in the first matrix in a rotational loop; at the next clock, the second row array of the first matrix is convolved with the second row array of the second matrix according to the rotational loop order of the row array of the first matrix and the rotational loop order of the second matrix, and the third row array is stored in the first matrix in a rotational loop manner... After M convolutions, all convolution results are accumulated, and the accumulated results are output as filtered signals.
6. The optimization method of the polyphase filter based on FPGA according to claim 5, characterized in that: The method of convolving the row array of the first matrix with the row array of the second matrix is as follows: Convolve X0 with hM-1, convolve X1 with hM-2, and so on, convolve XM-1 with h0.