Method for generating IRIG-B direct current code synchronous second pulse front edge based on single-chip microcomputer

Abstract

The application discloses a method for generating an IRIG-B direct current code synchronous second pulse front edge based on a single-chip microcomputer. max The application can realize the same second pulse 1PPS precision by using a domestic single-chip microcomputer, does not need to use a separate FPGA, and greatly reduces the cost. When the first N max code symbols are received, a timer TIMER2 is enabled to start counting. When the counting value of the timer TIMER2 reaches a maximum value, an overflow interrupt is entered, and the timer TIMER3 is configured as a single pulse mode and enabled after the timer TIMER2 enters the overflow interrupt. After the timer TIMER3 is triggered, a signal second pulse 1PPS output by the timer TIMER3 is synchronized with the rising edge of the frame start code symbol of the next frame after a fixed delay Δ and a programmable delay Delay.

Description

Technical Field

[0001] The present invention belongs to the technical field of time synchronization, and in particular relates to a method for generating a leading edge of an IRIG-B direct current code synchronized second pulse based on a single chip microcomputer. The method is suitable for realizing the generation of an IRIG-B direct current code synchronized second pulse by a single chip microcomputer. Background Art

[0002] Global satellite navigation systems, owing to their extensive signal coverage, high-precision time synchronization, and 24 / 7 service capabilities, have become a crucial technological foundation in numerous fields. IRIG-B (inter-range instrumentation group-B) code generators, which utilize GPS signals to generate 1 PPS (1 pulse per second) signals for time synchronization, are widely used. Currently, 1 PPS signals in IRIG-B codec systems are often implemented using FPGAs (field programmable gate arrays), resulting in high overall implementation costs. Summary of the Invention

[0003] The purpose of the present invention is to address the above-mentioned problems existing in the prior art and to provide a method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer.

[0004] The above-mentioned purpose of the present invention is achieved by the following technical means:

[0005] A method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer comprises the following steps:

[0006] Step S1, initializing timer TIMER1, timer TIMER2, and timer TIMER3, then enabling timer TIMER1, and determining the width of a code element in the IRIG-B DC code by timer TIMER1, thereby determining the type of the code element;

[0007] Step S2: Repeat step S1 to determine the type of the received code element in sequence, use the identified frame start code element as the frame start code element of the current frame IRIG-B DC code, use the rising edge of the frame start code element of the current frame IRIG-B DC code as the frame start position of the current frame IRIG-B DC code, then initialize the number N of received code elements to 1, and continue to receive the remaining code elements in the current frame IRIG-B DC code, and use timer TIMER1 to determine the type of each remaining code element in the current frame IRIG-B DC code in sequence, and increase the number N of received code elements by 1 each time a code element is received;

[0008] Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current framemax After the code element, the timer TIMER2 is enabled to start counting. When the count value of the timer TIMER2 reaches the maximum count value B of the timer TIMER2, an overflow interrupt is triggered. After the timer TIMER2 enters the overflow interrupt, the timer TIMER3 is configured to the single pulse mode and enabled.

[0009] Step S4: Timer TIMER3 is triggered by the rising edge of the last code element of the current frame IRIG-B DC code. After the triggering, after the single pulse trigger fixed delay Δ and the programmable delay Delay, timer TIMER3 outputs a signal second pulse 1PPS synchronized with the rising edge of the frame start code element of the next frame.

[0010] As described above, step S1 specifically includes the following steps:

[0011] Timer TIMER1 interrupts at the rising edge of each IRIG-B DC code element: When the IRIG-B DC code element is at a high level, timer TIMER1 counts; when the IRIG-B DC code element is at a low level, timer TIMER1 stops counting. The code element width is determined based on the count value of timer TIMER1, thereby obtaining the code element type. The counter of timer TIMER1 is then reset, and the next code element is determined.

[0012] The frame start symbol in step S2 as described above is identified by:

[0013] When two consecutive P codes are identified, the second one of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code.

[0014] As described above, the maximum value B of the timer TIMER2 in step S3 is calculated based on the following formula:

[0015] B=(99-N)*T / T2

[0016] Where T is the symbol period of the IRIG-B DC code, T2 is the clock period of timer TIMER2, * is the multiplication sign, and / is the division sign.

[0017] As described above, step S3 specifically includes the following steps:

[0018] Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99;

[0019] Step S3.2, the timer TIMER2 generates an overflow interrupt when the count value is B, configures the timer TIMER3 into a single pulse mode, triggers the single pulse mode by the rising edge of the 100th symbol of the current frame IRIG-B direct current code, and sets the programmable delay Delay of the single pulse mode and the pulse signal width generated.

[0020] The programmable delay Delay in step S4 is calculated according to the following formula:

[0021] Delay=(T-Δ) / T3

[0022] In the formula, Delay is the programmable delay of the timer TIMER3 in the single pulse mode, Δ is the fixed delay of the single-chip microcomputer timer single pulse hardware trigger, T is the symbol period of the IRIG-B direct current code, T3 is the clock period of the timer TIMER3, and / is a division sign.

[0023] Compared with the prior art, the present application has the following beneficial effects:

[0024] The present application realizes the same precision of the second pulse 1PPS by using the domestic single-chip microcomputer (such as UM3243F), and does not need to use a separate FPGA, thereby greatly reducing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A structural schematic diagram of a system for implementing the method of the present application;

[0026] Figure 2 A flowchart of the method of the present application;

[0027] Figure 3 A schematic diagram of the P code, 0 code and 1 code of the IRIG-B direct current code;

[0028] Figure 4 A timing diagram of the single pulse mode of the timer TIMER3 of the present application;

[0029] Figure 5 An implementation schematic diagram of the embodiment 2 of the present application. DETAILED DESCRIPTION

[0030] In order to facilitate those skilled in the art to understand and implement the present application, the present application is further described in detail below in combination with embodiments, and the embodiments described herein are only used to illustrate and explain the present application, and are not a limitation on the present application.

[0031] Embodiment 1:

[0032] An IRIG-B direct current code synchronization second pulse front edge generation method based on a single-chip microcomputer, comprising the following steps:

[0033] Step S1, initialize the timer TIMER1, the timer TIMER2, and the timer TIMER3, then enable the timer TIMER1, judge the symbol width of the IRIG-B direct current code through the timer TIMER1, further judge the type of the symbol, and specifically include the following processes:

[0034] The symbol period T of the IRIG-B direct current code is 10 ms, the IRIG-B direct current code includes three types of symbols, which are P code, 0 code, and 1 code, as shown in the following table, the P code is a symbol signal with a high level pulse width of 8 ms, the 0 code is a symbol signal with a high level pulse width of 2 ms, and the 1 code is a symbol signal with a high level pulse width of 5 ms; the timer TIMER1 can judge the symbol type by counting the symbol width. Figure 3

[0035] Step S1.1, the timer TIMER1 enters an interrupt at the rising edge of each symbol of the IRIG-B direct current code: when the symbol of the IRIG-B direct current code is high, the timer TIMER1 counts, when the symbol of the IRIG-B direct current code is low, the timer TIMER1 stops counting, and the symbol width is judged according to the counting value of the timer TIMER1, so as to obtain the symbol type;

[0036] Step S1.2, reset the counter of the timer TIMER1, and repeat step S1.1 to judge the next symbol.

[0037] Step S2, repeat step S1 to judge the types of the received symbols in turn, the identified frame start symbol is taken as the frame start symbol of the current frame IRIG-B direct current code, the rising edge of the frame start symbol of the current frame IRIG-B direct current code is taken as the frame start position of the current frame IRIG-B direct current code, the number N of received symbols is initialized to 1, then the remaining symbols in the current frame IRIG-B direct current code are continuously received, and the types of the remaining symbols in the current frame IRIG-B direct current code are judged in turn through the timer TIMER1, so as to obtain the binary time information represented by each symbol, and the number N of received symbols is increased by 1 after receiving each symbol.

[0038] Each frame of the IRIG-B direct current code includes 100 symbols, wherein the first symbol and the 100th symbol are P codes, therefore, when two continuous P codes are identified, the former P code in the two continuous P codes is the last symbol of the previous frame IRIG-B direct current code, and the latter P code is the first symbol of the current frame IRIG-B direct current code, that is, the frame start symbol of the current frame IRIG-B direct current code.

[0039] The frame start symbol is identified in the following way: ​

[0040] When two consecutive P codes are identified, the second P code of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code, and the rising edge of the frame start code element of the current frame IRIG-B DC code is used as the frame start position of the current frame IRIG-B DC code.

[0041] Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current frame max After the 99th symbol of the IRIG-B DC code is received, timer TIMER2 is enabled to start counting. When the count value of timer TIMER2 reaches the maximum value B of timer TIMER2 (the 99th symbol of the current frame IRIG-B DC code is received at this time), an overflow interrupt is triggered. After entering the interrupt function, timer TIMER3 is configured to single pulse mode and enabled. The specific steps include:

[0042] Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99.

[0043] In step S3.2, when the count value of timer TIMER2 is B, an overflow interrupt is generated, and timer TIMER3 is configured to single-pulse mode. It is triggered by the rising edge of the 100th code element of the current frame IRIG-B DC code (that is, the last code element of the current frame IRIG-B DC code, P code), and the programmable delay Delay of the single-pulse mode is set to generate the pulse signal width.

[0044] Where B is the maximum value of timer TIMER2, and B satisfies the following formula:

[0045] B= (99-N) *T / T2 (1)

[0046] Wherein, T is the symbol period of the IRIG-B DC code, N is the number of received symbols, T2 is the clock period of timer TIMER2, T2 is a positive integer, * is the multiplication sign, and / is the division sign.

[0047] The programmable delay is based on the following formula:

[0048] Delay=(T-Δ) / T3 (2)

[0049] Wherein, Delay is the programmable delay of the single-shot mode of the timer TIMER3, Δ is the fixed delay of the single-chip timer single-shot hardware trigger, Δ is a constant, Δ is related to the single-chip model, T is the symbol period of the IRIG-B direct current code, T3 is the clock period of the timer TIMER3, / is the division sign.

[0050] The principle of the single-shot mode is shown in Figure 4 The single-shot output is a special case of the compare output mode, which allows the timer TIMER3 to output a programmable width pulse signal after a programmable delay Δ after the occurrence of a set event (in this embodiment, the rising edge of the 100th symbol of the IRIG-B direct current code). Unlike other output modes, the counter will automatically stop before the next update event (update operation or update event) arrives after the counter is reset. Only when TIM_CCR1 and the counter initial value are different, the pulse can be output correctly. When counting up, CNT < TIM_CCR1 <= TIM_ARR is required, and when counting down, TIM_CNT > TIM_CCR1 is required. Figure 4 is that the TI2 input is used as the counter trigger signal, the OCxREF output is low when the counter value is equal to TIM_CCR1, the OCxREF returns to high when the counter reaches TIM_ARR1, and the counter rolls back to 0 and stops counting. Wherein, update event means update operation or update event, CNT means counter value; CCR1 means capture / compare register 1, TIM_CCR1 means the preset value of the capture / compare register 1, when the counter value is equal to TIM_CCR1, the timer enters the interrupt and executes the interrupt program, in this embodiment, CCR1 is used to set the programmable delay Δ, through the set preset value TIM_CCR1, when the counter value is equal to TIM_CCR1, a programmable delay Δ has passed; ARR means automatic reload register, which is used to reset the counter value to the preset initial value, TIM_ARR means the set upper limit of the counter value, when the counter value is equal to TIM_ARR, the counter will be reset to the preset initial value (such as 0); OCxREF means external event clear signal, TI2 is the input capture channel, Tpulse is the pulse width of the single-shot, OC1 refers to output compare channel 1, T Delay That is, the programmable delay Delay.

[0051] Step S4, the timer TIMER3 is triggered by the rising edge of the last P symbol of the current IRIG-B DC code (also the last symbol of the current IRIG-B DC code, the 100th symbol), and outputs a signal second pulse 1PPS synchronized with the rising edge of the frame start symbol of the next frame after a fixed delay Δ and a programmable delay Delay.

[0052] As an implementable manner, the chip model of the MCU is UM3243F, and an external clock stable 10MHz rubidium atomic clock is used as the system clock of the MCU.

[0053] The timer TIMER1 is configured as a 1MHz working clock, and the counting function of the timer TIMER1 is used and configured as an overflow interrupt.

[0054] The timer TIMER2 is configured as a 100MHz working clock, and the counting function of the timer TIMER2 is used and configured as an overflow interrupt.

[0055] The timer TIMER3 is configured as a 200MHz working clock, and the single pulse mode of the timer TIMER3 is used.

[0056] Embodiment 2:

[0057] An IRIG-B DC code synchronous second pulse front edge generation method based on a single-chip microcomputer, comprising the following steps:

[0058] As shown in Figure 1 The encoding and decoding circuit of the IRIG-B DC code used in the embodiment includes a single-chip microcomputer, a 5V-3.3V power conversion circuit, a serial transceiver circuit, an 8-way bus transceiver, and an input and output buffer. The chip model of the single-chip microcomputer used in the embodiment is UM3243F, and an external clock stable 10MHz rubidium atomic clock is used as the system clock of the single-chip microcomputer, which can provide accurate time base for the MCU. The timer TIMER1 of the single-chip microcomputer is a 1MHz working clock, and the counting mode of the timer TIMER1 is used, and the interrupt type is an external interrupt. The timer TIMER2 is configured as a 100MHz working clock, and the counting mode of the timer TIMER2 is used, and the interrupt type is an overflow interrupt. The timer TIMER3 is configured as a 200MHz working clock, and the single pulse mode of the timer TIMER3 is used, and the interrupt type is an external interrupt.

[0059] Since the symbols no longer carry the required time information of year, month, day, hour, minute and second when the number of symbols N>60, in the embodiment, the maximum value N max of the received symbols is set to 68, and when the number of received symbols N is equal to 68, the timer TIMER2 is enabled to start counting.

[0060] The steps S1 and S2 in the embodiment 1 are performed: initializing the timers TIMER1, TIMER2 and TIMER3, enabling the timer TIMER1, judging the type of each symbol in the external signal IRIG-B DC code through the timer TIMER1, determining the frame start position and the frame start symbol of the current frame IRIG-B DC code through detecting two continuous P codes, then continuously receiving the remaining symbols in the current frame IRIG-B DC code, judging the type of each symbol in turn, obtaining the binary time information represented by each symbol, and adding 1 to the number N of the received symbols after receiving each symbol.

[0061] The step S3 in the embodiment 1 is performed: after receiving the 68th symbol of the current frame IRIG-B DC code, enabling the timer TIMER2 to start counting, when the count value of the timer TIMER2 reaches the maximum value B of the timer TIMER2 (at this time, the 99th symbol of the current frame IRIG-B DC code is received), entering the overflow interrupt, after entering the interrupt function, configuring the timer TIMER3 as a single pulse mode and enabling, triggering by the rising edge of the last symbol of the current frame IRIG-B DC code, and setting the programmable delay Delay and the pulse signal width of the single pulse mode.

[0062] The maximum value B of the count value of the timer TIMER2 in the embodiment is:

[0063] B = (99-68) *10*10 -3 / (10 -2 *10 -6 ) = 31000000 (3)

[0064] In the embodiment, the fixed delay Δ of the single-chip microcomputer timer single pulse hardware trigger is 10 ns (nanoseconds), and the programmable delay Delay of the timer TIMER3 in the single pulse mode is set as:

[0065] Delay = (10*10 -3 -10*10 -9 )*(200*10 6 ) = 1999998 (4)

[0066] The step S4 in the embodiment 1 is performed: the single pulse of the timer TIMER3 is triggered by the rising edge of the last P code in the current frame IRIG-B DC code, after the fixed delay Δ and the programmable delay Delay, the second pulse 1PPS synchronized with the rising edge of the frame start symbol in the next frame IRIG-B DC code is output.

[0067] The present invention does not require the use of FPGA when achieving the same high precision. By using this method, a domestically produced single-chip microcomputer with a lower price can be used to replace the expensive FPGA, which will greatly reduce the application cost in large-scale applications.

[0068] It should be noted that the embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A method for generating the leading edge of IRIG-B DC code synchronized second pulse based on a single chip microcomputer, characterized in that: The following steps are involved: Step S1, initializing timer TIMER1, timer TIMER2, and timer TIMER3, then enabling timer TIMER1, and determining the width of a code element in the IRIG-B DC code by timer TIMER1, thereby determining the type of the code element; Step S2: Repeat step S1 to determine the type of the received code element in sequence, use the identified frame start code element as the frame start code element of the current frame IRIG-B DC code, use the rising edge of the frame start code element of the current frame IRIG-B DC code as the frame start position of the current frame IRIG-B DC code, then initialize the number N of received code elements to 1, and continue to receive the remaining code elements in the current frame IRIG-B DC code, and use timer TIMER1 to determine the type of each remaining code element in the current frame IRIG-B DC code in sequence, and increase the number N of received code elements by 1 each time a code element is received; Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current frame max After the code element, the timer TIMER2 is enabled to start counting. When the count value of the timer TIMER2 reaches the maximum count value B of the timer TIMER2, an overflow interrupt is triggered. After the timer TIMER2 enters the overflow interrupt, the timer TIMER3 is configured to the single pulse mode and enabled. Step S4: Timer TIMER3 is triggered by the rising edge of the last code element of the current frame IRIG-B DC code. After the triggering, after the single pulse trigger fixed delay Δ and the programmable delay Delay, timer TIMER3 outputs a signal second pulse 1PPS synchronized with the rising edge of the frame start code element of the next frame.

2. The method for generating the leading edge of the IRIG-B DC code synchronized second pulse based on a single chip microcomputer according to claim 1, characterized in that: The step S1 specifically includes the following steps: Timer TIMER1 interrupts at the rising edge of each IRIG-B DC code element: When the IRIG-B DC code element is at a high level, timer TIMER1 counts; when the IRIG-B DC code element is at a low level, timer TIMER1 stops counting. The code element width is determined based on the count value of timer TIMER1, thereby obtaining the code element type. The counter of timer TIMER1 is then reset, and the next code element is determined.

3. The method for generating the leading edge of the IRIG-B DC code synchronized second pulse based on a single chip microcomputer according to claim 1, characterized in that: The frame start symbol in step S2 is identified by: When two consecutive P codes are identified, the second one of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code.

4. The method for generating the leading edge of the IRIG-B DC code synchronized second pulse based on a single chip microcomputer according to claim 1, characterized in that: The maximum value B of the timer TIMER2 in step S3 is calculated based on the following formula: B=(99-N)*T / T2 Where T is the symbol period of the IRIG-B DC code, T2 is the clock period of timer TIMER2, * is the multiplication sign, and / is the division sign.

5. The method for generating the leading edge of the IRIG-B DC code synchronized second pulse based on a single chip microcomputer according to claim 4, characterized in that: The step S3 specifically includes the following steps: Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99; In step S3.2, when the count value of timer TIMER2 reaches B, an overflow interrupt is generated, and timer TIMER3 is configured to single-pulse mode, triggered by the rising edge of the 100th code element of the current frame IRIG-B DC code. The programmable delay Delay of the single-pulse mode and the generated pulse signal width are set.

6. The method for generating the leading edge of the IRIG-B DC code synchronized second pulse based on a single chip microcomputer according to claim 1, characterized in that: The programmable delay Delay in step S4 is calculated based on the following formula: Delay=(T-Δ) / T3 Where Delay is the programmable delay of timer TIMER3 in single-pulse mode, Δ is the fixed delay of the single-pulse hardware trigger of the microcontroller timer, T is the symbol period of the IRIG-B DC code, T3 is the clock period of timer TIMER3, and / is the division sign.

Images