Frequency source generation method and device
By generating a frequency source by locked clock signal, using the clock source generation unit, the FPGA unit and the frequency source generation unit, the problem of high precision, low phase noise, high stability and fast frequency switching in the prior art is solved, and a higher frequency source performance is achieved.
Patent Information
- Application Number
- CN202411580927.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-25
AI Technical Summary
The existing frequency source design cannot meet the requirements of high accuracy, low phase noise, high stability and fast frequency switching at the same time.
The frequency source is generated by the locked clock signal, and the first and second clock signals are generated by the clock source generation unit, the FPGA unit and the frequency source generation unit. The second clock signal is locked by the first clock signal through the voltage control signal of the FPGA unit. Finally, the frequency source generation unit generates a frequency source based on the locked second clock signal.
Improves the accuracy and stability of the frequency source, reduces phase noise, and achieves low frequency drift and fast frequency switching.
Smart Images
Figure CN119519701A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of frequency source generation, and in particular to a method and device for generating a frequency source. Background Art
[0002] High-performance frequency sources are the heart of electronic equipment such as radar and communications. With the development of radar, electronic countermeasures, communications and other technologies, higher and higher requirements are put forward for frequency synthesizers; these requirements are mainly reflected in indicators such as high precision, low phase noise, high stability and fast frequency switching.
[0003] Currently, the design of frequency sources mainly relies on temperature-compensated crystal oscillators or constant-temperature crystal oscillators as reference sources combined with PLL (phase-locked loop), DDS (direct digital frequency synthesizer) and other technologies, which cannot simultaneously meet the requirements of high precision, low noise, high stability and fast frequency switching. Summary of the invention
[0004] The embodiments of the present application provide a method and device for generating a frequency source, which generates a frequency source by locking a clock signal, so that the generated frequency source is more stable and accurate, thereby solving the technical problems existing in the prior art.
[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.
[0006] According to a first aspect of an embodiment of the present application, a frequency source generation method is implemented by a frequency source generation device, the device including a clock source generation unit, an FPGA unit and a frequency source generation unit, the method including:
[0007] The clock source generating unit generates a first clock signal and a second clock signal;
[0008] The FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal;
[0009] The clock source generating unit causes the second clock signal to be locked by the first clock signal through the voltage control signal;
[0010] The frequency source generating unit generates a frequency source based on the locked second clock signal and the control signal of the FPGA unit.
[0011] In some embodiments of the present application, based on the above solution, the FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal, including:
[0012] The FPGA unit performs frequency division and phase detection processing based on the first clock signal and the second clock signal to generate a PWM signal;
[0013] The PWM signal is subjected to smoothing filtering and direct current amplification processing in sequence to obtain the voltage-controlled signal.
[0014] According to a second aspect of an embodiment of the present application, there is provided a frequency source generating device, comprising: an FPGA unit, a clock source generating unit and a frequency source generating unit;
[0015] The FPGA unit is connected to the clock source generation unit and the frequency source generation unit respectively, and the clock source generation unit is also connected to the frequency source generation unit;
[0016] Wherein, the clock source generation unit generates a first clock signal and a second clock signal, and outputs the first clock signal and the second clock signal to the FPGA unit;
[0017] The FPGA unit divides the two clock signals, performs phase detection on the divided signals to generate a PWM signal and returns the PWM signal to the clock source generation unit as a voltage control input, so that the first clock signal locks the second clock signal;
[0018] The clock source generating unit outputs the locked second clock signal to the frequency source generating unit, and the frequency source generating unit generates a frequency source according to the control signal of the FPGA unit and the locked second clock signal.
[0019] In some embodiments of the present application, based on the aforementioned solution, the clock source generation unit includes: a first clock source generation subunit and a second clock source generation subunit;
[0020] The first clock source generating subunit is connected to the FPGA, generates a first clock signal and transmits it to the FPGA unit;
[0021] The second clock source generating subunit is connected to the FGPA, generates a second clock signal and transmits it to the FPGA unit, and the second clock source generating subunit receives the PWM signal output by the FPGA as a voltage control input;
[0022] The second clock source generating subunit is also connected to the frequency source generating unit, and outputs a locked second clock signal to the frequency source generating unit.
[0023] In some embodiments of the present application, based on the aforementioned scheme, the first clock source generating subunit adopts a CPT atomic clock.
[0024] In some embodiments of the present application, based on the aforementioned solution, the second clock source generation subunit adopts a constant temperature crystal oscillator.
[0025] In some embodiments of the present application, based on the aforementioned scheme, a signal processing unit is further provided between the second clock source generating subunit and the FPGA unit, and the signal processing unit is used to perform smoothing filtering and DC amplification processing on the PWM signal.
[0026] In some embodiments of the present application, based on the aforementioned solution, the frequency source generation unit includes: a first frequency source generation subunit and a second frequency source generation subunit;
[0027] The first frequency generating subunit is connected to the FPGA unit, the clock source generating unit and the second frequency source generating subunit respectively, receives the first control signal output by the FPGA and the locked second clock signal output by the clock source generating unit, and generates a system clock based on the first control signal and the locked second clock signal and transmits it to the second frequency source generating subunit;
[0028] The second frequency source generating subunit is also connected to the FPGA unit, receives the second control signal output by the FPGA and the system clock output by the first frequency source generating subunit, and generates a frequency source based on the second control signal and the system clock.
[0029] In some embodiments of the present application, based on the aforementioned solution, the first frequency source generating subunit adopts a phase-locked loop.
[0030] In some embodiments of the present application, based on the aforementioned solution, the second frequency source generating subunit adopts a direct digital frequency synthesizer.
[0031] The technical solution of the present application generates a frequency source by a second clock signal locked by a first clock signal, so that the generated frequency source has greatly improved accuracy and stability, and also has excellent performance in phase noise, with lower frequency drift and fast frequency switching.
[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0034] Figure 1A schematic flow chart of a frequency source generating method according to an embodiment of the present application is shown;
[0035] Figure 2 A schematic structural diagram of a frequency source generating device according to an embodiment of the present application is shown;
[0036] Figure 3 A schematic diagram showing the principle of locking a CPT atomic clock to a constant temperature crystal oscillator according to an embodiment of the present application is shown;
[0037] Figure 4 A schematic diagram of a digital phase detection principle according to an embodiment of the present application is shown;
[0038] Figure 5 A schematic diagram of two input signals with a phase difference Δφ according to an embodiment of the present application is shown;
[0039] Figure 6 A schematic diagram showing the phase difference between the output and input of a digital phase detector according to an embodiment of the present application is shown;
[0040] Figure 7 A schematic diagram showing the principles of smoothing filtering and DC amplification processing according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.
[0042] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.
[0043] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.
[0044] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.
[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those shown or described.
[0046] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0047] Some embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.
[0048] In order to solve the technical problems existing in the prior art, an embodiment of the present application provides a frequency source generating device to generate a high-performance frequency source.
[0049] See also Figure 1 , shows a flow chart of a frequency source generating method according to an embodiment of the present application.
[0050] like Figure 1 As shown, a frequency source generating method is demonstrated. Specifically, the method is implemented by a frequency source generating device, the device includes a clock source generating unit, an FPGA unit and a frequency source generating unit, and the method includes steps S100 to S400.
[0051] refer to Figure 1 , step S100, a clock source generating unit generates a first clock signal and a second clock signal.
[0052] It should be noted that the first clock signal and the second clock signal each have excellent indicators. For example, the excellent indicators of the first clock signal are high accuracy, good long-term stability, and small frequency drift; the excellent indicators of the second clock signal are better performance in short-term stability and phase noise than the first clock signal.
[0053] Continue to refer Figure 1 , step S200, the FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal.
[0054] It can be understood that the generated voltage control signal is used as the voltage control input of the clock source generating unit so that the second clock signal is locked by the first clock signal.
[0055] In some feasible embodiments, based on the above solution, the FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal, including:
[0056] The FPGA unit performs frequency division and phase detection processing based on the first clock signal and the second clock signal to generate a PWM signal;
[0057] The PWM signal is subjected to smoothing filtering and direct current amplification processing in sequence to obtain the voltage-controlled signal.
[0058] Continue to refer Figure 1 , step S300, the clock source generating unit causes the second clock signal to be locked by the first clock signal through the voltage control signal.
[0059] It should be noted that the locked second clock signal has the advantages of the first clock signal.
[0060] Continue to refer Figure 1 , step S400, the frequency source generating unit generates a frequency source based on the locked second clock signal and the control signal of the FPGA unit.
[0061] The stability and accuracy of the frequency source finally generated follow the index of the second clock signal after being locked. Therefore, according to actual needs, a clock source generating device that meets the index requirements can be selected to generate the first clock signal and the second clock signal, and then the above steps can be used to make the second clock signal have all the excellent indexes after being locked, so that the frequency source finally generated meets the requirements.
[0062] Based on the same inventive concept, an embodiment of the present application also provides a frequency source generating device.
[0063] See also Figure 2 , shows a schematic structural diagram of a frequency source generating device according to an embodiment of the present application.
[0064] like Figure 2 As shown, a frequency source generating device is shown, including: an FPGA unit, a clock source generating unit and a frequency source generating unit;
[0065] The FPGA unit is connected to the clock source generation unit and the frequency source generation unit respectively, and the clock source generation unit is also connected to the frequency source generation unit;
[0066] Wherein, the clock source generation unit generates a first clock signal and a second clock signal, and outputs the first clock signal and the second clock signal to the FPGA unit;
[0067] The FPGA unit divides the two clock signals, performs phase detection on the divided signals to generate a PWM signal and returns the PWM signal to the clock source generation unit as a voltage control input, so that the first clock signal locks the second clock signal;
[0068] The clock source generating unit outputs the locked second clock signal to the frequency source generating unit, and the frequency source generating unit generates a frequency source according to the control signal of the FPGA unit and the locked second clock signal.
[0069] It should be noted that the clock source generation unit and the FPGA unit form a clock signal locking loop, so that the second clock signal is locked by the first clock signal. In addition to its own characteristics, the locked second clock signal also has the characteristics of the first clock signal.
[0070] It should be noted that if Figure 2 As shown, the FPGA unit has a built-in digital phase detector, through which phase detection processing of the signal is implemented.
[0071] Continue to see Figure 2 , In some feasible embodiments, based on the aforementioned solution, the clock source generation unit includes: a first clock source generation subunit and a second clock source generation subunit;
[0072] The first clock source generating subunit is connected to the FPGA, generates a first clock signal and transmits it to the FPGA unit;
[0073] The second clock source generating subunit is connected to the FGPA, generates a second clock signal and transmits it to the FPGA unit, and the second clock source generating subunit receives the PWM signal output by the FPGA as a voltage control input;
[0074] The second clock source generating subunit is also connected to the frequency source generating unit, and outputs a locked second clock signal to the frequency source generating unit.
[0075] It should be noted that the first clock source generating subunit and the second clock source generating subunit are essentially different, and each has different advantages and disadvantages. In this way, the first clock source generating subunit, the second clock source generating subunit and the FPGA unit cooperate with each other to make the generated second clock signal locked by the first clock signal, that is, the second clock signal has the advantages of the first clock signal while having its own advantages.
[0076] Continue to see Figure 2 In some feasible embodiments, based on the above scheme, a signal processing unit is further provided between the second clock source generating subunit and the FPGA unit, and the signal processing unit is used to perform smoothing filtering and DC amplification processing on the PWM signal.
[0077] It should be noted that if Figure 2 As shown, the first clock source generating subunit is connected to the DIV / N port of the FPGA unit, and outputs the first clock signal to the FPGA unit; the second clock source generating subunit is connected to the DIV / M port of the FPGA unit, and outputs the second clock signal to the FPGA unit; the FPGA unit generates a PWM signal after frequency division and phase detection of the first clock signal and the second clock signal, and the output interface of the FPGA unit is connected to the input interface of the second clock source generating subunit, and the PWM signal generated by the FPGA unit is input to the second clock source generating subunit as a voltage control after smoothing filtering and DC amplification processing, so that the second clock source generating subunit generates a second clock signal locked by the first clock signal.
[0078] Exemplarily, the first clock source generating subunit adopts a CPT atomic clock, and the second clock source generating subunit adopts a constant temperature crystal oscillator.
[0079] It should be noted that CPT atomic clocks and oven-controlled crystal oscillators, as two commonly used clock sources, have their own advantages and disadvantages. The main features of CPT atomic clocks are high accuracy, good long-term stability, and small frequency drift, but their phase noise and short-term stability are slightly worse than those of oven-controlled crystal oscillators. Oven-controlled crystal oscillators are not as good as atomic clocks in terms of accuracy, long-term stability, frequency drift, etc., but oven-controlled crystal oscillators have better performance in short-term stability and phase noise.
[0080] The current mainstream CPT atomic clock indicators are: frequency accuracy: ≤±5E-11; frequency stability: ≤3E-10 / s, ≤1E-10 / 10s, ≤3E-11 / 100s; phase noise: ≤-90dBc / Hz@10Hz, ≤-120dBc / Hz@100Hz, ≤-140dBc / Hz@1KHz, ≤-145dBc / Hz@10KHz.
[0081] The constant temperature crystal oscillator indicators can generally meet the following requirements: frequency accuracy: ≤±1E-8; frequency stability: ≤5E-11 / s; phase noise: ≤-95dBc / Hz@10Hz, ≤-125dBc / Hz@100Hz, ≤-160dBc / Hz@1KHz, ≤-170dBc / Hz@10KHz.
[0082] In this embodiment, the CPT atomic clock is used to lock the voltage-controlled constant temperature crystal oscillator, so that the output frequency accuracy, long-term stability and drift of the constant temperature crystal oscillator follow the CPT atomic clock. This allows the frequency of the second clock signal output by the constant temperature crystal oscillator to maintain its own excellent indicators of short-term stability and phase noise, and also have the high accuracy, high stability and low frequency drift of the CPT atomic clock. The principle block diagram is as follows: Figure 3 In this embodiment, the output frequency of the oven-controlled crystal oscillator is ultimately maintained as follows: accuracy: ≤±5E-11; stability: ≤5E-11 / s, ≤1E-10 / 10s, ≤3E-11 / 100s; phase noise: ≤-95dBc / Hz@10Hz, ≤-125dBc / Hz@100Hz, ≤-160dBc / Hz@1KHz, ≤-170dBc / Hz@10KHz.
[0083] Continue to see Figure 2 , In some feasible embodiments, based on the aforementioned solution, the frequency source generating unit includes: a first frequency source generating subunit and a second frequency source generating subunit;
[0084] The first frequency generating subunit is connected to the FPGA unit, the clock source generating unit and the second frequency source generating subunit respectively, receives the first control signal output by the FPGA and the locked second clock signal output by the clock source generating unit, and generates a system clock based on the first control signal and the locked second clock signal and transmits it to the second frequency source generating subunit;
[0085] The second frequency source generating subunit is also connected to the FPGA unit, receives the second control signal output by the FPGA and the system clock output by the first frequency source generating subunit, and generates a frequency source based on the second control signal and the system clock.
[0086] It should be noted that if Figure 2 As shown, the first frequency generating subunit is connected to a control interface of the FPGA unit to receive a first control signal sent by the FPGA unit; the second frequency generating subunit is connected to another control interface of the FPGA unit to receive a second control signal sent by the FPGA unit.
[0087] Exemplarily, the first frequency source generating subunit adopts a phase-locked loop, and the second frequency source generating subunit adopts a direct digital frequency synthesizer.
[0088] It should be noted that the general frequency source generation unit is directly generated by a phase-locked loop or a direct digital frequency synthesizer. If the phase-locked loop is used alone, the frequency switching time is relatively long (20μS~50μS) and cannot meet the needs of fast frequency hopping. If the direct digital frequency synthesizer is used alone, although the corresponding frequency can be generated, the output frequency of the phase-locked loop integrated in the direct digital frequency synthesizer is relatively low, which will affect the quality of the signal generated by the direct digital frequency synthesizer.
[0089] Therefore, in this example, a frequency source generation unit is composed of a phase-locked loop and a direct digital frequency synthesizer. The phase-locked loop can output spurious noise with a wider frequency range and excellent frequency to generate the system clock required by the direct digital frequency synthesizer. The direct digital frequency synthesizer configures the corresponding frequency points through the FPGA unit, so that the frequency source has good indicators and fast frequency response time (within 1μS).
[0090] Below, a working principle of the technical solution of this application is provided:
[0091] The FPGA unit divides the first clock signal output by the first clock source generation subunit and the second clock signal output by the second clock source generation subunit into equal frequencies, and then performs phase detection processing on the frequencies obtained by dividing the two groups. Figures 4 to 6 As shown, Figure 4 The digital phase detector circuit generates a PWM wave proportional to the phase difference between two input signals. Figure 5 The two input signals with a phase difference of Δφ are shown in FIG. 1 . The phase detector generates a PWM duty cycle proportional to Δφ according to the phase difference, as shown in FIG. Figure 6 The PWM wave output by the phase detector is smoothed and filtered, and then amplified by DC, and then acts on the voltage control end of the constant temperature crystal oscillator. The implementation principle is as follows: Figure 7 shown.
[0092] After the second clock signal output by the second clock source generating subunit is locked, the long-term stability and frequency accuracy of the second clock signal follow the first clock signal; the locked second clock signal serves as the clock of the first frequency generating subunit, and the first frequency generating subunit generates the system clock required by the second frequency generating subunit. The first frequency generating subunit and the second frequency generating subunit are configured into the final output frequency source through the FPGA unit. Since the clock sources of the first frequency generating subunit and the second frequency generating subunit are both generated by the second clock source generating subunit, the stability and accuracy of the final frequency source follow the indicators of the first clock source generating subunit and the second clock source generating subunit.
[0093] It should be noted that, in the present technical solution, the first clock source generating subunit may be a CPT atomic clock, and the second clock source generating subunit may be a constant temperature crystal oscillator; however, the first clock source generating subunit may also be other devices that can generate high-precision frequency-standard clock signals, and the second clock source generating subunit may also be other devices that can realize low-noise crystal oscillators.
[0094] To sum up, the frequency source generated by the technical solution provided in the embodiment of the present application has the characteristics of high frequency accuracy, high frequency stability, low frequency drift, excellent phase noise and fast frequency switching; the technical solution provided in the embodiment of the present application provides an implementation path for fields with high requirements on frequency source indicators.
[0095] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. It should be understood that the present application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A frequency source generation method, implemented by a frequency source generation device, the device comprising a clock source generation unit, an FPGA unit and a frequency source generation unit, characterized in that: The method comprises: The clock source generating unit generates a first clock signal and a second clock signal; The FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal; The clock source generating unit causes the second clock signal to be locked by the first clock signal through the voltage control signal; The frequency source generating unit generates a frequency source based on the locked second clock signal and the control signal of the FPGA unit.
2. The method according to claim 1, characterized in that The FPGA unit generates a voltage control signal based on the first clock signal and the second clock signal, including: The FPGA unit performs frequency division and phase detection processing based on the first clock signal and the second clock signal to generate a PWM signal; The PWM signal is subjected to smoothing filtering and direct current amplification processing in sequence to obtain the voltage-controlled signal.
3. A frequency source generating device, applied to the method according to any one of claims 1 to 2, characterized in that: include: FPGA unit, clock source generation unit and frequency source generation unit; The FPGA unit is connected to the clock source generation unit and the frequency source generation unit respectively, and the clock source generation unit is also connected to the frequency source generation unit; Wherein, the clock source generation unit generates a first clock signal and a second clock signal, and outputs the first clock signal and the second clock signal to the FPGA unit; The FPGA unit divides the two clock signals, performs phase detection on the divided signals to generate a PWM signal and returns the PWM signal to the clock source generation unit as a voltage control input, so that the second clock signal is locked by the first clock signal; The clock source generating unit outputs the locked second clock signal to the frequency source generating unit, and the frequency source generating unit generates a frequency source according to the control signal of the FPGA unit and the locked second clock signal.
4. The device according to claim 1, characterized in that The clock source generating unit comprises: a first clock source generating subunit and a second clock source generating subunit; The first clock source generating subunit is connected to the FPGA, generates a first clock signal and transmits it to the FPGA unit; The second clock source generating subunit is connected to the FGPA, generates a second clock signal and transmits it to the FPGA unit, and the second clock source generating subunit receives the PWM signal output by the FPGA as a voltage control input; The second clock source generating subunit is also connected to the frequency source generating unit, and outputs a locked second clock signal to the frequency source generating unit.
5. The device according to claim 4, characterized in that The first clock source generating subunit adopts a CPT atomic clock.
6. The device according to claim 4, characterized in that The second clock source generation subunit adopts a constant temperature crystal oscillator.
7. The device according to claim 4, characterized in that A signal processing unit is further provided between the second clock source generating subunit and the FPGA unit, and the signal processing unit is used for performing smoothing filtering and DC amplification processing on the PWM signal.
8. The device according to any one of claims 3 to 7, characterized in that: The frequency source generating unit comprises: a first frequency source generating subunit and a second frequency source generating subunit; The first frequency generating subunit is connected to the FPGA unit, the clock source generating unit and the second frequency source generating subunit respectively, receives the first control signal output by the FPGA and the locked second clock signal output by the clock source generating unit, and generates a system clock based on the first control signal and the locked second clock signal and transmits it to the second frequency source generating subunit; The second frequency source generating subunit is also connected to the FPGA unit, receives the second control signal output by the FPGA and the system clock output by the first frequency source generating subunit, and generates a frequency source based on the second control signal and the system clock.
9. The device according to claim 8, characterized in that The first frequency source generating subunit adopts a phase-locked loop.
10. The device according to claim 8, characterized in that The second frequency source generating subunit adopts a direct digital frequency synthesizer.