Inbound signal extraction circuit and synchronous bidirectional transceiver

Abstract

The invention provides an inbound signal extraction circuit and a synchronous bidirectional transceiver. The inbound signal extraction circuit is characterized in that an input end of a first driving module accesses an outbound signal; the first equalization module is connected between the working voltage and the output end of the first driving module, the first end of the second equalization module is connected with the output end of the first driving module, and the third equalization module is connected between the working voltage and the second end of the second equalization module. The first equalization module, the second equalization module and the third equalization module are used for equalizing the voltage and time sequence allowance of the outbound signal and the inbound signal; the input end of the second driving module is connected with the output end of the first driving module and the second end of the second balancing module, a first signal is generated, and the inbound signal is extracted based on the separation operation of the signal of the second end of the second balancing module and the first signal. According to the method, the consistency of voltage amplitude and phase can be maintained to the maximum extent, enough voltage and time sequence allowance are ensured, the signal transmission rate is improved, power consumption is saved, and the method has wide applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to an inbound signal extraction circuit and a synchronous bidirectional transceiver. Background Art

[0002] In a link with bidirectional signal transmission, for example, a communication link between processors in a server, it is extremely advantageous to simultaneously transmit signals in both directions, because the same transmission link is usually used for data transmission and data reception, and compared with a unidirectional transmission link, bidirectional transmission achieves twice the signal transmission rate. In a bidirectional transmission link, a hybrid circuit is usually required to separate the inbound signal from the signal at the receiving end, because the signal at the receiving end is a superposition of the inbound signal and the outbound signal, and can be separated by subtracting the outbound signal component from the signal at the receiving end. However, due to errors such as voltage amplitude and phase inconsistency between the mirror copy signal introduced by the existing hybrid circuit and the main driver, the voltage and timing margin are reduced, which in turn limits the signal transmission rate, thereby making the separated inbound signal inaccurate, which restricts the transmission quality of the communication link.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an inbound signal extraction circuit and a synchronous bidirectional transceiver to solve the problem in the prior art that it is difficult to separate the inbound signal from the bidirectional transmission link.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides an inbound signal extraction circuit, which is arranged on a bidirectional link, and both the outbound signal and the inbound signal are transmitted on the bidirectional link, characterized in that the inbound signal extraction circuit at least includes: a first driving module, a second driving module, a first equalizing module, a second equalizing module and a third equalizing module, wherein:

[0006] The input end of the first driving module is connected to the outbound signal; the first equalizing module is connected between the working voltage and the output end of the first driving module, the first end of the second equalizing module is connected to the output end of the first driving module, and the third equalizing module is connected between the working voltage and the second end of the second equalizing module. The first equalizing module, the second equalizing module and the third equalizing module are used to equalize the voltage and timing margin of the outbound signal and the inbound signal; the input end of the second driving module is connected to the output end of the first driving module and the second end of the second equalizing module to generate a first signal, and the inbound signal is extracted based on the separation operation of the signal at the second end of the second equalizing module and the first signal.

[0007] Optionally, the first driving module includes: a first NMOS tube, a second NMOS tube and a first current source, wherein: the gates of the first NMOS tube and the second NMOS tube are connected to the outbound signal, the source of the first NMOS tube is connected to the source of the second NMOS tube; and the first current source is connected between the source of the first NMOS tube and a reference ground.

[0008] Optionally, the first balancing module includes a first resistor and a second resistor, wherein the first resistor and the second resistor are both connected between a working voltage and an output terminal of the first driving module.

[0009] Optionally, the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0010] Optionally, the second balancing module includes a third resistor and a fourth resistor, wherein a first end of the third resistor and a first end of the fourth resistor are both connected to the output end of the first driving module.

[0011] Optionally, the resistance value of the third resistor is equal to the resistance value of the fourth resistor.

[0012] Optionally, the third balancing module includes a fifth resistor and a sixth resistor, wherein the fifth resistor is connected between the operating voltage and the second end of the fourth resistor; and the sixth resistor is connected between the operating voltage and the second end of the third resistor.

[0013] Optionally, the resistance value of the fifth resistor is equal to the resistance value of the sixth resistor.

[0014] Optionally, the fourth resistor is connected in series with the first resistor to form a first series branch, the first series branch is connected in parallel with the fifth resistor to form a first parallel branch, and the resistance value of the first parallel branch is equal to the characteristic impedance value of the bidirectional link; the third resistor is connected in series with the second resistor to form a second series branch, the second series branch is connected in parallel with the sixth resistor to form a second parallel branch, and the resistance value of the second parallel branch is equal to the characteristic impedance value of the bidirectional link.

[0015] Optionally, the second driving module includes: a first unit, a second unit, a seventh resistor and an eighth resistor, wherein: the first end of the seventh resistor and the first end of the eighth resistor are both connected to the working voltage; the first unit is connected between the output end of the first driving module and the second end of the seventh resistor and the second end of the eighth resistor; the second unit is connected between the second end of the second balancing module and the second end of the seventh resistor and the second end of the eighth resistor.

[0016] Optionally, the first unit includes: a third NMOS tube, a fourth NMOS tube and a second current source, wherein: the drain of the third NMOS tube is connected to the second end of the eighth resistor, the drain of the fourth NMOS tube is connected to the second end of the seventh resistor, the gate of the third NMOS tube and the gate of the fourth NMOS tube are both connected to the output end of the first driving module, and the source of the third NMOS tube is connected to the source of the fourth NMOS tube; the second current source is connected between the source of the third NMOS tube and the reference ground.

[0017] Optionally, the second unit includes: a fifth NMOS tube, a sixth NMOS tube and a third current source, wherein: the drain of the fifth NMOS tube is connected to the second end of the seventh resistor, the drain of the sixth NMOS tube is connected to the second end of the eighth resistor, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are both connected to the second end of the second equalization module, and the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube; the third current source is connected between the source of the fifth NMOS tube and the reference ground.

[0018] Optionally, the resistance value of the seventh resistor is equal to the resistance value of the eighth resistor.

[0019] To achieve the above-mentioned object and other related objects, the present invention provides a synchronous bidirectional transceiver, and the synchronous bidirectional transceiver includes the inbound signal extraction circuit.

[0020] As described above, an inbound signal extraction circuit and a synchronous bidirectional transceiver of the present invention have the following beneficial effects:

[0021] The inbound signal extraction circuit and synchronous bidirectional transceiver of the present invention can maintain the consistency of voltage amplitude and phase to the maximum extent, ensure sufficient voltage and timing margin, improve signal transmission rate and save power consumption, and have wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram showing an exemplary unidirectional transmission link and a simultaneous bidirectional transmission link according to the present invention.

[0023] Figure 2 It is a schematic diagram showing the working principle of separating the inbound signal from the signal at the receiving end of the present invention.

[0024] Figure 3 FIG. 4 is a schematic diagram showing an exemplary mirror hybrid circuit of the present invention.

[0025] Figure 4 It is a schematic diagram showing the structure of the inbound signal extraction circuit of the present invention.

[0026] Figure 5 Shown is a schematic diagram of the framework of the inbound signal extraction circuit of the present invention.

[0027] Figure 6 Shown is a schematic diagram of a bidirectional link based on an inbound signal extraction circuit of the present invention.

[0028] Description of Reference Numerals

[0029] 1Inbound signal extraction circuit

[0030] 11First driver module

[0031] 12 Second driver module

[0032] 121 Unit 1

[0033] 122 Unit 2

[0034] 13. First equalization module

[0035] 14 Second equalization module

[0036] 15Third Equalization Module DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. The illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] Figure 1 A unidirectional transmission link and a bidirectional transmission link are shown, where (a) represents a unidirectional transmission link and (b) represents a bidirectional transmission link. Figure 1 As shown in (a), the transmitter Tx of a unidirectional transmission link can only send signals in one direction, and the receiver Rx can only receive signals in one direction. Therefore, a separate channel must be set for the transmitter Tx and a separate channel must be set for the receiver Rx in a chip to avoid signal conflicts. Although the reliability of the unidirectional transmission link is guaranteed, the signal transmission rate is greatly reduced.

[0040] like Figure 1 As shown in (b), the bidirectional transmission link adopts a hybrid circuit form, and both endpoints ① and ② are superimposed with inbound signals and outbound signals. Compared with the unidirectional transmission link, the signal transmission rate of the bidirectional transmission link is greatly enhanced, and its transmission rate is equivalent to twice that of the unidirectional transmission link. Therefore, if the inbound signal is extracted from endpoint ① or endpoint ②, it is necessary to separate the outbound signal from the signal of endpoint ① or endpoint ②, and it is also necessary to reduce the error caused by the inconsistency of the voltage amplitude and phase between the inbound signal and the outbound signal to avoid the decline of the signal transmission rate.

[0041] Figure 2 shows how the incoming signal is separated from the receiving signal, and Figure 3 The hybrid circuit used for the separation operation is shown, and the architecture of this hybrid circuit is also called a replica hybrid circuit. Figure 2 As shown in (a), V represents the signal actually seen by the receiving end, V r Indicates inbound signal, V t represents an outbound signal, then V = V t +V r ;like Figure 2 As shown in (b), step 1 represents the outbound signal V t Perform mirror copying. Step 2 means subtracting the outbound signal V from the signal V actually seen by the receiving end. t The mirror signal is used to obtain the inbound signal Vr .

[0042] like Figure 3 As shown, the hybrid circuit of the replica signal generates an outbound signal V by introducing a mirror driver (replica driver) that is identical to the main driver. t The same image signal V t ', subtract V from V t 'Then get the inbound signal V r However, in the mirror hybrid circuit, due to the mirror signal V t 'With the outbound signal V generated by the main driver t There is an error (voltage amplitude and phase inconsistency), resulting in the image signal V t ' reduces the voltage and timing margin, thus limiting the signal transmission rate, making the calculated inbound signal V r Inaccurate.

[0043] Therefore, the present invention provides an inbound signal extraction circuit and a synchronous bidirectional transceiver, which are specifically implemented as follows:

[0044] like Figure 4 As shown, this embodiment provides an inbound signal extraction circuit 1, which is set on a bidirectional link. Both the outbound signal and the inbound signal are transmitted on the bidirectional link. The inbound signal extraction circuit 1 includes: a first driving module 11, a second driving module 12, a first equalizing module 13, a second equalizing module 14 and a third equalizing module 15, wherein:

[0045] The input end of the first driving module 11 receives the outbound signal V TX1 The first balancing module 13 is connected between the working voltage VDD and the output end of the first driving module 11, the first end of the second balancing module 14 is connected to the output end of the first driving module 11, and the third balancing module 15 is connected between the working voltage VDD and the second end of the second balancing module 14. The first balancing module 13, the second balancing module 14 and the third balancing module 15 are used to balance the voltage and timing margin of the outbound signal and the inbound signal; the input end of the second driving module 12 is connected to the output end of the first driving module 11 and the second end of the second balancing module 14 to generate a first signal, and extract the inbound and outbound signals based on the separation operation of the signal at the second end of the second balancing module 14 and the first signal.

[0046] Specifically, as an example, Figure 4As shown, the first driving module 11 includes: a first NMOS transistor MN1, a second NMOS transistor MN2 and a first current source I1, wherein: the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the outbound signal, and the source of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2; the first current source I1 is connected between the source of the first NMOS transistor MN1 and the reference ground, and the first current source I1 is connected between the source of the second NMOS transistor MN2 and the reference ground.

[0047] The first equalization module 13 includes a first resistor R1 and a second resistor R2, wherein the first resistor R1 and the second resistor R2 are both connected between the working voltage VDD and the output end of the first driving module 11, that is, the first resistor R1 is connected between the working voltage VDD and the drain of the second NMOS transistor MN2, and the second resistor R2 is connected between the working voltage VDD and the drain of the first NMOS transistor MN1. More specifically, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2.

[0048] The second balancing module 14 includes a third resistor R3 and a fourth resistor R4, wherein the first end of the third resistor R3 and the first end of the fourth resistor R4 are both connected to the output end of the first driving module 11, that is, the first end of the third resistor R3 is connected to the drain of the first NMOS transistor MN1, and the first end of the fourth resistor R4 is connected to the drain of the second NMOS transistor MN2. More specifically, the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4.

[0049] The third equalization module 15 includes a fifth resistor R5 and a sixth resistor R6, wherein the fifth resistor R5 is connected between the working voltage VDD and the second end of the fourth resistor R4; the sixth resistor R6 is connected between the working voltage VDD and the second end of the third resistor R3. More specifically, the resistance value of the fifth resistor R5 is equal to the resistance value of the sixth resistor R6.

[0050] Furthermore, the fourth resistor R4 is connected in series with the first resistor R1 to form a first series branch, the first series branch and the fifth resistor R5 are connected in parallel to form a first parallel branch, and the resistance value of the first parallel branch is equal to the characteristic impedance value of the bidirectional link; the third resistor R3 and the second resistor R2 are connected in series to form a second series branch, the second series branch and the sixth resistor R6 are connected in parallel to form a second parallel branch, and the resistance value of the second parallel branch is equal to the characteristic impedance value of the bidirectional link.

[0051] The second driving module 12 includes: a first unit 121, a second unit 122, a seventh resistor R7 and an eighth resistor R8, wherein: the first end of the seventh resistor R7 and the first end of the eighth resistor R8 are both connected to the working voltage VDD; the first unit 121 is connected between the output end of the first driving module 11 and the second end of the seventh resistor R7 and the second end of the eighth resistor R8; the second unit 122 is connected between the second end of the second balancing module 14 and the second end of the seventh resistor R7 and the second end of the eighth resistor R8. More specifically, the resistance value of the seventh resistor R7 is equal to the resistance value of the eighth resistor R8.

[0052] More specifically, the first unit 121 includes: a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a second current source I2, wherein: the drain of the third NMOS transistor MN3 is connected to the second end of the eighth resistor R8, the drain of the fourth NMOS transistor MN4 is connected to the second end of the seventh resistor R7, the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 are both connected to the output end of the first driving module 11, that is, the gate of the third NMOS transistor MN3 is connected to the drain of the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4 is connected to the drain of the first NMOS transistor MN1, and the source of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4; the second current source I2 is connected between the source of the third NMOS transistor MN3 and the reference ground, and the second current source I2 is connected between the source of the fourth NMOS transistor MN4 and the reference ground, wherein the first signal is generated by the drain of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4.

[0053] The second unit 122 includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6 and a third current source I3, wherein: the drain of the fifth NMOS transistor MN5 is connected to the second end of the seventh resistor R7, the drain of the sixth NMOS transistor MN6 is connected to the second end of the eighth resistor R8, the gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are both connected to the second end of the second balancing module 14, that is, the gate of the fifth NMOS transistor MN5 is connected to the second end of the fourth resistor R4, the gate of the sixth NMOS transistor MN6 is connected to the second end of the third resistor R3, and the fifth NMOS transistor MN5 is connected to the second end of the fourth resistor R4. The gate of the fifth NMOS tube MN5 and the gate of the sixth NMOS tube MN6 are connected to the signal of the second end of the second balancing module 14; the source of the fifth NMOS tube MN5 is connected to the source of the sixth NMOS tube MN6; the third current source I3 is connected between the source of the fifth NMOS tube MN5 and the reference ground, and the third current source I3 is connected between the source of the sixth NMOS tube MN6 and the reference ground, wherein the third current source I3 separates the signal of the second end of the second balancing module 14 from the first signal through the drain of the fifth NMOS tube MN5 and the drain of the sixth NMOS tube MN6 to extract the inbound and outbound signals, wherein VRX1 The voltage of the inbound signal that characterizes the extracted inbound signal.

[0054] It should be noted that the first driver module 11 and the second driver module 12 can also be set up using ASIC (Application Specific Integrated Circuit, i.e., a dedicated integrated circuit, which is a proprietary application chip designed and manufactured for specific user requirements and specific electronic systems, and its computing power and computing efficiency can be customized according to algorithm requirements), or can be set up using IP core (IP core, full name intellectual property core, English full name intellectual property core, in the reusable design methodology of integrated circuits, refers to a reusable module in the form of logic units and chip designs provided by one party. IP cores have usually passed design verification, and designers can shorten the design cycle by designing based on IP cores), or can be set up using logic gate circuits, wherein the setting forms of ASIC, IP core and logic gate circuits are not described one by one here, as long as the separation operation can be performed to extract the inbound signal, any setting form of the first driver module 11 and the second driver module 12 is applicable, and is not limited to this embodiment.

[0055] It should be noted that the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 can be set as a single resistor, or can be set as a plurality of resistors connected in series, or a plurality of resistors connected in parallel, or a combination of a plurality of resistors connected in series and parallel. As long as the first balancing module 13, the second balancing module 14 and the third balancing module 15 can balance the voltage and timing margin of the outbound signal and the inbound signal, any setting form of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 is applicable, and is not limited to the present embodiment.

[0056] Figure 5 The framework of the inbound signal extraction circuit is shown, which eliminates the power consumption of the replica driver due to the duplication of the outbound signal, avoids the error caused by duplicating the outbound signal, and thus improves the signal transmission rate. Since the framework of the inbound signal extraction circuit is relatively concise, it enables the bidirectional link to integrate modules such as equalization to further improve the signal transmission quality and pulse amplitude modulation to further improve the signal transmission rate, without burdening the bidirectional link. Therefore, the inbound signal extraction circuit provided in this embodiment has wide applicability. It should be noted that the first equalization module 13, the second equalization module 14 and the third equalization module 15 are all in Figure 5A simplified illustration is given in the figure.

[0057] In order to further verify the applicability of the inbound signal extraction circuit provided in this embodiment, Figure 6 A bidirectional link is shown, and the bidirectional link is provided with the inbound signal extraction circuit provided by this embodiment, wherein the characteristic impedance of the bidirectional link is Z0, Chip1 and Chip2 can both include the inbound signal extraction circuit, and Chip1 and Chip2 are respectively provided at the two ends of the bidirectional link, and V t1 Represents the signal transmitted from Chip1 to Chip2, V t1 The output of Chip1's transmitter TX1 is transmitted to Chip2 via a bidirectional link. TX1 Represented as the voltage of the transmitting end TX1, V r1 Represents the signal transmitted from Chip2 to Chip1, V r1 Output from Chip2's transmitter TX2, V TX2 It is represented as the voltage at the transmitter TX2, assuming a lossless bidirectional link, where:

[0058] The voltage signal at the second end of the third resistor R3 and the second end of the fourth resistor R4 in Chip1 is V, and the signal V is expressed as:

[0059] V=V t1 +V r1 (1);

[0060] Assume that the resistance values ​​of the first resistor R1 and the second resistor R2 are both 2Z0-r, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are both r, the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 are both 2Z0, and the signal at the first end of the third resistor R3 and the first end of the fourth resistor R4 is V S , then the signal V S The voltage is equal to (2Z0-r)||(r+2Z0||Z0)*I1, where "||" represents a parallel relationship, Z0 represents the characteristic impedance of the bidirectional link, and I1 represents the output value of the first current source. The voltage V1b provided by Chip1 to the first end of the third resistor R3 and the first end of the fourth resistor R4 is obtained by calculation, then

[0061]

[0062] The voltage provided by Chip1 to the second end of the third resistor R3 and the second end of the fourth resistor R4 is V1a.

[0063] but Further, The voltage V2b provided by Chip2 to the first end of the third resistor R3 and the first end of the fourth resistor R4 is

[0064]

[0065] Therefore, the signal V at the first end of the third resistor R3 and the first end of the fourth resistor R4 S The relationship is: V S =V1b+V2b(4); According to equations (1), (2) and (3), the expression of signal V is obtained, where:

[0066]

[0067] According to equations (4) and (5), eliminate the component containing I1, and then get V RX1 An expression where:

[0068]

[0069] This completes the separation operation to extract the inbound and outbound signals.

[0070] This embodiment further provides a synchronous bidirectional transceiver, which includes the inbound signal extraction circuit described in this embodiment, and is used to extract inbound and outbound signals. The working process of the synchronous bidirectional transceiver will not be described in detail here.

[0071] In summary, an inbound signal extraction circuit and a synchronous bidirectional transceiver of the present invention are arranged on a bidirectional link, and both the outbound signal and the inbound signal are transmitted on the bidirectional link, including: a first driving module, a second driving module, a first equalizing module, a second equalizing module and a third equalizing module, wherein: the input end of the first driving module is connected to the outbound signal; the first equalizing module is connected between the working voltage and the output end of the first driving module, the first end of the second equalizing module is connected to the output end of the first driving module, the third equalizing module is connected between the working voltage and the second end of the second equalizing module, the first equalizing module, the second equalizing module and the third equalizing module are used to equalize the voltage and timing margin of the outbound signal and the inbound signal; the input end of the second driving module is connected to the output end of the first driving module and the second end of the second equalizing module to generate a first signal, and extract the inbound signal based on the separation operation of the signal at the second end of the second equalizing module and the first signal. The inbound signal extraction circuit and the synchronous bidirectional transceiver of the present invention can maximize the consistency of voltage amplitude and phase, ensure sufficient voltage and timing margin, improve signal transmission rate and save power consumption, and have wide applicability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An inbound signal extraction circuit, arranged on a bidirectional link, wherein both the outbound signal and the inbound signal are transmitted on the bidirectional link, characterized in that: The inbound signal extraction circuit at least includes: a first driving module, a second driving module, a first equalizing module, a second equalizing module and a third equalizing module, wherein: The input end of the first driving module is connected to the outbound signal; the first equalizing module is connected between the working voltage and the output end of the first driving module, the first end of the second equalizing module is connected to the output end of the first driving module, and the third equalizing module is connected between the working voltage and the second end of the second equalizing module. The first equalizing module, the second equalizing module and the third equalizing module are used to equalize the voltage and timing margin of the outbound signal and the inbound signal; the input end of the second driving module is connected to the output end of the first driving module and the second end of the second equalizing module to generate a first signal, and the inbound signal is extracted based on the separation operation of the signal at the second end of the second equalizing module and the first signal.

2. The inbound signal extraction circuit according to claim 1, characterized in that: The first driving module includes: a first NMOS tube, a second NMOS tube and a first current source, wherein: the gates of the first NMOS tube and the second NMOS tube are connected to the outbound signal, the source of the first NMOS tube is connected to the source of the second NMOS tube; and the first current source is connected between the source of the first NMOS tube and a reference ground.

3. The inbound signal extraction circuit according to claim 1, characterized in that: The first equalizing module includes a first resistor and a second resistor, wherein the first resistor and the second resistor are both connected between a working voltage and an output terminal of the first driving module.

4. The inbound signal extraction circuit according to claim 3, characterized in that: The resistance value of the first resistor is equal to the resistance value of the second resistor.

5. The inbound signal extraction circuit according to claim 4, characterized in that: The second equalizing module includes a third resistor and a fourth resistor, wherein a first end of the third resistor and a first end of the fourth resistor are both connected to the output end of the first driving module.

6. The inbound signal extraction circuit according to claim 5, characterized in that: The resistance value of the third resistor is equal to the resistance value of the fourth resistor.

7. The inbound signal extraction circuit according to claim 6, characterized in that: The third equalizing module includes a fifth resistor and a sixth resistor, wherein the fifth resistor is connected between the operating voltage and the second end of the fourth resistor; and the sixth resistor is connected between the operating voltage and the second end of the third resistor.

8. The inbound signal extraction circuit according to claim 7, characterized in that: The resistance value of the fifth resistor is equal to the resistance value of the sixth resistor.

9. The inbound signal extraction circuit according to claim 8, characterized in that: The fourth resistor is connected in series with the first resistor to form a first series branch, the first series branch is connected in parallel with the fifth resistor to form a first parallel branch, and the resistance value of the first parallel branch is equal to the characteristic impedance value of the bidirectional link; the third resistor is connected in series with the second resistor to form a second series branch, the second series branch is connected in parallel with the sixth resistor to form a second parallel branch, and the resistance value of the second parallel branch is equal to the characteristic impedance value of the bidirectional link.

10. The inbound signal extraction circuit according to claim 1, characterized in that: The second driving module includes: a first unit, a second unit, a seventh resistor and an eighth resistor, wherein: the first end of the seventh resistor and the first end of the eighth resistor are both connected to the working voltage; the first unit is connected between the output end of the first driving module and the second end of the seventh resistor and the second end of the eighth resistor; the second unit is connected between the second end of the second balancing module and the second end of the seventh resistor and the second end of the eighth resistor.

11. The inbound signal extraction circuit according to claim 10, characterized in that: The first unit includes: a third NMOS tube, a fourth NMOS tube and a second current source, wherein: the drain of the third NMOS tube is connected to the second end of the eighth resistor, the drain of the fourth NMOS tube is connected to the second end of the seventh resistor, the gate of the third NMOS tube and the gate of the fourth NMOS tube are both connected to the output end of the first driving module, and the source of the third NMOS tube is connected to the source of the fourth NMOS tube; the second current source is connected between the source of the third NMOS tube and the reference ground.

12. The inbound signal extraction circuit according to claim 10, characterized in that: The second unit includes: a fifth NMOS tube, a sixth NMOS tube and a third current source, wherein: the drain of the fifth NMOS tube is connected to the second end of the seventh resistor, the drain of the sixth NMOS tube is connected to the second end of the eighth resistor, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are both connected to the second end of the second equalization module, and the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube; the third current source is connected between the source of the fifth NMOS tube and the reference ground.

13. The inbound signal extraction circuit according to claim 10, characterized in that: The resistance value of the seventh resistor is equal to the resistance value of the eighth resistor.

14. A synchronous bidirectional transceiver, characterized in that: The synchronous bidirectional transceiver comprises an inbound signal extraction circuit as described in any one of claims 1-13.

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