Memory device and method of manufacturing the same

Abstract

The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a bottom source structure, a plurality of gate layers and a plurality of dielectric layers, a contact structure, and a plurality of pillar structures. The bottom source structure is disposed on the substrate. The bottom source electrode structure comprises a bottom electrode layer, a dielectric stacking structure and a blocking structure. The gate layer and the dielectric layer are stacked on the bottom source structure in a staggered manner. A contact structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The pillar structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. A dielectric stack structure of the bottom source structure surrounds each of the pillar structures, and a blocking structure of the bottom source structure is disposed between one of the pillar structures and the contact structure.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for manufacturing the memory device. Background Art

[0002] In the semiconductor industry, the structure of memory devices is constantly changing, and the storage capacity of memory devices is constantly increasing. Memory devices are used in storage components of many products (such as MP3 players, digital cameras, and computer files, etc.). As these applications increase, the demand for memory devices focuses on small size and large storage capacity. In order to meet this condition, memory devices and manufacturing methods with high component density, small size and robust structure are required. Therefore, it is important to provide a robust process in the manufacture of memory devices. Summary of the invention

[0003] One technical aspect of the present disclosure is a memory device.

[0004] According to some embodiments of the present disclosure, a memory device includes a substrate, a bottom source structure, a plurality of gate layers and a plurality of dielectric layers, a contact structure, and a plurality of pillar structures. The bottom source structure is disposed on the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure, and a barrier structure. The gate layer and the dielectric layer are stacked alternately on the bottom source structure. The contact structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The pillar structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the pillar structures, and the barrier structure of the bottom source structure is disposed between one of the pillar structures and the contact structure.

[0005] In some embodiments of the present disclosure, the blocking structure contacts the dielectric stack structure and the contact structure.

[0006] In some embodiments of the present disclosure, the bottom-source structure further includes a first conductive layer and a second conductive layer disposed on the first conductive layer, and the blocking structure is disposed between the first conductive layer and the second conductive layer.

[0007] In some embodiments of the present disclosure, the contact structure extends along a first direction, and the first portion of the blocking structure is adjacent to a section of the contact structure along the first direction.

[0008] In some embodiments of the present disclosure, the blocking structure further includes a second portion. The second portion of the blocking structure extends along a second direction perpendicular to the first direction.

[0009] In some embodiments of the present disclosure, the memory device further comprises a memory structure. The memory structure passes through the gate layer and the dielectric layer above the array region. The contact structure extends along a first direction above the array region and the step region including the pillar structure.

[0010] Another technical aspect of the present disclosure is a memory device.

[0011] According to some embodiments of the present disclosure, a memory device includes a substrate, a bottom source structure, a plurality of gate layers and a plurality of dielectric layers, a contact structure, and a pillar structure. The bottom source structure is disposed on the substrate. The bottom source structure includes a bottom electrode layer and a dielectric stack structure. The gate layer and the dielectric layer are stacked alternately on the bottom source structure. The contact structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The pillar structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The dielectric stack structure of the bottom source structure is laterally located between a lower portion of the contact structure and a lower portion of the pillar structure.

[0012] In some embodiments of the present disclosure, the bottom source structure further includes a blocking structure, and the blocking structure is laterally adjacent to the dielectric stack structure.

[0013] In some embodiments of the present disclosure, a bottom surface of the pillar structure is below a bottom surface of the dielectric stack structure.

[0014] Another technical aspect of the present disclosure is a method for manufacturing a memory device.

[0015] According to some embodiments of the present disclosure, a method for manufacturing a memory device includes sequentially forming a first conductive layer, a dielectric stack structure, and a second conductive layer on a substrate, wherein the substrate has an array region and a step region. A barrier layer is formed on the second conductive layer, wherein the barrier layer above the step region further passes through the second conductive layer and the dielectric stack structure. A plurality of dielectric layers and a plurality of sacrificial material layers are formed and stacked alternately on the barrier layer. A memory structure is formed to pass downward through the dielectric layer, sacrificial material layer, barrier layer, second conductive layer, and dielectric stack structure above the array region, wherein the memory structure includes a memory element and a channel layer on the memory element. A pillar structure is formed to pass downward through the dielectric layer, sacrificial material layer, barrier layer, second conductive layer, and dielectric stack structure above the step region. A slit channel is formed to pass downward through the dielectric layer and sacrificial material layer above the array region and the step region. The barrier layer and the second conductive layer above the array region are etched from the slit channel to expose the dielectric stack structure. The dielectric stack structure above the array region and the memory element of the memory structure are etched to expose the channel layer of the memory structure. A bottom electrode layer is formed to electrically connect the channel layer of the memory structure. The sacrificial material layer is replaced with a plurality of gate layers. A contact structure is formed in the slit channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understood, the following are the descriptions of the accompanying drawings:

[0017] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A as well as Fig.14A Schematically illustrates top views of different stages of a method for manufacturing a memory device according to some embodiments of the present disclosure.

[0018] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B as well as Fig. 14B Schematically illustrates cross-sectional views of different stages of a method for manufacturing a memory device according to some embodiments of the present disclosure.

[0019] Fig. 14C yes Fig.14A A cross-sectional view taken along line segment S2-S2.

[0020] Fig.15 A top view of a memory device according to some embodiments of the present disclosure is schematically shown.

[0021] Description of reference numerals:

[0022] 100, 100': Memory device

[0023] 110: Substrate

[0024] 120: Isolation layer

[0025] 130: First conductive layer

[0026] 131, 151, 171, 211, 261, 271, 281, 311, 321: Top

[0027] 137, 153, 303: Surface

[0028] 147, 157, 167, 193, DS1: Sidewall

[0029] 140: First dielectric layer

[0030] 150: Second dielectric layer

[0031] 160: The third dielectric layer

[0032] 165, 175, 275, DS2: Bottom

[0033] 170: Second conductive layer

[0034] 180: Isolation layer

[0035] 190: Barrier layer

[0036] 195: Blocking Structure

[0037] 195': Partial

[0038] 210: Dielectric layer

[0039] 220: Sacrificial material layer

[0040] 230: Memory Components

[0041] 232: Barrier layer

[0042] 234: Storage layer

[0043] 236: Tunneling layer

[0044] 240: Channel layer

[0045] 250: Dielectric filling structure

[0046] 260: Conductive plug

[0047] 260S: Space

[0048] 270: Pillar structure

[0049] 270U,CSU: Upper part

[0050] 270L,CSL: Lower part

[0051] 280: Isolation layer

[0052] 290: Protective layer

[0053] 300: Bottom electrode layer

[0054] 300': Conductive structure

[0055] 302': Part 1

[0056] 304': Part 2

[0057] 310: Padding layer

[0058] 320: Electrode layer

[0059] 330: Gate layer

[0060] AR; array area

[0061] BS: Bottom-source structure

[0062] CH: Channel structure

[0063] CS: Contact Structure

[0064] D1: First direction

[0065] D2: Second direction

[0066] DS: Dielectric Stack Structure

[0067] H1: Holes

[0068] MS: Memory Structure

[0069] O1, O1', O2: Open

[0070] O1a, 195a: Part I

[0071] O1b,195b: Part II

[0072] P1: Part

[0073] R1, R2: Groove

[0074] T1, T2: thickness

[0075] SR: Step Area

[0076] ST: Slit channel

[0077] W1: First width

[0078] W2: Second width

[0079] A1-A1', S1-S1', S2-S2': Line segment DETAILED DESCRIPTION

[0080] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some existing conventional structures and elements will be schematically shown in the drawings in a simple schematic manner. In addition, for the convenience of readers, the sizes of the elements in the drawings are not drawn according to the actual scale.

[0081] As used herein, "about", "approximately" or "substantially" shall generally refer to within 10 percent of a given value or range, and more preferably within 5 percent. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the meaning of the term "about", "approximately" or "substantially" can be inferred.

[0082] In an embodiment of the present disclosure, a memory device and a method for manufacturing the same are provided. It should be understood that for ease of description, the term "top view" in the present disclosure may generally refer to the second conductive layer (i.e., Figure 1B The cross-sectional view of the middle line segment AA) is provided to highlight the technical features of the present disclosure. In addition, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A as well as Fig.14A Top views of the layout of a memory device according to some embodiments of the present disclosure are schematically shown, and for simplicity, some elements are not shown in these top views. Figures 1A to 1B , Figures 2A to 2B , Figures 3A to 3B , Figures 4A to 4B , Figures 5A to 5B , Figures 6A to 6B , Figures 7A to 7B , Figures 8A to 8B , Figures 9A to 9B , Figures 10A to 10B , Figures 11A to 11B , Figures 12A to 12B , Figures 13A to 13B as well as Figures 14A to 14C Schematically illustrating views of a method for manufacturing a memory device 100 at different stages according to some embodiments of the present disclosure.

[0083] Figure 1A A top view schematically shows a step in manufacturing the memory device 100, and Figure 1B Schematically shows Figure 1A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Figure 1A and Figure 1B , providing a substrate 110. The substrate 110 has an array region AR and a step region SR, wherein a memory array is formed above the array region AR of the substrate 110. The step region SR is adjacent to the array region AR.

[0084] An isolation layer 120 is formed on the substrate 110. Then, a first conductive layer 130, a dielectric stack structure DS, a second conductive layer 170, and an isolation layer 180 are sequentially formed on the substrate 110. In some embodiments, the first conductive layer 130, the dielectric stack structure DS, and the second conductive layer 170 are referred to as a bottom stack structure. In some other embodiments, the first conductive layer 130, the dielectric stack structure DS, the second conductive layer 170, and the isolation layer 180 are referred to as a bottom stack structure. The bottom stack structure extends along a plane defined by a first direction D1 and a second direction D2, wherein the first direction D1 is perpendicular to the second direction D2. The isolation layer 120 contacts the substrate 110. The first conductive layer 130 contacts the isolation layer 120. The dielectric stack structure DS contacts the first conductive layer 130. The second conductive layer 170 contacts the dielectric stack structure DS. The isolation layer 180 contacts the second conductive layer 170. In some embodiments, forming the dielectric stack structure DS includes sequentially forming a first dielectric layer 140 , a second dielectric layer 150 , and a third dielectric layer 160 . The first dielectric layer 140 contacts the first conductive layer 130 , and the third dielectric layer 160 contacts the second conductive layer 170 .

[0085] After forming the isolation layer 180 on the substrate 110, an opening O1 is formed downwardly through the isolation layer 180, the second conductive layer 170, and the third dielectric layer 160 of the dielectric stack structure DS, and the second dielectric layer 150 of the dielectric stack structure DS is exposed. In some embodiments, forming the opening O1 further includes etching a portion of the second dielectric layer 150 so that the exposed surface 153 of the second dielectric layer 150 is located below the top surface 151 of the second dielectric layer 150 (or the bottom surface of the third dielectric layer 160). In some embodiments, a patterned photoresist is formed on the isolation layer 180, wherein the patterned photoresist can be formed by appropriate deposition, development and / or etching techniques. Then, the patterned photoresist is used as an etching mask to etch the isolation layer 180, the second conductive layer 170, and the third dielectric layer 160 of the dielectric stack structure DS that are not covered by the patterned photoresist to form the opening O1. After the opening O1 is formed, the patterned photoresist may be removed by using a photoresist stripping process (eg, an ashing process).

[0086] like Figure 1A As shown, the opening O1 is disposed above the step region SR and is separated from the array region AR. The opening O1 may include a first portion O1a and a second portion O1b perpendicular to the first portion O1a. Specifically, the first portion O1a extends along a first direction D1, and the second portion O1b extends along a second direction D2. The first portion O1a is connected to the second portion O1b. The opening O1 has a comb-shaped profile in a top view.

[0087] In some embodiments, the substrate 110 is a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or the like. The substrate 110 may include an interconnect structure having conductive contacts, transistors, or other similar components. In some embodiments, the isolation layer 120 includes an oxide (e.g., silicon oxide). In some embodiments, the first conductive layer 130 and the second conductive layer 170 include the same material. For example, the first conductive layer 130 and the second conductive layer 170 include a semiconductor material (e.g., polysilicon). In some embodiments, the first dielectric layer 140 is a first oxide layer, the second dielectric layer 150 is a nitride layer, and the third dielectric layer 160 is a second oxide layer. In some embodiments, the isolation layer 180 includes an oxide (e.g., silicon oxide). In some embodiments, the isolation layer 120 and the isolation layer 180 include the same material (e.g., oxide).

[0088] Figure 2A A top view schematically shows a step in manufacturing the memory device 100, and Figure 2B Schematically shows Figure 1A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1 - A1 ′ and line segment S1 - S1 ′, respectively. Figure 3A A top view schematically shows a step in manufacturing the memory device 100, and Figure 3B Schematically shows Figure 3A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Figure 2A , Figure 2B , Figure 3A and Figure 3B After the opening O1 is formed, the dielectric stack structure DS is etched to laterally expand a portion P1 of the opening O1 located below the second conductive layer 170. Figure 2A and Figure 2B , a first etching process is performed on the second dielectric layer 150 so that the bottom surface 165 of the third dielectric layer 160 is exposed. In some embodiments, the first etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, since the second dielectric layer 150 and the first dielectric layer 140 (or the third dielectric layer 160) have different etching selectivities, during the first etching process, the second dielectric layer 150 is etched while the first dielectric layer 140 (or the third dielectric layer 160) remains substantially intact (unetched). That is, the first dielectric layer 140, the third dielectric layer 160, the second conductive layer 170, and the isolation layer 180 have a higher etching resistance to the first etching process than the second dielectric layer 150.

[0089] like Figure 2A , Figure 2B , Figure 3A as well as Figure 3B As shown, after performing the first etching process, a second etching process is performed to expose the bottom surface 175 of the second conductive layer 170 and the top surface 131 of the first conductive layer 130. In detail, performing the second etching process includes etching the third dielectric layer 160 and the first dielectric layer 140 of the dielectric stack structure DS. In some embodiments, performing the second etching process further includes etching the isolation layer 180 so that the top surface 171 of the second conductive layer 170 is exposed. During the second etching process, since the first dielectric layer 140, the third dielectric layer 160 and the isolation layer 180 are made of the same material (e.g., oxide), the first dielectric layer 140, the third dielectric layer 160 and the isolation layer 180 can be etched at the same time. After performing the second etching process, the opening O1 exposes the sidewall 147 of the first dielectric layer 140, the sidewall 157 of the second dielectric layer 150 and the sidewall 167 of the third dielectric layer 160. The sidewalls 147, 157, and 167 are substantially aligned with each other. As a result of the first etching process and the second etching process, the opening O1 has a first width W1 in the second conductive layer 170 and a second width W2 in the dielectric stack structure DS. The second width W2 of the opening O1 is greater than the first width W1 of the opening O1. In some embodiments, the second etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, since the first dielectric layer 140 (or the third dielectric layer 160) and the second dielectric layer 150 have different etching selectivities, during the second etching process, the first dielectric layer 140 (or the third dielectric layer 160) is etched while the second dielectric layer 150 remains substantially intact (unetched). That is, the second dielectric layer 150 and the second conductive layer 170 have a higher etching resistance to the second etching process than the first dielectric layer 140, the third dielectric layer 160, and the isolation layer 180. In some embodiments, the etchant of the second etching process is different from the etchant of the first etching process.

[0090] Figure 4A A top view schematically shows a step in manufacturing the memory device 100, and Figure 4B Schematically shows Figure 4A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Figure 4A and Figure 4B, after performing the second etching process, a conductive material is filled in the opening O1 and above the second conductive layer 170 to form a barrier layer 190. In other words, the second conductive layer 170 is covered by the barrier layer 190. The barrier layer 190 has a portion 195' above the step region SR and passing through the second conductive layer 170 and the dielectric stack structure DS. In some embodiments, since the conductive structure fills the opening O1, the barrier layer 190 in the second conductive layer 170 and the dielectric stack structure DS inherits the geometry of the opening O1. In other words, the barrier layer 190 in the second conductive layer 170 has a first width W1, and the barrier layer 190 in the dielectric stack structure DS has a second width W2 greater than the first width W1.

[0091] In some embodiments, Figure 3A , Figure 3B , Figure 4A as well as Figure 4B As shown, the first width W1 of the opening O1 in the second conductive layer 170 is greater than the thickness T1 of the dielectric stack structure DS. Therefore, the opening O1 can be completely filled with the conductive material, so there is no void in the barrier layer 190. If the first width W1 of the opening O1 in the second conductive layer 170 is less than the thickness T1 of the dielectric stack structure DS, the opening O1 in the second conductive layer 170 will be sealed by the conductive material too early, so that a void may be formed in a portion of the barrier layer 190 in the dielectric stack structure DS. In some embodiments, the first width W1 of the opening O1 in the second conductive layer 170 (or the first width of the barrier layer 190) is in a range from about 50 nanometers to about 200 nanometers. If the first width W1 is less than 50 nanometers, the barrier layer 190 in the dielectric stack structure DS will have a void. If the first width W1 is greater than 200 nanometers, the barrier layer 190 above the second conductive layer 170 will be too thick.

[0092] In some embodiments, the thickness T2 of the barrier layer 190 above the second conductive layer 170 is greater than half of the first width W1 of the opening O1 in the second conductive layer 170. Therefore, the opening O1 can be filled with conductive material, so there is no void in the barrier layer 190. In some embodiments, the thickness T2 of the barrier layer 190 above the second conductive layer 170 is in the range of about 50 nanometers to about 300 nanometers. If the thickness T2 of the barrier layer 190 is less than 50 nanometers, the barrier layer 190 in the dielectric stack structure DS may have voids. If the thickness T2 of the barrier layer 190 is greater than 300 nanometers, the electrical performance of the barrier layer 190 may be poor.

[0093] In some embodiments, filling the opening O1 with a conductive material to form the barrier layer 190 is performed by using chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes. In some embodiments, the barrier layer 190 and the second conductive layer 170 include the same material. For example, the barrier layer 190 and the second conductive layer 170 include a semiconductor material (e.g., polysilicon). In some embodiments, the barrier layer 190 and the first conductive layer 130 include the same material. For example, the barrier layer 190 and the first conductive layer 130 include a semiconductor material (e.g., polysilicon).

[0094] Figure 5A A top view schematically shows a step in manufacturing the memory device 100, and Figure 5B Schematically shows Figure 5A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Figure 5A and Figure 5B , a plurality of dielectric layers 210 and a plurality of sacrificial material layers 220 are alternately stacked above the barrier layer 190. The dielectric layers 210 and the sacrificial material layers 220 are alternately arranged above the barrier layer 190, and the bottom layer of the dielectric layer 210 closest to the barrier layer 190 directly contacts the barrier layer 190. In some embodiments, the dielectric layer 210 and the sacrificial material layer 220 include different materials. For example, the dielectric layer 210 includes an oxide (e.g., silicon oxide), and the sacrificial material layer 220 includes a nitride (e.g., silicon nitride).

[0095] Fig. 6A A top view schematically shows a step in manufacturing the memory device 100, and Figure 6B Schematically shows Fig. 6A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig. 6A and Figure 6BAfter forming the dielectric layer 210 and the sacrificial material layer 220, a plurality of memory structures MS are formed downwardly through the dielectric layer 210, the sacrificial material layer 220, the barrier layer 190, the second conductive layer 170, and the dielectric stack structure DS above the array region AR. In some embodiments, each of the memory structures MS has a portion embedded in the first conductive layer 130. Each of the memory structures MS includes a channel structure CH and a conductive plug 260 located on the channel structure CH. The channel structure CH includes a memory element 230, a channel layer 240, and a dielectric filling structure 250. The memory element 230 contacts the sacrificial material layer 220, the barrier layer 190, the second conductive layer 170, the dielectric stack structure DS, and the first conductive layer 130. The channel layer 240 contacts the memory element 230, and the channel layer 240 is located between the memory element 230 and the dielectric filling structure 250. In some embodiments, the memory element 230 includes a barrier layer 232, a storage layer 234, and a tunneling layer 236. The barrier layer 232 is disposed on the sidewalls of the dielectric layer 210, the sidewalls of the sacrificial material layer 220, the sidewalls of the barrier layer 190, the sidewalls of the second conductive layer 170, the sidewalls of the dielectric stack structure DS, the sidewalls of the first conductive layer 130, and the surface of the first conductive layer 130. The storage layer 234 is disposed on the barrier layer 232, and the tunneling layer 236 is disposed on the storage layer 234. The barrier layer 232 and the tunneling layer 236 may include oxide (e.g., silicon oxide) or other suitable dielectric materials, and the storage layer 234 may include nitride (e.g., silicon nitride) or other materials capable of capturing electrons. Therefore, the memory element 230 may be a three-layer structure of an oxide layer, a nitride layer, and an oxide layer. The channel layer 240 may include polysilicon or other suitable semiconductor materials. The dielectric filling structure 250 may include oxide (e.g., silicon oxide) or other suitable dielectric materials. The conductive plug 260 may include polysilicon or other suitable semiconductor materials. The conductive plug 260 and the channel layer 240 may include the same material, such as a semiconductor material or polysilicon.

[0096] In some embodiments, forming the memory structure MS includes the following steps. A plurality of openings O2 are formed downward through the dielectric layer 210, the sacrificial material layer 220, the barrier layer 190, the second conductive layer 170, and the dielectric stack structure DS above the array region AR, so that the first conductive layer 130 is exposed. The memory element 230 (including the barrier layer 232, the storage layer 234, and the tunneling layer 236) is formed on the opposite sidewalls of the opening O2, but the opening O2 is not yet completely filled with the memory element 230. Then, a channel layer 240 is formed on the sidewalls and the bottom of the memory element 230, but the opening O2 is not yet completely filled with the channel layer 240. Thereafter, a dielectric material is filled in the opening O2 to form a dielectric filling structure 250 on the channel layer 240. In this way, a channel structure CH including the memory element 230, the channel layer 240, and the dielectric filling structure 250 is formed. After forming the channel structure CH (i.e., the memory element 230, the channel layer 240, and the dielectric filling structure 250), the recessed space 260S is used to expose the top surface of the channel structure CH. Therefore, the top surface of the channel structure CH is below the top surface 211 of the top layer of the dielectric layer 210. Then, a conductive material is filled in the space 260S to form a conductive plug 260 on the channel structure CH. In other words, the top surface 261 of the conductive plug 260 is substantially coplanar with the top surface 211 of the top layer of the dielectric layer 210. In this way, the memory structure MS including the channel structure CH (including the memory element 230, the channel layer 240, and the dielectric filling structure 250) and the conductive plug 260 is formed in the opening O2.

[0097] For the step region SR, a plurality of pillar structures 270 are formed downwardly through the dielectric layer 210, the sacrificial material layer 220, the barrier layer 190, the second conductive layer 170, and the dielectric stack structure DS above the step region SR. In detail, the dielectric layer 210, the sacrificial material layer 220, the barrier layer 190, the second conductive layer 170, and the dielectric stack structure DS above the step region SR are first etched to form a hole H1 exposing the first conductive layer 130. Then, a dielectric material is filled in the hole H1 to form the pillar structure 270. In some embodiments, each of the pillar structures 270 has a portion embedded in the first conductive layer 130. In some embodiments, the pillar structure 270 includes an oxide (e.g., silicon oxide) or other suitable dielectric material. In some embodiments, forming the memory structure MS is performed before forming the pillar structure 270. In some embodiments, as Fig. 6A As shown, each of the memory structures MS has a circular outline in a top view, and each of the pillar structures 270 has a circular outline in a top view. Fig. 6A As shown, the diameter of each of the pillar structures 270 is larger than the diameter of each of the memory structures MS.

[0098] Thereafter, an isolation layer 280 is formed on the topmost layer of the dielectric layer 210. In some embodiments, the pillar structure 270 and the isolation layer 280 can be formed together using a single deposition process. In other words, the pillar structure 270 and the isolation layer 280 comprise the same material. In some embodiments, the pillar structure 270 and the isolation layer 280 comprise an oxide (e.g., silicon oxide) or other suitable dielectric material. In some embodiments, the pillar structure 270, the isolation layer 280, and the dielectric layer 210 comprise the same material, such as an oxide.

[0099] Fig. 7A A top view schematically shows a step in manufacturing the memory device 100, and Figure 7B Schematically shows Fig. 7A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig. 7A and Figure 7B After forming the memory structure MS and the pillar structure 270, the dielectric layer 210 and the sacrificial material layer 220 are etched to form a slit channel ST above the array region AR and the step region SR and downwardly penetrate the dielectric layer 210 and the sacrificial material layer 220. In some embodiments, forming the slit channel ST further includes etching the barrier layer 190 above the array region AR and the step region SR.

[0100] In some embodiments, Fig. 7A As shown, each of the slit channels ST extends between the array region AR and the step region SR and extends along the first direction D1. Figure 1A As discussed, the opening O1 forming the barrier layer 190 includes a first portion O1a along the first direction D1 and a second portion O1b along the second direction D2. The slit channel ST is parallel to and overlaps the first portion O1a of the corresponding opening O1. The second portion O1b of the opening O1 is located between the memory structure MS and the pillar structure 270.

[0101] View Now Fig.15 , Fig.15 Schematically shows a top view of a memory device 100' according to some embodiments of the present disclosure. Fig. 7A and Fig.15 As shown, Fig.15 The memory device 100′ and Fig. 7AThe memory device 100 is substantially the same as the memory device 100, except for the profile of the opening O1' forming the barrier layer 190. The opening O1' extends along the first direction D1. The slit channels ST are respectively parallel to and overlap the corresponding openings O1'. The opening O1' does not have a portion located directly between the memory structure MS and the pillar structure 270.

[0102] Fig. 8A A top view schematically shows a step in manufacturing the memory device 100, and Figure 8B Schematically shows Fig. 8A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig. 8A and Figure 8B , an etching process is performed to further extend (or deepen) the slit channel ST. For the array region AR, the barrier layer 190 and the second conductive layer 170 are etched from the slit channel ST, and the etching process may stop at the position of the third dielectric layer 160 of the dielectric stack structure DS because the third dielectric layer 160 may include a higher etching resistance to the etching process. For the step region SR, the first portion of the barrier layer 190 exposed by the slit channel ST is removed, and the second portion of the barrier layer 190 not exposed by the slit channel ST is retained under the second conductive layer 170 after the etching process is completed. The remaining second portion of the barrier layer 190 is referred to as a barrier structure 195. In other words, the remaining second portion of the barrier layer 190 located between the first conductive layer 130 and the second conductive layer 170 is referred to as a barrier structure 195. The barrier structure 195 contacts the dielectric stack structure DS. After etching the barrier layer 190 over the array region AR and the step region SR, the first conductive layer 130 over the array region AR is still covered by the dielectric stack structure DS, while the first conductive layer 130 over the step region SR is exposed. In some embodiments, a portion of the first conductive layer 130 over the step region SR is etched so that an exposed surface 137 of the first conductive layer 130 is below a top surface 131 of the first conductive layer 130 contacting the barrier structure 195. In some embodiments, etching the barrier layer 190 over the array region AR and the step region SR is performed by using a dry etching process, a wet etching process, or a combination thereof.

[0103] Fig.9A A top view schematically shows a step in manufacturing the memory device 100, and Fig. 9B Schematically shows Fig.9A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig.9A and Fig. 9B , the protective layer 290 is conformally formed on Fig. 8A and Figure 8B In detail, the protective layer 290 is formed on the top surface 281 of the isolation layer 280, the sidewalls of the dielectric layer 210, the sidewalls of the sacrificial material layer 220, the sidewalls of the barrier layer 190, and the sidewalls of the second conductive layer 170. In some embodiments, for the array region AR, the protective layer 290 is formed on the third dielectric layer 160 of the dielectric stack structure DS and contacts the third dielectric layer 160 of the dielectric stack structure DS. The protective layer 290 is configured to prevent the sidewalls of the slit trench ST (e.g., the sidewalls of the dielectric layer 210 and the sidewalls of the sacrificial material layer 220) from being etched in a subsequent etching process (e.g., in FIG. 10A to FIG. 11B In some embodiments, for the step region SR, the protection layer 290 is formed on the top surface of the first conductive layer 130 and the sidewalls of the barrier structure 195, and the protection layer 290 contacts the first conductive layer 130 and the barrier structure 195. In some embodiments, the protection layer 290 includes a semiconductor material (e.g., polysilicon). In some embodiments, the protection layer 290, the second conductive layer 170, and / or the first conductive layer 130 include the same material.

[0104] After forming the protection layer 290, the bottom portion of the protection layer 290 is etched to expose the dielectric stack structure DS above the array region AR and to expose the first conductive layer 130 above the step region SR. In some embodiments, etching the protection layer 290 is performed by using a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the third dielectric layer 160 of the dielectric stack structure DS above the array region AR is etched to expose the second dielectric layer 150 of the dielectric stack structure DS below. In some embodiments, a portion of the second dielectric layer 150 of the dielectric stack structure DS is etched so that the sidewalls and the surface of the second dielectric layer 150 are exposed. Since the barrier structure 195 above the step region SR protects the adjacent dielectric stack structure DS, the dielectric stack structure DS is not exposed (i.e., covered by the barrier structure 195) during etching of the protection layer 290. In addition, during etching of the dielectric stack structure DS (i.e., above the step region SR), the dielectric stack structure DS is not exposed (i.e., covered by the barrier structure 195). FIG. 10A to FIG. 11B During the etching process of the dielectric stack structure DS, damage to the pillar structure 270 will be avoided or prevented, thereby avoiding deformation or collapse problems.

[0105] Fig. 10A A top view schematically shows a step in manufacturing the memory device 100, and Fig. 10B Schematically shows Fig. 10A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig. 10A and Fig. 10B , the entire second dielectric layer 150 of the dielectric stack structure DS above the array region AR is removed to form a recess R1. The recess R1 exposes the first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS. In some embodiments, Fig. 10B As shown, the groove R1 is connected to the slit trench ST. In some embodiments, a wet etching process is used to remove the second dielectric layer 150 of the dielectric stack structure DS, wherein the wet etching process may use a phosphoric acid solution or other appropriate acidic etching solutions.

[0106] Fig.11A A top view schematically shows a step in manufacturing the memory device 100, and Fig. 11B Schematically shows Fig.11A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig.11A and Fig. 11B , remove the entire first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS above the array region AR to expand the recess R1. The memory element 230 of the memory structure MS is etched through the recess R1 to expose the channel layer 240 above the array region AR. The recess R1 further exposes the first conductive layer 130 and the second conductive layer 170 above the array region AR. In some embodiments, the first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS and the memory element 230 are etched by using a dry etching process, a wet etching process, or a combination thereof.

[0107] Fig. 12A A top view schematically shows a step in manufacturing the memory device 100, and Fig. 12B Schematically shows Fig. 12A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig. 12A and Fig. 12B, a conductive structure 300' is filled in the groove R1. In addition, a conductive structure 300' is formed on the sidewall of the slit trench ST, but the slit trench ST is not completely filled with the conductive structure 300'. In some embodiments, the conductive structure 300' is conformally formed on the protective layer 290. Therefore, the conductive structure 300' includes a first portion 302' on the isolation layer 280 and a second portion 304' on the sidewall of the slit trench ST. In some embodiments, the conductive structure 300' is filled into the groove R1 by using chemical vapor deposition, atomic layer deposition, physical vapor deposition or other appropriate deposition process methods. In some embodiments, the conductive structure 300' includes a semiconductor material (e.g., polysilicon). In some embodiments, the conductive structure 300', the protective layer 290, the second conductive layer 170 and / or the first conductive layer 130 include the same material.

[0108] Fig.13A A top view schematically shows a step in manufacturing the memory device 100, and Fig. 13B Schematically shows Fig.13A 1 is a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1' and line segment S1-S1'. Fig.13A and Fig. 13B , patterning the conductive structure 300' to form (or define) a bottom electrode layer 300 electrically connected to the channel layer 240 of the memory structure MS. Fig. 12B and Fig. 13B As shown, an etching process is performed to remove the first portion 302' of the conductive structure 300' above the isolation layer 280 and the second portion 304' of the conductive structure 300' on the sidewall of the slit trench ST. Fig. 13BAs shown, the surface 303 of the bottom electrode layer 300 is exposed through the slit trench ST, and the surface 303 of the bottom electrode layer 300 is below the bottom surface 175 of the second conductive layer 170. In some embodiments, the etching process is performed so that the entire conductive structure 300' above the step region SR is removed, thereby exposing the first conductive layer 130 above the step region SR. In addition, the entire protective layer 290 above the array region AR and the step region SR is removed. Therefore, the top surface 281 of the isolation layer 280, the sidewall of the dielectric layer 210, the sidewall of the sacrificial material layer 220, the sidewall of the barrier layer 190, and the sidewall of the second conductive layer 170 above the array region AR and the step region SR are exposed. In some embodiments, the sidewall 193 of the barrier structure 195 separated from the dielectric stack structure DS is exposed. In some embodiments, since the conductive structure 300' and the protection layer 290 include the same material (e.g., polysilicon or other suitable semiconductor materials), the conductive structure 300' and the protection layer 290 can be removed in a single selective etching process. In some embodiments, a wet etching process is used to remove the conductive structure 300' and the protection layer 290. In some embodiments, the first conductive layer 130, the dielectric stack structure DS, the second conductive layer 170, the barrier layer 190, the barrier structure 195, and the bottom electrode layer 300 are referred to as a bottom source structure BS.

[0109] Fig.14A A top view schematically showing a step of manufacturing a memory device 100, Fig. 14B Schematically shows Figure 2A sectional views of the memory device 100 above the array region AR and the step region SR taken along line segments A1-A1′ and S1-S1′, respectively; and Fig. 14C Schematically shows Fig.14A FIG. 1 is a cross-sectional view of the memory device 100 above the step region SR taken along line segment S2 - S2 ′. Fig.13A , Fig. 13B as well as FIG. 14A to FIG. 14C , the sacrificial material layer 220 is replaced with a plurality of gate layers 330. In detail, the entirety of the sacrificial material layer 220 is removed to form a groove R2, so that the groove R2 is connected to the slit channel ST. In some embodiments, the sacrificial material layer 220 is removed using a wet etching process, wherein the wet etching process may use a phosphoric acid solution or other appropriate acidic etching solution. In some embodiments, the pillar structure 270 provides structural support to prevent the memory device 100 from collapsing during the removal of the sacrificial material layer 220.

[0110] After removing the sacrificial material layer 220 to form the groove R2, a conductive material is filled in the groove R2, and then an etching process is performed to remove excess conductive material to form a gate layer 330. The gate layer 330 may be referred to as a word line. Specifically, the gate layer 330 may serve as a control gate electrode of the memory device 100 (particularly a vertical NAND memory device). In some embodiments, the conductive material is filled in the groove R2 by using chemical vapor deposition, atomic layer deposition, physical vapor deposition, chemical plating process or other appropriate deposition process. In some embodiments, the gate layer 330 includes a metal (e.g., tungsten) or other appropriate conductive material.

[0111] After the sacrificial material layer 220 is replaced with the gate layer 330, a contact structure CS is formed in the slit trench ST. In detail, each of the contact structures CS includes a liner layer 310 and an electrode layer 320. The liner layer 310 can be formed in the slit trench ST by using a deposition process, and then a conductive material is filled in the slit trench ST to form the electrode layer 320. The formation of the liner layer 310 can use a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other appropriate deposition processes. The liner layer 310 includes an oxide (e.g., silicon oxide) or other appropriate dielectric material. In some embodiments, the liner layer 310, the isolation layer 280, and / or the dielectric layer 210 include the same material (e.g., oxide). In some embodiments, the formation of the electrode layer 320 uses a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other appropriate deposition processes. The electrode layer 320 may include a semiconductor material (e.g., polysilicon), a metal, or other appropriate conductive material. In some embodiments, the electrode layer 320 , the conductive plug 260 , the bottom electrode layer 300 , the first conductive layer 130 , the second conductive layer 170 and / or the barrier layer 190 (or the barrier structure 195 ) include the same material, such as polysilicon.

[0112] In some embodiments, a polishing process (e.g., a chemical mechanical polishing process) is performed to remove excess material of the liner layer 310 and / or the electrode layer 320. For example, the isolation layer 280 is used as an etch stop layer to perform the polishing process so that the top surface of each contact structure CS (i.e., the top surface 321 of the electrode layer 320 and the top surface 311 of the liner layer 310) is substantially coplanar with the top surface 281 of the isolation layer 280.

[0113] In some embodiments, the contact structure CS is disposed on the sidewalls of the gate layer 330, the sidewalls of the dielectric layer 210, the sidewalls of the barrier layer 190, and the sidewalls of the second conductive layer 170. In other words, the contact structure CS passes through the gate layer 330, the dielectric layer 210, the barrier layer 190, and the second conductive layer 170 downward. In addition, for the step region SR, each of the contact structures CS has a portion embedded in the first conductive layer 130. In some embodiments, the liner layer 310 is configured to separate the electrode layer 320 from the gate layer 330 to avoid electrical contact between the electrode layer 320 and the gate layer 330. The electrode layer 320 of the contact structure CS is electrically connected to the bottom electrode layer 300 above the array region AR, and the electrode layer 320 of the contact structure CS is electrically connected to the first conductive layer 130 above the step region SR.

[0114] In some embodiments, the memory device 100 includes a substrate 110, a bottom source structure BS, a gate layer 330, a dielectric layer 210, a contact structure CS, and a pillar structure 270. The gate layer 330 and the dielectric layer 210 are alternately stacked above the bottom source structure BS. The contact structure CS passes through the gate layer 330 and the dielectric layer 210 downward and extends to the bottom source structure BS. The pillar structure 270 passes through the gate layer 330 and the dielectric layer 210 downward and extends to the bottom source structure BS. The bottom source structure BS is disposed above the substrate 110, and the bottom source structure BS includes a bottom electrode layer 300, a first conductive layer 130, a dielectric stack structure DS, a second conductive layer 170, a barrier layer 190, and a barrier structure 195. Fig. 14C Schematically shows Fig.14A FIG. 1 is a cross-sectional view of the memory device 100 above the step region SR taken along line segment S2-S2'. In some embodiments, as Fig. 14C As shown, the dielectric stack structure DS is laterally located between two adjacent pillar structures 270 along the second direction D2. The barrier structure 195 of the bottom source structure BS is laterally located between one of the pillar structures 270 and one of the contact structures CS along the second direction D2. In other words, for the step region SR, the dielectric stack structure DS surrounds each of the pillar structures 270, and the barrier structure 195 surrounds each of the contact structures CS.

[0115] In some embodiments, Fig. 14CAs shown, each of the contact structures CS includes an upper portion CSU and a lower portion CSL. For the step region SR, the upper portion CSU is disposed in the isolation layer 280, the dielectric layer 210, and the gate layer 330, and the lower portion CSL is disposed in the barrier layer 190, the second conductive layer 170, the barrier structure 195, and the first conductive layer 130. For the step region SR, the lower portion CSL contacts the barrier structure 195 and is surrounded by the barrier structure 195. Specifically, for the step region SR, two opposite sidewalls of the lower portion CSL of each of the contact structures CS contact the barrier structure 195.

[0116] In some embodiments, Fig. 14C As shown, each of the pillar structures 270 includes an upper portion 270U and a lower portion 270L. The upper portion 270U is disposed in the dielectric layer 210 and the gate layer 330, and the lower portion 270L is disposed in the barrier layer 190, the second conductive layer 170, the dielectric stack structure DS, and the first conductive layer 130. The lower portion 270L contacts the dielectric stack structure DS and is surrounded by the dielectric stack structure DS. Each of the pillar structures 270 has a top surface 271 below the top surface 281 of the isolation layer 280 and a bottom surface 275 below the top surface 131 of the first conductive layer 130. In some embodiments, the bottom surface 275 of the pillar structure 270 is below the bottom surface DS2 of the dielectric stack structure DS. In some embodiments, the dielectric stack structure DS of the bottom source structure BS is laterally located between the lower portion CSL of one of the contact structures CS and the lower portion 270L of one of the pillar structures 270 along the second direction D2.

[0117] In some embodiments, Fig. 14B and Fig. 14CAs shown, the dielectric stack structure DS is vertically located between the first conductive layer 130 and the second conductive layer 170 along a direction perpendicular to a plane defined by the first direction D1 and the second direction D2. The blocking structure 195 is vertically located between the first conductive layer 130 and the second conductive layer 170 along a direction perpendicular to a plane defined by the first direction D1 and the second direction D2. The blocking structure 195 is laterally adjacent to the dielectric stack structure DS along the second direction D2. In some embodiments, for the step region SR, each of the blocking structures 195 contacts the sidewall DS1 of the dielectric stack structure DS and the sidewall of one of the contact structures CS. Specifically, for the step region SR, two opposite sidewalls of each of the blocking structures 195 contact the lower portion CSL of one of the dielectric stack structure DS and the contact structure CS, respectively. In some embodiments, for the step region SR, each of the blocking structures 195 contacts the lower portion CSL of one of the contact structures CS and is separated from the lower portion 270L of one of the pillar structures 270. In other words, the blocking structure 195 and the pillar structure 270 are separated by the dielectric stack structure DS. In some embodiments, the dielectric stack structure DS contacts one of the blocking structures 195 and one of the pillar structures 270. Fig. 14B As shown, the dielectric stack structure DS contacts the lower portion 270L of each of the pillar structures 270 and is separated from the lower portion CSL of each of the contact structures CS. In other words, the dielectric stack structure DS is separated from the contact structure CS by the barrier structure 195. The dielectric stack DS laterally abuts the barrier structure 195.

[0118] In some embodiments, Fig. 14B As shown, the memory device 100 further includes a memory structure MS above the array region AR. The memory structure MS passes downward through the dielectric layer 210, the gate layer 330, the barrier layer 190 and the second conductive layer 170 above the array region AR. The memory structure MS is separated from the pillar structure 270. In other words, the memory structure MS is disposed above the array region AR of the substrate 110, and the pillar structure 270 is disposed above the step region SR of the substrate 110. The bottom electrode layer 300 of the bottom source structure BS is electrically connected to the memory structure MS and the contact structure CS.

[0119] In some embodiments, Fig.14AAs shown, the memory structures MS are arranged in multiple rows along the second direction D2, wherein the memory structures MS can be regarded as vertical NAND memory strings. The contact structures CS extend along the first direction D1 above the array region AR and the step region SR. The array region AR includes the memory structures MS, and the step region SR includes the pillar structures 270. The contact structures CS are configured to divide the memory device 100 into a plurality of blocks. For example, the memory structures MS and the pillar structures 270 located between two adjacent contact structures CS are regarded as one block. In some embodiments, as Fig. 7A and Fig.14A As shown, the blocking structure 195 inherits the geometric shape of the opening O1. Specifically, the blocking structure 195 includes a first portion 195a corresponding to the first portion O1a of the opening O1 and a second portion 195b corresponding to the second portion O1b of the opening O1. That is, the profile of the first portion 195a of the blocking structure 195 is substantially the same as the profile of the first portion O1a of the opening O1, and the profile of the second portion 195b of the blocking structure 195 is substantially the same as the profile of the second portion O1b of the opening O1. In some embodiments, as Fig. 7A and Fig.14A As shown, the first portion 195a of the blocking structure 195 is disposed adjacent to a section of the contact structure CS along the first direction D1. The second portion 195b of the blocking structure 195 extends along a second direction D2 perpendicular to the first direction D1.

[0120] According to the above-mentioned embodiment of the present disclosure, since the dielectric stack structure surrounds each of the pillar structures and the blocking structure is arranged between one of the pillar structures and the contact structure, damage to the pillar structure during the etching process (for example, etching the dielectric stack to expose the channel layer of the memory structure) can be avoided or prevented, thereby avoiding deformation or collapse problems.

[0121] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached claims.

Claims

1. A memory device, comprising: a substrate; A bottom source structure is disposed on the substrate, wherein the bottom source structure comprises a bottom electrode layer, a dielectric stack structure and a blocking structure; A plurality of gate layers and a plurality of dielectric layers are alternately stacked on the bottom source structure; a contact structure extending through the gate layers and the dielectric layers to the bottom source structure; and A plurality of pillar structures pass through the gate layers and the dielectric layers and extend to the bottom source structure, wherein the dielectric stack structure of the bottom source structure surrounds each of the pillar structures, and wherein the blocking structure of the bottom source structure is disposed between one of the pillar structures and the contact structure. 2 . The memory device of claim 1 , wherein the blocking structure contacts the dielectric stack structure and the contact structure. 3 . The memory device according to claim 1 , wherein the bottom source structure further comprises a first conductive layer and a second conductive layer disposed on the first conductive layer, and the blocking structure is disposed between the first conductive layer and the second conductive layer. 4 . The memory device of claim 1 , wherein the contact structure extends along a first direction, and a first portion of the blocking structure is adjacent to a section of the contact structure along the first direction. 5 . The memory device of claim 4 , wherein the blocking structure further comprises a second portion, the second portion of the blocking structure extending along a second direction perpendicular to the first direction.

6. The memory device according to claim 1, further comprising: A memory structure passes through the gate layers and the dielectric layers above an array region, wherein the contact structure extends along the first direction above the array region and a step region including the pillar structures.

7. A memory device comprising: a substrate; A bottom source structure is disposed on the substrate, wherein the bottom source structure comprises a bottom electrode layer and a dielectric stack structure; A plurality of gate layers and a plurality of dielectric layers are alternately stacked on the bottom source structure; a contact structure extending through the gate layers and the dielectric layers to the bottom source structure; and A pillar structure passes through the gate layers and the dielectric layers and extends to the bottom source structure, wherein the dielectric stack structure of the bottom source structure is laterally located between a lower portion of the contact structure and a lower portion of the pillar structure. 8 . The memory device of claim 7 , wherein the bottom source structure further comprises a blocking structure, the blocking structure laterally adjacent to the dielectric stack structure. 9 . The memory device of claim 7 , wherein a bottom surface of the pillar structure is below a bottom surface of the dielectric stack structure.

10. A method for manufacturing a memory device, comprising: A first conductive layer, a dielectric stack structure and a second conductive layer are sequentially formed on a substrate, wherein the substrate has an array region and a step region; forming a barrier layer on the second conductive layer, wherein the barrier layer above the stepped region further passes through the second conductive layer and the dielectric stack structure; forming a plurality of dielectric layers and a plurality of sacrificial material layers alternately stacked on the barrier layer; forming a memory structure downwardly through the dielectric layers, the sacrificial material layers, the barrier layer, the second conductive layer and the dielectric stack structure above the array region, wherein the memory structure comprises a memory element and a channel layer on the memory element; forming a pillar structure downwardly passing through the dielectric layers, the sacrificial material layers, the barrier layer, the second conductive layer and the dielectric stack structure above the step region; forming a slit channel downwardly through the dielectric layers and the sacrificial material layers above the array region and the step region; Etching the barrier layer and the second conductive layer above the array region from the slit channel to expose the dielectric stack structure; Etching the dielectric stack structure and the memory element of the memory structure above the array region to expose the channel layer of the memory structure; forming a bottom electrode layer electrically connected to the channel layer of the memory structure; replacing the sacrificial material layers with a plurality of gate layers; as well as A contact structure is formed in the slit trench.

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