Manufacturing method of TMBS semiconductor device for reducing electric noise

Abstract

The invention relates to the technical field of semiconductor device manufacturing, and provides a TMBS semiconductor device manufacturing method for reducing electric noise, which is characterized by comprising the following steps: selecting a semiconductor material as a TMBS substrate, and forming an oxide layer on the surface of the semiconductor substrate by using chemical vapor deposition, the position of a groove is defined on the oxide layer by using a photoetching technology, the groove is etched on the oxide layer by using a reactive ion technology, a metal MOS grid electrode is formed, the bottom oxide layer, in contact with the groove, of the metal MOS grid electrode is completely covered with a protective layer, 20%-50% of the side wall oxide layer is covered with the protective layer, a TMBS chip is arranged on the TMBS substrate, and packaging and fixing are carried out by using a packaging material. According to the invention, the bottom oxide layer and the side wall oxide layer are reasonably covered by the protective layer, the electric field distribution is optimized, and the noise caused by a non-uniform electric field in the manufacturing process of the TMBS semiconductor device is reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to a TMBS semiconductor device manufacturing method for reducing electrical noise. Background Art

[0002] TMBS (trench MOS barrier Schottky rectifier) ​​is a power device that introduces a trench MOS gate structure. It reduces the electric field strength at the Schottky barrier by utilizing the "charge coupling" effect, thereby reducing the forward conduction voltage drop and obtaining a lower reverse leakage current.

[0003] However, with the development of electronic devices towards miniaturization and high integration, the control of electrical noise becomes particularly important, because electrical noise can significantly affect the integrity of signals and the performance of devices. Adding a protective layer to TMBS semiconductors can effectively shield external electromagnetic interference (EMI and RFI) and reduce the impact of these interferences on the performance of semiconductor devices. However, the local protection of the protective layer still has defects, such as weak areas caused by incomplete coverage or uneven deposition of the protective layer, resulting in weak electrical noise reduction effect, and electric field concentration leading to failure or leakage of the protective layer. Summary of the invention

[0004] In view of the above-mentioned defects of the prior art, the present invention proposes a method for manufacturing a TMBS semiconductor device for reducing electrical noise. The technical solution steps designed by the present invention include:

[0005] S10: Selecting a semiconductor material as a TMBS substrate;

[0006] S20: forming an oxide layer on the surface of the semiconductor substrate by chemical vapor deposition;

[0007] S30: using photolithography technology to define the position of the groove on the oxide layer;

[0008] S40: etching a groove in the oxide layer using reactive ion technology;

[0009] S50: forming a metal MOS gate inside the trench;

[0010] S60: depositing a protective layer in the region of the bottom oxide layer and the sidewall oxide layer contacting the metal MOS gate;

[0011] S70: placing a TMBS chip on the TMBS substrate, and wrapping and fixing the chip with a packaging material;

[0012] Preferably, the S60 includes:

[0013] The protective layer material is vertically deposited on the bottom oxide layer of the metal MOS gate contact using a physical vapor deposition method, so that the protective layer completely covers the bottom oxide layer;

[0014] The protective layer material is deposited at an oblique angle on the sidewall oxide layer of the metal MOS gate contact using physical vapor deposition, so that the protective layer partially covers the sidewall oxide layer, with a coverage rate between 20% and 50%.

[0015] Preferably, the semiconductor material in S10 includes but is not limited to silicon, gallium arsenide and gallium nitride.

[0016] Preferably, the material of the oxide layer in S20 is silicon dioxide.

[0017] Preferably, the S50 includes:

[0018] Use physical vapor deposition to evenly deposit metal material on the sidewalls and bottom of the trench, use photolithography to form a photoresist pattern on the deposited metal to define the specific position of the metal MOS gate, and use reactive ion etching to remove the metal area not covered by the photoresist to form a metal MOS gate.

[0019] Preferably, the metal material is aluminum.

[0020] Preferably, the material of the protective layer in S60 includes but is not limited to silicon nitride and aluminum oxide.

[0021] Preferably, the depositing of the protective layer in S60 includes:

[0022] The protective layer material is deposited using physical vapor deposition, a photoresist pattern is formed on the deposited protective layer using photolithography technology to define the specific position of the protective layer, and reactive ion etching is used to remove the protective layer material not protected by the photoresist to form a protective layer.

[0023] Preferably, the step of obliquely depositing the protective layer material on the sidewall oxide layer contacting the metal MOS gate comprises:

[0024] The experimental data and simulation data of the sidewall oxide layer at different deposition angles were recorded, and the predicted coverage of the sidewall oxide layer at each deposition angle was calculated using the following formula:

[0025]

[0026] In the formula, is the predicted coverage of condition j at deposition angle i, The sigmoid function is used to map the output to the interval [0, 1]. and are two different support vector machine models, is the weight, and are the experimental data set and the simulated data set respectively;

[0027] From the experimental data set and simulated data sets Extracting coexisting sedimentation angle data sets , the formula is as follows:

[0028]

[0029] exist The preset condition J and the set of deposition angles with predicted coverage between 0.2 and 0.5 are retained, and the formula is as follows:

[0030]

[0031] Preferably, the step of providing the TMBS chip on the TMBS substrate in S70 includes:

[0032] Metal wiring is made on the surfaces of two or more TMBS chips, and semi-elliptical crack solder joints are set up on the metal wiring. The TMBS chips are connected to the solder joints of the TMBS chips in the upper layer and / or the next layer through the solder joints. The TMBS chips are also connected to the corresponding pins on the TMBS substrate through the solder joints.

[0033] Preferably, the crack length of the semi-elliptical crack weld is 5 , the crack depth is 1 .

[0034] Beneficial effects:

[0035] 1. The present invention uses physical vapor deposition to perform vertical deposition and oblique angle deposition to cover the bottom oxide layer and the sidewall oxide layer with reasonable protective layers, optimize the electric field distribution, and reduce the noise caused by the uneven electric field;

[0036] 2. The present invention combines experimental data and simulation data, and performs calculation and prediction through support vector machine model and sigmoid function, so as to more accurately analyze and predict the coverage of the sidewall oxide layer, calculate the predicted coverage of the sidewall oxide layer at each deposition angle, and help select the best deposition angle, thereby optimizing the quality and performance of the sidewall oxide layer;

[0037] 3. The present invention realizes interconnection by adding metal wiring and semi-elliptical crack solder joints in the chip. Compared with traditional direct welding, the new solder joint design reduces the defects that may occur during the welding process, reduces the overall failure rate, and improves the yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1It is a flow chart of a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in detail below. The following embodiments are implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0040] The present invention provides a method for manufacturing a TMBS semiconductor device for reducing electrical noise, such as Figure 1 As shown, the technical solution includes the following steps, specifically including:

[0041] S10: Selecting a semiconductor material as a TMBS substrate;

[0042] S20: forming an oxide layer on the surface of the semiconductor substrate by chemical vapor deposition;

[0043] S30: using photolithography technology to define the position of the groove on the oxide layer;

[0044] S40: etching a groove in the oxide layer using reactive ion technology;

[0045] S50: forming a metal MOS gate inside the trench;

[0046] S60: depositing a protective layer in the region of the bottom oxide layer and the sidewall oxide layer contacting the metal MOS gate;

[0047] S70: placing a TMBS chip on the TMBS substrate, and wrapping and fixing the chip with a packaging material;

[0048] Preferably, the S60 includes:

[0049] The protective layer material is vertically deposited on the bottom oxide layer of the metal MOS gate contact using a physical vapor deposition method, so that the protective layer completely covers the bottom oxide layer;

[0050] The protective layer material is deposited at an oblique angle on the sidewall oxide layer of the metal MOS gate contact using physical vapor deposition, so that the protective layer partially covers the sidewall oxide layer, with a coverage rate between 20% and 50%.

[0051] Specifically, the vertical deposition of the bottom oxide layer of the metal MOS gate contact to completely cover the protective layer material includes: using a thickness monitor (such as an optical thickness gauge or QCM) to monitor the thickness of the deposition in real time. Adjust the deposition rate and time according to the real-time data to ensure full coverage of the bottom of the gate. The oblique deposition of the sidewall oxide layer to partially cover the protective layer material includes: using a scanning electron microscope (SEM) to observe the thickness and coverage of the film layer, and depositing the sidewall oxide layer for a shorter time to control the coverage rate between 20% and 50%.

[0052] In addition, the bottom oxide layer of the metal MOS gate contact is completely covered with a protective layer, and the sidewall oxide layer is deposited at an oblique angle to partially cover the protective layer. This protective layer wrapping method can form a diode junction with the area between the bottom of the gate and the drain after the groove is etched. This protective layer wrapping strategy can form a contact interface with the area between the bottom of the gate and the drain after the groove is etched (drift region), thereby effectively isolating the high electric field area and protecting the gate insulation layer from the influence of high electric field pressure. By completely separating the high electric field tolerance area from the gate insulation layer, the risk of premature failure of the gate insulation layer is reduced. At the same time, the protective layer makes the electric field more evenly distributed between the metal oxide semiconductor field effect transistor (MOSFET) gate and the protective layer by enhancing the auxiliary depletion effect on the drift region, thereby improving the breakdown voltage of the device and ensuring that the device has better reliability under high voltage conditions.

[0053] Preferably, the semiconductor material in S10 includes but is not limited to silicon, gallium arsenide and gallium nitride.

[0054] Preferably, the material of the oxide layer in S20 is silicon dioxide.

[0055] Preferably, S50 includes:

[0056] Use physical vapor deposition to evenly deposit metal material on the sidewalls and bottom of the trench, use photolithography to form a photoresist pattern on the deposited metal to define the specific position of the metal MOS gate, and use reactive ion etching to remove the metal area not covered by the photoresist to form a metal MOS gate.

[0057] Preferably, the metal material is aluminum.

[0058] Preferably, the material of the protection layer in S60 includes but is not limited to silicon nitride and aluminum oxide.

[0059] Preferably, depositing a protective layer in S60 includes:

[0060] The protective layer material is deposited using physical vapor deposition, a photoresist pattern is formed on the deposited protective layer using photolithography technology to define the specific position of the protective layer, and reactive ion etching is used to remove the protective layer material not protected by the photoresist to form a protective layer.

[0061] Preferably, the step of obliquely depositing the protective layer material on the sidewall oxide layer of the metal MOS gate contact comprises:

[0062] The experimental data and simulation data of the sidewall oxide layer at different deposition angles were recorded, and the predicted coverage of the sidewall oxide layer at each deposition angle was calculated using the following formula:

[0063]

[0064] In the formula, is the predicted coverage of condition j at deposition angle i, The sigmoid function is used to map the output to the interval [0, 1]. and are two different support vector machine models, is the weight, and are the experimental data set and the simulated data set respectively;

[0065] From the experimental data set and simulated data sets Extracting coexisting sedimentation angle data sets , the formula is as follows:

[0066]

[0067] exist The preset condition J and the set of deposition angles with predicted coverage between 0.2 and 0.5 are retained, and the formula is as follows:

[0068]

[0069] Specifically, is the coverage of condition j at deposition angle i, where condition j includes but is not limited to deposition parameters (such as deposition rate, deposition time and material type), experimental conditions (base temperature and pressure) and simulation conditions (simulation assumptions and model parameters).

[0070] In addition, before the oblique angle deposition of the sidewall oxide layer, the and Training includes collecting experimental data sets and simulation data sets, where the experimental data sets include deposition angles and corresponding actual sidewall oxide layer coverage, and the simulation data sets include deposition angles and corresponding simulated sidewall oxide layer coverage; determining appropriate features or attributes to describe the sidewall oxide layer situation, i.e., condition j; using the SVM regression algorithm to train the first model for the experimental data set , train the second model using the SVM regression algorithm on the simulated data set Among them, by combining experimental data and simulation prediction data, and calculating and predicting through support vector machine model and sigmoid function, the coverage of the sidewall oxide layer can be analyzed and predicted more accurately. The predicted coverage of the sidewall oxide layer at each deposition angle can help select the best deposition angle, thereby optimizing the quality and performance of the sidewall oxide layer. According to the preset conditions and the requirements for predicted coverage, the sidewall oxide layer can be predicted at the intersection. The set of deposition angles that meet the conditions is screened out, thereby determining the deposition angle range that best suits the experimental and simulation conditions.

[0071] Preferably, the step of providing the TMBS chip on the TMBS substrate in S70 includes:

[0072] Metal wiring is made on the surfaces of two or more TMBS chips, and semi-elliptical crack solder joints are set up on the metal wiring. The TMBS chips are connected to the solder joints of the TMBS chips in the upper layer and / or the next layer through the solder joints. The TMBS chips are also connected to the corresponding pins on the TMBS substrate through the solder joints.

[0073] Preferably, the crack length of the semi-elliptical crack weld is 5 , the crack depth is 1 .

[0074] Specifically, in chip stacking technology, direct welding may cause alignment errors and a high welding failure rate, and the design and area utilization issues of each layer of chips make it impossible to manufacture TSV for welding at each position. Therefore, the present invention realizes interconnection by adding metal wiring and semi-elliptical crack solder joints in the chip, wherein the metal wiring is a multi-layer metal wire used to connect the internal circuit and external pins of the TMBS chip. Reduce alignment errors: The use of metal wiring allows for more flexible layout, thereby reducing alignment errors caused by direct welding. This method makes the connection between chips more stable and reliable. Reduce welding failure rate: Compared with traditional direct welding, the new solder joint design reduces the defects that may occur during the welding process, reduces the overall failure rate, and improves the yield rate. The design of the semi-elliptical crack solder joint not only improves the mechanical strength, but also optimizes the electrical performance and ensures the stability of signal transmission.

[0075] In addition to the connection between chips, the soldering points of the TMBS chips also need to be connected to the pins on the substrate. This means that all stacked TMBS chips need to be connected to the corresponding pins on the substrate through their respective soldering points to ensure that the signal can be transmitted from the chip to the external circuit.

[0076] The preferred specific embodiments of the present invention are described in detail above. It should be understood that ordinary technicians in the field can make many modifications and changes based on the concept of the present invention without creative work. Therefore, all technical solutions that can be obtained by technicians in the technical field based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A method for manufacturing a TMBS semiconductor device for reducing electrical noise, characterized in that: The following steps are involved: S10: Selecting a semiconductor material as a TMBS substrate; S20: forming an oxide layer on the surface of the semiconductor substrate by chemical vapor deposition; S30: using photolithography technology to define the position of the groove on the oxide layer; S40: etching a groove in the oxide layer using reactive ion technology; S50: forming a metal MOS gate inside the trench; S60: depositing a protective layer in the region of the bottom oxide layer and the sidewall oxide layer contacting the metal MOS gate; S70: placing a TMBS chip on the TMBS substrate, and wrapping and fixing the chip with a packaging material; The S60 includes: The protective layer material is vertically deposited on the bottom oxide layer of the metal MOS gate contact using a physical vapor deposition method, so that the protective layer completely covers the bottom oxide layer; The protective layer material is deposited at an oblique angle on the sidewall oxide layer of the metal MOS gate contact using physical vapor deposition, so that the protective layer partially covers the sidewall oxide layer, with a coverage rate between 20% and 50%.

2. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 1, characterized in that: The semiconductor material in S10 includes but is not limited to silicon, gallium arsenide and gallium nitride.

3. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 1, characterized in that: The material of the oxide layer in S20 is silicon dioxide.

4. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 1, characterized in that: The S50 includes: Use physical vapor deposition to evenly deposit metal material on the sidewalls and bottom of the trench, use photolithography to form a photoresist pattern on the deposited metal to define the specific position of the metal MOS gate, and use reactive ion etching to remove the metal area not covered by the photoresist to form a metal MOS gate.

5. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 4, characterized in that: The metal material is aluminum.

6. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 1, characterized in that: The material of the protective layer in S60 includes, but is not limited to, silicon nitride and aluminum oxide.

7. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 6, characterized in that: The depositing of the protective layer in S60 includes: The protective layer material is deposited using physical vapor deposition, a photoresist pattern is formed on the deposited protective layer using photolithography technology to define the specific position of the protective layer, and reactive ion etching is used to remove the protective layer material not protected by the photoresist to form a protective layer.

8. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 7, characterized in that: The step of obliquely depositing the protective layer material on the sidewall oxide layer of the metal MOS gate contact comprises: The experimental data and simulation data of the sidewall oxide layer at different deposition angles were recorded, and the predicted coverage of the sidewall oxide layer at each deposition angle was calculated using the following formula: ; In the formula, is the predicted coverage of condition j at deposition angle i, The sigmoid function is used to map the output to the interval [0, 1]. and are two different support vector machine models, is the weight, and are the experimental data set and the simulated data set respectively; From the experimental data set and simulated data sets Extracting coexisting sedimentation angle data sets , the formula is as follows: ;exist The preset condition J and the set of deposition angles with predicted coverage between 0.2 and 0.5 are retained, and the formula is as follows:

9. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 1, characterized in that: The step of arranging the TMBS chip on the TMBS substrate in S70 includes: Metal wiring is made on the surfaces of two or more TMBS chips, and semi-elliptical crack solder joints are set up on the metal wiring. The TMBS chips are connected to the solder joints of the TMBS chips in the upper layer and / or the next layer through the solder joints. The TMBS chips are also connected to the corresponding pins on the TMBS substrate through the solder joints.

10. A method for manufacturing a TMBS semiconductor device for reducing electrical noise according to claim 9, characterized in that: The crack length of the semi-elliptical crack weld is 5 , the crack depth is 1 .

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