Gallium nitride device and preparation method thereof

Abstract

The embodiment of the invention provides a gallium nitride device and a preparation method thereof, the gallium nitride device comprises an epitaxial layer, a gate electrode is arranged on the epitaxial layer, a plurality of Y-shaped nano channels are arranged in the epitaxial layer below the gate electrode, and the plurality of Y-shaped nano channels are formed by two rows of wedge-shaped grooves which are oppositely arranged. According to the embodiment of the invention, at least the problems that the linearity of the device is improved by adopting a double-channel coupling mode in related technologies, the realization difficulty is high, and the linearity of the device in an application level is easy to degrade are solved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular, to a gallium nitride device and a method for preparing the same. Background Art

[0002] As the third generation wide bandgap compound semiconductor devices, GaN HEMTs (High Electron Mobility Transistors) have significant performance advantages in the millimeter wave field. Especially driven by the 5G technology industry, millimeter wave GaN devices have broad application prospects in large-capacity ultra-high-speed mobile communications, high-resolution imaging radars, and secure communications. However, while achieving higher application frequencies, the linearity problem of the device has become increasingly serious.

[0003] In order to solve the linearity problem, researchers have conducted research on device-level GaN HEMT high linearity technology. Among them, the mainstream solutions are to start from modulating the carrier velocity field relationship under the device gate or improving the device gate-source capacitance morphology. For example, Fin HEMT is a structure that integrates Fins of different widths in the gate width direction. Its gate-source capacitance continues to increase with the gate voltage, compensating for the trend of carrier mobility decrease under large gate voltage, so that a larger transconductance gate voltage swing can be achieved, significantly improving the device linearity; dual-channel HEMT is a new channel introduced to compensate for the mobility degradation of the first channel, using the coupling between the two channels to suppress the nonlinear change of the access resistance, thereby increasing the output third order intercept point (Output 3rd order intercept point, referred to as OIP3) of the device. MIS HEMT is a dielectric layer added to the GaN HEMT, which can effectively increase the distance between the gate and the device channel, slow down the mobility degradation trend of the channel two-dimensional electron gas (two Dimensional Electron Gas, referred to as 2DEG) under large gate voltage, and thus improve the linearity of the device.

[0004] However, for high-frequency communication systems, these technical solutions have more or less fatal flaws. For example, the parasitic capacitance newly introduced by the three-dimensional fin structure of Fin-HEMT will become non-negligible under large current bias points, seriously affecting the frequency characteristics of the device; dual-channel devices need to be designed to the limit of performance based on specific material properties to achieve the coupling of the two channels, otherwise the currents of the two channels will not be able to grow linearly, but will lead to the degradation of the linearity of the device at the application level; the MIS structure will introduce new interface parasitics, affecting the reliability of the device. Therefore, it is very important to realize a high-linearity technical solution with small parasitic introduction, low implementation difficulty, and easy large-scale application to meet the requirements of modern communication systems for high speed, high precision, and high reliability.

[0005] In summary, there is no good solution to the problem that the dual-channel coupling method used in related technologies to improve device linearity is difficult to implement and easily leads to linearity degradation of the device at the application level. Summary of the invention

[0006] The embodiments of the present application provide a gallium nitride device and a method for preparing the same, so as to at least solve the problem in the related art that the dual-channel coupling method is used to improve the linearity of the device, which is difficult to implement and easily leads to linearity degradation of the device at the application level.

[0007] According to one embodiment of the present application, a gallium nitride device is provided, which includes an epitaxial layer, a gate electrode is arranged on the epitaxial layer, and a plurality of Y-shaped nanochannels are provided in the epitaxial layer below the gate electrode, wherein the plurality of Y-shaped nanochannels include two rows of wedge-shaped grooves arranged opposite to each other.

[0008] According to another embodiment of the present application, a method for preparing a gallium nitride device is provided, the method comprising: preparing an epitaxial layer, a source electrode, and a drain electrode; preparing a plurality of Y-shaped nanochannels on an upper surface of the epitaxial layer, wherein the plurality of Y-shaped nanochannels include two rows of wedge-shaped grooves arranged opposite to each other; and preparing a gate electrode above the plurality of Y-shaped nanochannels.

[0009] According to another embodiment of the present application, a chip is provided. The chip includes the gallium nitride device described in any one of the embodiments of the present application.

[0010] In the embodiment of the present application, a Y-shaped nanochannel formed by two rows of wedge-shaped grooves arranged opposite to each other is arranged in the epitaxial layer below the gate electrode. This can solve the problem that the dual-channel coupling method used in the related art to improve the linearity of the device is difficult to implement and easily leads to linearity degradation of the device at the application level. By controlling the channel path in stages under different gate biases, the linearity of the device can be significantly improved, and it has the advantages of simplicity, high efficiency, energy saving, and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional structural diagram of a gallium nitride device according to an embodiment of the present application;

[0012] Figure 2 is a top view of the Y-shaped nanochannel of an embodiment of the present application;

[0013] Figure 3 is a schematic diagram of the overall structure of a gallium nitride device according to an embodiment of the present application;

[0014] Figure 4 is a schematic cross-sectional structure diagram of a gallium nitride device according to an embodiment of the present application;

[0015] Figure 5 is a schematic diagram of a top view structure of a gallium nitride device according to an embodiment of the present application;

[0016] Figure 6 is a schematic diagram of the working principle of a gallium nitride device according to an embodiment of the present application;

[0017] Figure 7 is a schematic diagram of the working principle of a Y-shaped nanochannel according to an embodiment of the present application;

[0018] Figure 8 is a schematic diagram of the working principle of the gate electrode according to an embodiment of the present application;

[0019] Fig. 9 is a flow chart of a method for preparing a gallium nitride device according to an embodiment of the present application;

[0020] Fig.10 This is a flow chart of the key process for preparing a gallium nitride device according to an embodiment of the present application;

[0021] Fig.11 It is a schematic diagram of the key process preparation flow of the gallium nitride device according to the embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] A gallium nitride device is provided in an embodiment of the present application, in particular a gallium nitride high electron mobility transistor (GaN HEMT) device.

[0025] Figure 1 is a cross-sectional structural diagram of a gallium nitride device according to an embodiment of the present application. Figure 1 As shown, the GaN device includes the following structure:

[0026] The epitaxial layer 10 is provided with a gate electrode 20 , and the epitaxial layer 10 below the gate electrode has a plurality of Y-shaped nano-channels, wherein the plurality of Y-shaped nano-channels include two rows of wedge-shaped grooves 30 arranged opposite to each other.

[0027] In this embodiment, the epitaxial layer may include an epitaxial material (eg, a channel layer, a barrier layer) and an isolation material (eg, a passivation layer).

[0028] Figure 2is a top view of the Y-shaped nanochannel of an embodiment of the present application, such as Figure 2 As shown, the Y-shaped nanochannel is formed by two rows of wedge-shaped grooves 30 arranged opposite to each other.

[0029] In some embodiments, two rows of wedge-shaped grooves are arranged in parallel, and each wedge-shaped groove 30 consists of two parts: a pointed groove and a rectangular groove. The adjacent side of the two rows of wedge-shaped grooves is a pointed groove, and the non-adjacent side is a rectangular groove.

[0030] In some embodiments, the shapes and sizes of the multiple wedge-shaped grooves in the same row are the same, and the present application does not limit the shapes and sizes of the wedge-shaped grooves in different rows.

[0031] In the embodiment of the present application, by setting a Y-shaped nanochannel, the movement path of electrons can be spatially limited, the mutual scattering interference between electrons in the channel is reduced, the nonlinear factors caused by scattering are suppressed, and the linearity characteristics of the device are improved. This can solve the problem that the dual-channel coupling method used in the related technology to improve the linearity of the device is difficult to implement and easily leads to linearity degradation of the device at the application level.

[0032] Figure 3 is a schematic diagram of the overall structure of a gallium nitride device according to an embodiment of the present application, such as Figure 3 As shown, the GaN device also includes the following structures:

[0033] A source electrode 40 and a drain electrode 50 .

[0034] In some embodiments, a source electrode and a drain electrode are respectively disposed at two ends of the epitaxial layer 10 , and the plurality of Y-shaped nanochannels are located on a side close to the source electrode.

[0035] In some embodiments, the wedge-shaped groove 30 includes: a plurality of first grooves 31 and a plurality of second grooves 32 , wherein the plurality of first grooves 31 are located on a side close to the source electrode, and the plurality of second grooves 32 are located on a side close to the drain electrode.

[0036] In some embodiments, the epitaxial layer 10 includes, from bottom to top, a substrate layer 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15. The source electrode 40 and the drain electrode 50 are located on the upper surface of the barrier layer 14, the first trench 31 extends into the channel layer and cuts off the two-dimensional electron gas in the channel layer, and the second trench 32 extends to the upper surface of the barrier layer.

[0037] In some embodiments, a side where the first groove and the second groove are adjacent to each other is a pointed groove, and a side where the first groove and the second groove are not adjacent to each other is a rectangular groove.

[0038] In some embodiments, the multiple first grooves are staggered with the multiple second grooves, wherein the pointed grooves of each first groove and the two adjacent second grooves are staggered and opposed, and the epitaxial layer materials between the grooves can form a Y-shaped nanochannel, and the pointed grooves of each second groove and the two adjacent first grooves are staggered and opposed, and the epitaxial layer materials between the grooves can also form a Y-shaped nanochannel.

[0039] In this embodiment, by providing two rows of wedge-shaped grooves of different depths, segmented multiplexing of the Y-shaped nanochannel can be achieved under different gate biases, further ensuring the linearity of the gallium nitride device under different gate biases.

[0040] In some embodiments, the gate electrode structure can be adjusted according to the application scenario. For example, the gate electrode can be a floating T-shaped gate structure. Furthermore, a floating T-shaped gate structure with a V-shaped groove can be used in a high-frequency environment.

[0041] The embodiment of the present application designs a millimeter-wave device with local stress modulation under the gate, and utilizes the different stress releases under the gate by gradually varying in-situ SiN grooves to achieve multi-threshold voltage regulation in the gate width direction and transconductance profile compensation of the multi-threshold device, thereby significantly improving the linearity of the device. At the same time, the parasitic capacitance is reduced by combining a floating T-type gate structure with low insertion loss, effectively combining the two key technical means of high frequency and high linearity, so that the device can achieve high linearity applications within a higher frequency band.

[0042] Figure 4 is a schematic diagram of a cross-sectional structure of a gallium nitride device according to an embodiment of the present application, such as Figure 4 As shown, the root of the gate electrode 20 extends to the inside of the wedge-shaped groove.

[0043] In some embodiments, the width of the first trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length of the gate electrode, and the length of the first trench is 2 / 3 to 1 of the gate length; the root of the gate electrode close to the source electrode covers part of the tip of the first trench.

[0044] In some embodiments, the width of the second trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length of the gate electrode, and the length of the second trench is 2 / 3 to 1 / 2 of the gate length; the root of the gate electrode close to the drain electrode covers the entire second trench.

[0045] In one embodiment, the metal at the root of the gate electrode fills the pointed groove of the first groove, the pointed groove of the second groove and the rectangular groove, and the gap position (epitaxial layer material) between the metal at the root of the gate electrode forms a Y-shaped nanochannel. Under different gate voltages, the gate electrode can realize the switching control of the Y-shaped nanochannel through the depletion effect of the metal material on the surrounding epitaxial layer material.

[0046] In some embodiments, a metal interconnection layer is further disposed on the source electrode and the drain electrode.

[0047] In some embodiments, the material of the substrate layer includes at least one of the following: SiC, sapphire, Si, GaN.

[0048] In some embodiments, the material of the buffer layer includes at least one of the following: GaN, AlGaN, AlN.

[0049] In some embodiments, the material of the channel layer includes at least one of the following: GaN, InGaN.

[0050] In some embodiments, the material of the barrier layer includes at least one of the following: AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-face GaN.

[0051] In some embodiments, the material of the passivation layer includes at least one of the following: SiN, SiO2, Al2O3, AlN, TaO, and LaO.

[0052] Furthermore, if the barrier layer is set to be thin, it may not be possible to generate sufficient two-dimensional electron gas (2DEG) through polarization with the buffer layer. In this case, the polarization of the barrier layer can be enhanced by setting an appropriate thickness of in-situ SiN above the barrier layer.

[0053] In the embodiment of the present application, by introducing a Y-shaped nanochannel formed by a three-dimensional wedge-shaped groove and a three-dimensional gate electrode, the distribution and movement of carriers in the device can be effectively modulated in stages, intermodulation distortion and nonlinear characteristics can be reduced, and the design of a high-linearity power amplifier can be realized. The system's digital pre-distortion (DPD) for the linearity of the power amplifier module is reduced, which is an indicator of the input cost and design pressure.

[0054] Figure 5 is a schematic diagram of a top view of a gallium nitride device according to an embodiment of the present application, such as Figure 5 As shown, the root of the metal gate electrode covers part of the first trench and the entirety of the second trench.

[0055] In this embodiment, the gate metal in the first trench is equivalent to a buried metal in the bulk material, and its depletion range for the material is larger than that of a conventional planar gate structure. By arranging the gate metal in the trench, the gallium nitride device can have a better off state.

[0056] Figure 6 is a schematic diagram of the working principle of the gallium nitride device according to an embodiment of the present application, such as Figure 6As shown in the figure, the working principle of GaN devices can be divided into the following three states under different gate bias voltages:

[0057] The intermediate state includes the first trench opening stage and the trench sidewall modulation stage, and the fully open state is the second trench opening stage.

[0058] In this embodiment, each stage is described from the perspectives of the cross-sectional view of section A, section B, and the top view. Figure 6 The A section in Figure 3 The cross-sectional view at the position marked by section A in the middle is used to indicate the depletion range of the gate metal in the first trench. Figure 6 The B section in Figure 3 The cross-sectional view at the position marked by section B is used to indicate the depletion range of the gate metal in the second trench.

[0059] In this embodiment, the dotted line figuratively indicates the depletion range of the gate metal inside the material. Due to the basic characteristics of metal-semiconductor, as the gate voltage bias gradually changes from negative to positive, the depletion range of the gate metal inside the material gradually shrinks, and its depletion depth (width) gradually relaxes, causing the device to turn on until saturation.

[0060] In this embodiment, the first groove at the cross section A is spatially limited by the gate metals on both sides to define the movement path of electrons, thereby reducing the mutual scattering interference between electrons in the channel, suppressing the nonlinear factors caused by scattering, and improving the linearity characteristics of the device.

[0061] In this embodiment, the first trench at the cross section A reduces the effective channel size under the gate due to trench etching, which enables the current output capability of the GaN device to always remain at a stage where the source resistance is relatively small, suppresses the trend of increasing nonlinear source resistance caused by the space charge limitation effect in the active region, and further improves the linearity of the GaN device.

[0062] In this embodiment, the second groove at section B forms a nanochannel directly below the gate through the depletion effect of the planar gate. This gate depletion effect can release the depletion of the channel below it in a timely manner as the gate bias voltage becomes positive and the device tends to saturate, thereby reducing the active area resistance on the gate drain side in parallel, and to a certain extent, reducing the space charge limitation effect in the channel again, further improving the linearity of the device.

[0063] In this embodiment, with the opening of the second groove, the movement space of the electrons on the gate source side is smaller than the movement space of the electrons on the gate drain side, which leads to the electron concentration on the gate source side being much higher than the electron concentration on the gate drain side. The concentration difference on both sides provides the power for the electron movement to diffuse. When the device current is close to saturation, this concentration difference can also provide acceleration for the electrons in the channel in the direction of electron movement (source to drain), thereby reducing the transit time under the gate and improving the frequency response of the device.

[0064] Figure 7 Schematic diagram of the working principle of the Y-shaped nanochannel according to an embodiment of the present application. Figure 7 As shown, the Y-shaped nanochannel can be divided into nanochannel 1 (source side) and nanochannel 2 (drain side).

[0065] In this embodiment, when the GaN device gradually enters the fully open state from the intermediate state, the nanochannel 2 is completely released, the electron concentration on the gate source side is much higher than the electron concentration on the gate drain side, and the concentration difference on both sides provides diffusion power for the electron movement.

[0066] Furthermore, when the GaN device enters the fully-on state and the device current approaches saturation, this concentration difference can provide acceleration for electrons in the channel in the direction of electron movement (source to drain), reduce the transit time under the gate, and improve the frequency response of the device, which also ensures that GaN devices can meet higher frequency applications.

[0067] Figure 8 is a schematic diagram of the working principle of the gate electrode according to an embodiment of the present application, such as Figure 8 As shown, the upper part is the gate electrode structure in the embodiment of the present application, the root of the gate electrode on the side close to the source electrode goes deep into the first trench, and the lower part is a planar gate structure.

[0068] In this embodiment, the gate metal in the first trench is equivalent to a buried metal in the bulk material, and its depletion range for the material is larger than that of a conventional planar gate structure, so that the gallium nitride device can have a better off state.

[0069] In this embodiment, under the same driving voltage, compared with the planar gate structure, the gate electrode structure in the embodiment of the present application can block the source-drain current path deeper in the material when the device is in the off state, thereby making the gallium nitride device in the embodiment of the present application have a smaller device off state and stronger high-voltage stability.

[0070] According to another embodiment of the present application, a method for preparing a gallium nitride device is also provided, which is used to prepare the gallium nitride device in any of the above embodiments.

[0071] Fig. 9 is a flow chart of a method for preparing a gallium nitride device according to an embodiment of the present application, such as Fig. 9 As shown, the process mainly includes the following steps:

[0072] Step S1, preparing an epitaxial layer, a source electrode and a drain electrode, and generating a passivation layer between the source electrode and the drain electrode to obtain an intermediate sample;

[0073] Step S2, preparing a plurality of Y-shaped nanochannels on the upper surface of the intermediate sample, wherein the plurality of Y-shaped nanochannels include two rows of wedge-shaped grooves arranged opposite to each other;

[0074] Step S3, preparing a gate electrode above the plurality of Y-shaped nanochannels.

[0075] In some embodiments, the epitaxial layer includes, from bottom to top, a substrate layer, a buffer layer, a channel layer, and a barrier layer. The passivation layer is disposed on the barrier layer to isolate and protect the epitaxial layer.

[0076] In some embodiments, the preparation of the epitaxial layer, the source electrode and the drain electrode in step S1 may include the following steps:

[0077] Step S101, sequentially growing a buffer layer, a channel layer, and a barrier layer on a substrate layer;

[0078] Step S102 , forming ohmic contacts at two ends of the barrier layer by an ohmic injection process or an ohmic annealing process to obtain the source electrode and the drain electrode.

[0079] In some embodiments, the wedge-shaped groove includes a plurality of first grooves and a plurality of second grooves.

[0080] Further, step S2 may include the following steps:

[0081] Step S201, etching the passivation layer on a side close to the source electrode by an inductively coupled plasma-reactive ion etching (ICP-RIE) process, and cutting off the etching process to the inside of the channel layer to form the plurality of first grooves;

[0082] Step S202 , etching the passivation layer adjacent to the first trench and close to the drain electrode by the ICP-RIE process, and stopping at the upper surface of the barrier layer to form the plurality of second trenches.

[0083] In some embodiments, step S3 may include: photolithographically forming a floating T-type gate structure above the multiple first grooves and the multiple second grooves, and forming a gate electrode by an electron beam evaporation process, wherein the root of the gate electrode close to the source electrode side fills part of the first groove, and the root of the gate electrode close to the drain electrode side completely fills the second groove.

[0084] In some embodiments, step S101 may include: sequentially growing the buffer layer, the channel layer, and the barrier layer on the substrate layer by a Metal-Organic Chemical Vapor Deposition (MOCVD) process or a Molecular Beam Epitaxy (MBE) process.

[0085] Furthermore, after step S101, the method may also include: when the thickness of the barrier layer is less than a preset value, growing in-situ SiN on the barrier layer to enhance the polarization of the barrier layer; when the thickness of the barrier layer is greater than or equal to the preset value, depositing SiN by a plasma enhanced chemical vapor deposition (PECVD) process to protect the barrier layer.

[0086] In this embodiment, the preset value is used to determine the thickness of the barrier layer. If the barrier layer is set to be thin (i.e., the thickness of the barrier layer is less than the preset value), it will not be able to generate enough two-dimensional electron gas (2DEG) through polarization with the buffer layer. Exemplarily, the preset value can be set to 8nm, but the present application is not limited thereto.

[0087] In some embodiments, after step S3, the method may further include:

[0088] Step S4, photolithography and evaporation of a metal interconnection layer provided on the source electrode and the drain electrode;

[0089] Step S5, leading out the source electrode, the drain electrode and the gate electrode through a peripheral interconnection process;

[0090] Step S6, grounding the gallium nitride device through a through-hole process.

[0091] Fig.10 is a flow chart of the key process of preparing the gallium nitride device according to the embodiment of the present application, such as Fig.10 As shown, the process includes the following steps:

[0092] Step S1001, growing epitaxial material by MOCVD or MBE;

[0093] Step S1002, fabricating source and drain electrodes on the epitaxial substrate;

[0094] Step S1003, making active area isolation;

[0095] Step S1004, preparing a Y-shaped nanochannel;

[0096] Step S1005, gate metal evaporation;

[0097] Step S1006, photolithography and evaporation of a metal interconnection layer.

[0098] In this embodiment, in step S1001 , an insertion layer, a buffer layer, a channel layer, and a barrier layer may be sequentially grown on the substrate layer by a metal organic chemical vapor deposition process or a molecular beam epitaxy process.

[0099] In some embodiments, if the barrier layer in step S1001 is too thin to generate sufficient two-dimensional electron gas (2DEG) through polarization with the buffer layer, the polarization of the barrier layer can be enhanced by providing an appropriate thickness of in-situ SiN on the barrier layer. If the barrier layer is of conventional thickness, SiN can be deposited by a plasma enhanced chemical vapor deposition (PECVD) process to protect the barrier layer.

[0100] In some embodiments, the active area isolation in step S1003 is equivalent to the passivation layer in the above embodiments, which is used to passivate and protect the material.

[0101] In some embodiments, step S1004 of preparing the Y-shaped nanochannel may include: first trench photolithography, etching the first trench to the cache layer, second trench photolithography, and etching the second trench to the surface of the barrier layer.

[0102] The gallium nitride device preparation process in the embodiment of the present application is highly compatible with the process of conventional GaN HEMT devices, is simple to implement, and can achieve high linearity characteristics at low cost.

[0103] Fig.11 is a schematic diagram of the key process flow of preparing a gallium nitride device according to an embodiment of the present application, such as Fig.10 As shown in the figure, during the preparation process, the cross section of the GaN device changes from Fig.11 (a) changes to Fig.11 (f).

[0104] In this embodiment, if Fig.11 As shown in (a), the process sequentially grows an insertion layer (not shown in the figure), a buffer layer, a channel layer and a barrier layer on a substrate (substrate layer).

[0105] In some embodiments, the substrate material is one of SiC, sapphire or Si, the buffer layer is one of GaN, AlGaN or AlN, the channel layer is one of GaN and InGaN, and the barrier layer can be AlGaN or InAlN, AlN, ScAlN and other materials; if there are special needs, in-situ SiN can also be grown during the epitaxial material growth to enhance the material properties.

[0106] In this embodiment, if Fig.11 As shown in (b), an ohmic contact (source electrode and drain electrode) can be prepared by selecting an ohmic injection or annealing process according to needs.

[0107] In some embodiments, the ohmic implantation process may include: photolithography of source and drain implantation patterns, and implantation of a certain dose of Si ions, and then photolithography of source and drain metal patterns, followed by thermal annealing activation treatment to form ohmic contacts.

[0108] In some embodiments, the annealing ohmic process may include: photolithography of source and drain patterns and deposition of source and drain metals, followed by thermal annealing to form ohmic contacts.

[0109] In this embodiment, if Fig.11 As shown in (c), the material needs to be passivated for protection.

[0110] In some embodiments, the passivation layer material includes but is not limited to SiN, SiO2, Al2O3, AlN, TaO, LaO and other dense materials, and the thickness of the passivation layer is preferably 10 to 60 nm.

[0111] In this embodiment, if Fig.11 As shown in (d), an inductively coupled plasma-reactive ion etching (ICP-RIE) process can be used to etch the source side under the gate and cut off inside the channel layer to form a first trench, thereby realizing a first type of nanochannel;

[0112] In some embodiments, the width of the first trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length, and the length is 2 / 3 to 1 of the gate length, and the gate root only covers a portion of the tip of the first trench.

[0113] In some embodiments, the etching depth of the first trench may extend downward by twice the distance from the surface of the barrier layer with reference to the thickness of the barrier layer.

[0114] In this embodiment, if Fig.11 As shown in (e), an inductively coupled plasma-reactive ion etching (ICP-RIE) process can be used to etch the drain side under the gate and cut off at the surface of the barrier layer to form a second groove, realize a second nano-channel, and form a Y-shaped nano-channel on the material together with the first groove.

[0115] In some embodiments, the width of the second trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length, and the length is 1 / 3 to 1 / 2 of the gate length, and the gate root will achieve full metal coverage of the second trench.

[0116] In some embodiments, the second trench etches only the passivation layer within the pattern and stops at the upper surface of the barrier layer;

[0117] In some embodiments, after etching, the sample may be placed in a tetramethylammonium hydroxide (TMAH) solution to repair the etching damage.

[0118] In this embodiment, if Fig.11 As shown in (f), a floating T-type gate structure can be photolithographically formed above the first trench and the second trench, and then gate metal is evaporated to form a floating T-type gate with low insertion loss. The gate metal fills part of the first trench to achieve gate control enhancement of the nanochannel and completely fills the second trench to achieve staged control of the channel.

[0119] In some embodiments, the process further includes performing a peripheral interconnection process to lead out electrodes, performing a through-hole process to ground the device, and completing the final preparation of the device.

[0120] The gallium nitride device prepared by the embodiment of the present application has the advantages of being simple, easy to use, highly efficient, energy-saving, and low-cost. It can save the circuit area of ​​the pre-distortion circuit module, reduce costs, reduce implementation difficulty, and improve the overall performance of the base station.

[0121] According to yet another embodiment of the present application, a chip is provided. The chip includes the gallium nitride device described in any one of the above embodiments.

[0122] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0123] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A gallium nitride device, characterized in that: The gallium nitride device comprises an epitaxial layer, a gate electrode is arranged on the epitaxial layer, and a plurality of Y-shaped nano-channels are provided in the epitaxial layer below the gate electrode, wherein the plurality of Y-shaped nano-channels comprise two rows of wedge-shaped grooves arranged opposite to each other.

2. The gallium nitride device according to claim 1, characterized in that: A source electrode and a drain electrode are respectively disposed at two ends of the epitaxial layer, and the plurality of Y-shaped nanochannels are located on a side close to the source electrode.

3. The gallium nitride device according to claim 2, characterized in that: The wedge-shaped groove includes: a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are located on a side below the gate electrode close to the source electrode, and the plurality of second grooves are located on a side below the gate electrode close to the drain electrode.

4. The gallium nitride device according to claim 3, characterized in that: The epitaxial layer includes from bottom to top: a channel layer, a barrier layer and a passivation layer, wherein the source electrode and the drain electrode are located on the upper surface of the barrier layer, the first trench extends into the channel layer, and the second trench extends to the upper surface of the barrier layer.

5. The gallium nitride device according to claim 3, characterized in that: The wedge-shaped groove consists of a pointed groove and a rectangular groove, the side where the first groove and the second groove are adjacent is the pointed groove, and the side where the first groove and the second groove are not adjacent is the rectangular groove.

6. The gallium nitride device according to claim 5, characterized in that: The plurality of first grooves are arranged alternately with the plurality of second grooves.

7. The gallium nitride device according to claim 5, characterized in that: The width of the first trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length of the gate electrode, and the length of the first trench is 2 / 3 to 1 of the gate length; The root of the gate electrode close to the source electrode covers a portion of the tip of the first trench.

8. The gallium nitride device according to claim 5, characterized in that: The width of the second trench in the gate width direction is 1 / 3 to 1 / 2 of the gate length of the gate electrode, and the length of the second trench is 2 / 3 to 1 / 2 of the gate length; The root of the gate electrode on the side close to the drain electrode covers the entire second trench.

9. The gallium nitride device according to claim 1, characterized in that: The gate electrode is a floating T-type gate structure.

10. The gallium nitride device according to claim 2, characterized in that: A metal interconnection layer is provided on the source electrode and the drain electrode.

11. The gallium nitride device according to claim 4, characterized in that: The material of the channel layer includes at least one of the following: GaN, InGaN; The material of the barrier layer includes at least one of the following: AlGaN, AlN, InAlN, ScAlN, InAlGaN, N-face GaN; The material of the passivation layer includes at least one of the following: SiN, SiO2, Al2O3, AlN, TaO, and LaO.

12. A method for preparing a gallium nitride device, characterized in that: The method comprises: preparing an epitaxial layer, a source electrode and a drain electrode, and generating a passivation layer between the source electrode and the drain electrode to obtain an intermediate sample; Preparing a plurality of Y-shaped nanochannels on the upper surface of the intermediate sample, wherein the plurality of Y-shaped nanochannels include two rows of wedge-shaped grooves arranged opposite to each other; A gate electrode is formed above the plurality of Y-shaped nano-channels.

13. The method according to claim 12, characterized in that The epitaxial layer includes from bottom to top: a substrate layer, a buffer layer, a channel layer and a barrier layer. The epitaxial layer, a source electrode and a drain electrode are prepared, including: Growing the buffer layer, the channel layer and the barrier layer in sequence on the substrate layer; Ohmic contacts are formed at two ends of the barrier layer by an ohmic injection process or an ohmic annealing process to obtain the source electrode and the drain electrode.

14. The method according to claim 13, characterized in that The wedge-shaped groove includes a plurality of first grooves and a plurality of second grooves, and a plurality of Y-shaped nano-channels are prepared on the upper surface of the intermediate sample, including: Etching the passivation layer on the side close to the source electrode by an inductively coupled plasma-reactive ion etching (ICP-RIE) process, and cutting off at the inside of the channel layer to form the plurality of first grooves; and / or, The ICP-RIE process is used to etch the passivation layer adjacent to the first trench and close to the drain electrode, and the etching is stopped at the upper surface of the barrier layer to form the plurality of second trenches.

15. The method according to claim 12, characterized in that The wedge-shaped groove includes a plurality of first grooves and a plurality of second grooves, and a gate electrode is prepared above the plurality of Y-shaped nano-channels, including: A floating T-type gate structure is photolithographically formed above the multiple first grooves and the multiple second grooves, and a gate electrode is formed by an electron beam evaporation process, wherein a root of the gate electrode close to the source electrode side fills a portion of the first groove, and a root of the gate electrode close to the drain electrode side completely fills the second groove.

16. The method according to claim 13, characterized in that The buffer layer, the channel layer and the barrier layer are sequentially grown on the substrate layer, comprising: The buffer layer, the channel layer and the barrier layer are sequentially grown on the substrate layer by a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process.

17. The method according to claim 16, characterized in that After sequentially growing the buffer layer, the channel layer, and the barrier layer on the substrate layer, the method further includes: When the thickness of the barrier layer is less than a preset value, in-situ SiN is grown on the barrier layer to enhance the polarization of the barrier layer; When the thickness of the barrier layer is greater than or equal to a preset value, SiN is deposited by a plasma enhanced chemical vapor deposition (PECVD) process to protect the barrier layer.

18. The method according to claim 12, characterized in that After preparing gate electrodes above the plurality of Y-shaped nanochannels, the method further comprises: Photolithography and evaporation of a metal interconnection layer disposed on the source electrode and the drain electrode; Leading out the source electrode, the drain electrode and the gate electrode through a peripheral interconnection process; The GaN device is grounded through a via process.

19. A chip, characterized in that: The chip comprises the gallium nitride device described in any one of claims 1 to 11.

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