Transistor and manufacturing method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a transistor and a manufacturing method thereof, a memory and electronic equipment. The invention relates to the technical field of semiconductors. The transistor includes a gate, a ferroelectric layer, and an active layer. The grid electrode is arranged on one side of the substrate. The ferroelectric layer covers the gate and the substrate. The active layer is arranged on the side, away from the substrate, of the ferroelectric layer, and the material of the active layer comprises metal oxide. The active layer is made of metal oxide, and compared with the active layer made of a silicon-containing material, the problem of device degradation is effectively solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a transistor and a manufacturing method thereof, a memory and an electronic device. Background Art

[0002] At present, ferroelectric transistors (FeFETs) have attracted extensive attention from academia and industry due to their advantages such as fast read and write speed, low power consumption, high integration potential, and non-volatility. Memories containing FeFETs have multiple functions and tunable properties, and have broad application prospects in low-power sensors, non-volatile data storage, and emerging artificial synapses. Summary of the invention

[0003] In view of the shortcomings of the existing methods, the present application proposes a transistor and a manufacturing method thereof, a memory and an electronic device to solve the technical problem of reduced fatigue characteristics or retention characteristics of the existing transistors.

[0004] In a first aspect, an embodiment of the present application provides a transistor, including:

[0005] A gate is disposed on one side of the substrate;

[0006] A ferroelectric layer covering the gate;

[0007] The active layer is arranged on a side of the ferroelectric layer away from the substrate; the material of the active layer includes metal oxide.

[0008] Optionally, the ferroelectric layer includes a contact layer in contact with the active layer, and a body layer other than the contact layer; and an oxygen vacancy concentration of the contact layer is lower than an oxygen vacancy concentration of the body layer.

[0009] Optionally, the body layer and the contact layer are an integrated structure, and both the body layer and the contact layer contain metal oxide ferroelectric materials;

[0010] The contact layer further comprises anions, wherein the anions form chemical bonds with the metal in the contact layer, and the bond energy between the anions and the metal in the contact layer is greater than the bond energy between the metal and oxygen in the bulk layer.

[0011] Optionally, the metal oxide ferroelectric material of the body layer and the contact layer includes hafnium oxide containing a doping element, and the doping element includes at least one of zirconium, silicon, yttrium, aluminum, and lanthanum;

[0012] The bond energy of the chemical bond between the anion and the hafnium ion in the contact layer is greater than the bond energy of the hafnium oxygen bond in the hafnium oxide in the body layer.

[0013] Optionally, the metal in the metal oxide of the active layer includes at least one of indium, zinc, tin and gallium.

[0014] Optionally, the anion comprises a fluoride ion.

[0015] In some embodiments, a transistor is provided, comprising:

[0016] Gate;

[0017] Semiconductor layer;

[0018] The ferroelectric layer is located between the gate and the semiconductor layer; wherein the material of the semiconductor layer includes metal oxide.

[0019] In some embodiments, the ferroelectric layer comprises a metal oxide;

[0020] The region of the semiconductor layer in contact with the ferroelectric layer contains anions, and the bond energy of the chemical bond formed between the anions and the metal in the metal oxide of the ferroelectric layer is greater than the bond energy between the metal in the metal oxide and oxygen.

[0021] In some embodiments, the ferroelectric layer is a hafnium-based ferroelectric layer, and the anions are F ions.

[0022] In a second aspect, an embodiment of the present application provides a memory, comprising: a transistor as described in any of the above embodiments.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, including: the above-mentioned memory.

[0024] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a transistor, comprising:

[0025] forming a gate and a ferroelectric layer in sequence on one side of the substrate;

[0026] An active layer is formed on a side of the ferroelectric layer away from the gate, and a material of the active layer includes metal oxide.

[0027] Optionally, a gate and a ferroelectric layer are sequentially formed on one side of the substrate, comprising:

[0028] forming an isolation layer on one side of the substrate, and sequentially forming a gate, a ferroelectric layer and a sacrificial layer on the isolation layer;

[0029] doping a plasma containing fluorine ions into the sacrificial layer;

[0030] Annealing the entire substrate to form a ferroelectric phase of the ferroelectric layer; at the same time, diffusing the fluorine ions to the contact interface between the ferroelectric layer and the sacrificial layer to obtain chemical bonds between the fluorine ions and the metal ions in the ferroelectric layer, thereby forming a contact layer of the ferroelectric layer;

[0031] removing the sacrificial layer;

[0032] And, an active layer is formed on a side of the ferroelectric layer away from the gate, wherein the material of the active layer comprises a metal oxide, including:

[0033] A metal oxide is deposited on the contact layer of the ferroelectric layer to form an active layer.

[0034] Optionally, the material of the sacrificial layer includes at least one of titanium, tungsten, ruthenium and gallium.

[0035] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0036] The material of the active layer of the transistor is metal oxide, which will not be oxidized by the oxygen source introduced when manufacturing the ferroelectric layer, avoiding the formation of an interface layer with a low dielectric constant at the contact interface between the ferroelectric layer and the active layer, thereby improving the device performance of the transistor.

[0037] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0039] Figure 1 A schematic cross-sectional view of a film layer of a transistor provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a process for manufacturing a transistor provided in an embodiment of the present application;

[0041] Figure 3 A schematic cross-sectional view of a film layer obtained after manufacturing an isolation layer on one side of a substrate in a method for manufacturing a transistor provided in an embodiment of the present application;

[0042] Figure 4 A schematic cross-sectional view of a film layer obtained after manufacturing a gate on a side of an isolation layer away from a substrate in a method for manufacturing a transistor provided in an embodiment of the present application;

[0043] Figure 5 A schematic cross-sectional view of a film layer obtained after a ferroelectric layer and a sacrificial layer are sequentially formed on a side of a gate away from an isolation layer in a method for manufacturing a transistor provided in an embodiment of the present application;

[0044] Figure 6A schematic diagram of a film cross-section when fluorine ion plasma is injected into a sacrificial layer in a transistor manufacturing method provided in an embodiment of the present application;

[0045] Figure 7 In a method for manufacturing a transistor provided in an embodiment of the present application, an annealing process is performed on the entire substrate to form a ferroelectric phase of the ferroelectric layer; at the same time, fluorine ions are diffused to the contact interface between the ferroelectric layer and the sacrificial layer to obtain chemical bonds between the fluorine ions and the metal ions in the ferroelectric layer, and a cross-sectional schematic diagram of the film layer obtained after forming a contact layer of the ferroelectric layer;

[0046] Figure 8 A schematic diagram of a cross-section of a film layer obtained after removing a sacrificial layer in a method for manufacturing a transistor provided in an embodiment of the present application.

[0047] Description of reference numerals:

[0048] 1- substrate;

[0049] 2-gate;

[0050] 3- ferroelectric layer; 31- contact layer; 32- bulk layer;

[0051] 4- Active layer;

[0052] 51-first source / drain; 52-second source / drain;

[0053] 6-Isolation layer;

[0054] 71 - sacrificial layer; 72 - plasma of fluoride ions. DETAILED DESCRIPTION

[0055] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0056] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0058] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0059] In the embodiment of the present application, the transistor containing the ferroelectric layer, the active layer or the semiconductor layer adopts a metal oxide semiconductor material, and the ferroelectric layer will not be oxidized by the oxygen source introduced during the manufacture. Compared with the semiconductor layer being a Si semiconductor, the formation of an interface layer with a low dielectric constant at the contact interface between the ferroelectric layer and the metal oxide layer can be effectively avoided, thereby improving the device performance.

[0060] In some embodiments, the gate and the ferroelectric layer are formed first and then the metal oxide semiconductor layer is formed, which can effectively avoid the influence of high-temperature manufacturing of the gate and the ferroelectric layer on the performance of the metal oxide semiconductor layer.

[0061] The transistor can be a planar transistor or a vertical transistor. The semiconductor layer and the gate can be stacked up and down, or the semiconductor layer surrounds the gate or the gate surrounds the semiconductor layer. The gate can extend horizontally or vertically relative to the substrate.

[0062] In some embodiments, a transistor includes: a gate; a semiconductor layer; a ferroelectric layer located between the gate and the semiconductor layer; wherein the material of the semiconductor layer includes a metal oxide. In some embodiments, the ferroelectric layer includes a metal oxide; the region where the semiconductor layer contacts the ferroelectric layer includes anions, and the bond energy of the chemical bond formed between the anions and the metal in the metal oxide of the ferroelectric layer is greater than the bond energy between the metal and oxygen in the metal oxide.

[0063] Exemplarily, the ferroelectric layer is a hafnium-based ferroelectric layer, and the anions are fluorine (F) ions.

[0064] Taking a planar transistor as an example, an embodiment of the present application provides a transistor, the structural diagram of which is shown in FIG. Figure 1 As shown, it includes a gate 2, a ferroelectric layer 3 and an active layer 4.

[0065] The gate 2 is disposed on one side of the substrate 1 .

[0066] The ferroelectric layer 3 covers the gate 2 .

[0067] The active layer 4 is disposed on a side of the ferroelectric layer 3 away from the substrate 1 , and the material of the active layer 4 includes metal oxide.

[0068] In the related art, the active layer is commonly made of silicon or silicon germanium, and the transistor is a top-gate structure. When the ferroelectric layer of the transistor is deposited, the oxygen source introduced causes the surface of the active layer to be oxidized, and an interface layer with a low dielectric constant is formed at the contact interface between the ferroelectric layer and the active layer. The interface layer generates a strong electric field, which will aggravate the injection of charges from the active layer into the ferroelectric layer, resulting in the formation of defective morphology of the ferroelectric layer, thereby affecting the performance of the memory, especially the fatigue characteristics and retention characteristics.

[0069] In the present application, the material of the active layer 4 of the transistor is metal oxide, which will not be oxidized by the oxygen source introduced when manufacturing the ferroelectric layer 3, thereby avoiding the formation of an interface layer with a low dielectric constant at the contact interface between the ferroelectric layer 3 and the active layer 4, thereby improving the fatigue characteristics and retention characteristics of the transistor and enhancing customer confidence.

[0070] The transistor of the present application is a back-gate structure, and the gate is made first and then the metal oxide layer is made, which can prevent the active layer from being in a high temperature environment when the gate is made. In some embodiments, the ferroelectric layer is made first and then the active layer is made, which can prevent the active layer from being in a high temperature environment when the ferroelectric layer is made, which is beneficial to protecting the active layer.

[0071] Optionally, the metal in the metal oxide of the active layer 4 includes at least one of indium, zinc, tin and gallium.

[0072] Specifically, the metal oxide may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO ... Titanium dioxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials, as long as the electrical performance of the transistor meets the requirements, the specific details can be adjusted according to the actual situation.

[0073] The above-mentioned metal oxides only emphasize the element type of the material, but do not emphasize the atomic proportion in the material and the film quality of the material.

[0074] It should be noted that the oxygen source includes at least one of oxygen, ozone and water vapor.

[0075] Optionally, the material of the gate 2 includes at least one of titanium nitride (TiN), ruthenium (Ru), tungsten (W), platinum (Pt), tantalum nitride (TaN) and P-type silicon.

[0076] Alternatively, if Figure 1 As shown, the ferroelectric layer 3 includes a contact layer 31 in contact with the active layer 4 , and a body layer 32 other than the contact layer 31 ; the oxygen vacancy concentration of the contact layer 31 is lower than that of the body layer 32 .

[0077] In this embodiment, the oxygen vacancy concentration of the contact layer 31 is lower than that of the body layer 32, which is beneficial to reducing the interface state density of the contact layer 31, avoiding aggravating the carrier injection into the ferroelectric layer 3, and improving the fatigue resistance and retention characteristics of the transistor.

[0078] Optionally, the body layer 32 and the contact layer 31 are an integrated structure, and both the body layer 32 and the contact layer 31 contain metal oxide ferroelectric materials.

[0079] The contact layer 31 further includes anions, which form chemical bonds with the metal in the contact layer 31 . The bond energy between the anions and the metal in the contact layer 31 is greater than the bond energy between the metal and oxygen in the bulk layer 32 .

[0080] In the related art, direct contact between the active layer and the ferroelectric layer will lead to a high interface state density at the contact interface, especially a high oxygen vacancy concentration, which will aggravate the entry of carriers in the active layer into the ferroelectric layer, thereby causing performance degradation of the transistor.

[0081] In this embodiment, the anions are injected during the process of manufacturing the ferroelectric layer 3. By injecting anions from the outside during the manufacture of the ferroelectric layer 3, the anions are combined with the metal ions in the contact layer 31 of the ferroelectric layer 3 to form chemical bonds, which can passivate the oxygen vacancies at the contact interface between the ferroelectric layer 3 and the active layer 4, which is beneficial to reducing the interface state density of the contact interface, and further beneficial to improving the performance of the transistor.

[0082] Optionally, the anion comprises a fluoride ion.

[0083] In this embodiment, the anions are fluoride ions, which can occupy oxygen vacancies. In addition, hafnium fluoride formed by fluoride ions and hafnium ions reduces the oxygen vacancies in the contact layer 31. The bond energy of hafnium fluoride is greater than that of hafnium oxide, which can increase the valence band step and is beneficial to improving the performance of the transistor.

[0084] Optionally, the metal oxide ferroelectric material of the contact layer 31 and the body layer 32 includes hafnium oxide containing doping elements, and the doping elements include at least one of zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), and lanthanum (La).

[0085] The bond energy of the chemical bond between the anion and the hafnium ion in the contact layer 31 is greater than the bond energy of the hafnium oxygen bond in the hafnium oxide in the body layer 32 .

[0086] In this embodiment, the bond energy of the chemical bond between the anion and the hafnium ion in the contact layer 31 is greater than the bond energy of the hafnium oxygen bond in hafnium oxide, which can make the chemical bond between the anion and the metal ion in the contact layer 31 more stable and help increase the valence band step, thereby helping to improve the performance of the transistor.

[0087] Moreover, the bond energy of the chemical bond between the anion in the contact layer 31 and the hafnium ion is greater than the bond energy of the hafnium oxygen bond in the hafnium oxide in the body layer 32, so that the valence band offset (VBO) between the material of the active layer 4 and the material of the contact layer 31 increases, that is, the valence band offset between the material of the active layer 4 and the material of the contact layer 31 is greater than the valence band offset between the material of the active layer 4 and the material of the body layer 32. This can improve the durability of the transistor.

[0088] Specifically, the valence band gap between the metal oxide of the active layer 4 and the contact layer 31 is not less than 0.4 electron volts.

[0089] The valence band offset can be understood as follows: when semiconductors and semiconductors, or insulators and semiconductors contact to form an interface structure, discontinuous steps will be formed at the bottom of the conduction band and the top of the valence band of the materials on both sides, namely, the band offset. The band offset at the bottom of the conduction band is called the conduction band offset (CBO), and the band offset at the top of the valence band is called the valence band offset (VBO).

[0090] Optionally, the transistor further includes a first source / drain 51 and a second source / drain 52 , and the active layer 4 is disposed between the first source / drain 51 and the second source / drain 52 .

[0091] In this embodiment, the first source / drain 51 may be a source, and the second source / drain 52 may be a drain; or, the first source / drain 51 may be a drain, and the second source / drain 52 may be a source.

[0092] Optionally, the transistor further includes an isolation layer 6 , and the isolation layer 6 is located between the substrate 1 and the gate 2 .

[0093] In this embodiment, by providing an isolation layer between the substrate 1 and the gate 2, it is possible to prevent the gate 2 from short-circuiting. Specifically, the isolation layer 6 is made of silicon oxide.

[0094] The relative position between the semiconductor layer and the gate is not limited to the upper and lower stacking relationship. Taking the vertical transistor as an example, the semiconductor layer may surround the gate or the gate may surround the semiconductor layer. The surrounded gate or semiconductor may be columnar, and the extension direction of the columnar structure may be horizontal extension or vertical extension relative to the main surface of the substrate.

[0095] Based on the same inventive concept, an embodiment of the present application provides a memory including the transistor provided by the above embodiment.

[0096] In this embodiment, the memory uses any one of the transistors (FeFET) provided in the aforementioned embodiments. Please refer to the aforementioned embodiments for its principles and technical effects, which will not be repeated here.

[0097] The memory containing the FeFET in the present application can be understood as a memory based on a ferroelectric transistor. The memory can be applied to the fields of memory, flash memory, etc. The storage unit of the memory can be a 1T, 2T, 3T, 4T or 6T storage unit. The storage array of the memory can be a two-dimensional array, or a three-dimensional stacked array.

[0098] The 1T, 2T, 3T, 4T or 6T memory cell refers to the number of transistors contained in the memory cell. Taking the 1T memory cell and the 2T memory cell as examples, the 1T memory cell refers to a memory cell that contains only one transistor that serves as both a read and a write function. The 2T memory cell refers to a memory cell that contains one read transistor and one write transistor.

[0099] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the memory provided by the above embodiment.

[0100] In this embodiment, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0101] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0102] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.

[0103] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a transistor, the flow chart of the method is as follows Figure 2 As shown, the method comprises steps S1 and S2:

[0104] S1: A gate 2 and a ferroelectric layer 3 are sequentially formed on one side of a substrate 1.

[0105] S2: an active layer 4 is manufactured on a side of the ferroelectric layer 3 away from the gate 2. The material of the active layer 4 includes metal oxide.

[0106] Optionally, in the above step S1, forming the gate 2 and the ferroelectric layer 3 in sequence on one side of the substrate 1 includes:

[0107] An isolation layer 6 is formed on one side of the substrate 1 , and a gate 2 , a ferroelectric layer 3 and a sacrificial layer 71 are sequentially formed on the isolation layer 6 .

[0108] The sacrificial layer 71 is doped with a plasma 72 containing fluorine ions.

[0109] The entire substrate 1 is annealed to form a ferroelectric phase of the ferroelectric layer 3; at the same time, the fluorine ions are diffused to the contact interface between the ferroelectric layer 3 and the sacrificial layer 71 to obtain chemical bonds between the fluorine ions and the metal ions in the ferroelectric layer 3, thereby forming a contact layer 31 of the ferroelectric layer 3.

[0110] The sacrificial layer 71 is removed.

[0111] In this embodiment, the contact layer 31 includes chemical bonds formed by fluorine ions that can be combined with metal ions in the ferroelectric layer 3, which can passivate oxygen vacancies at the contact interface between the ferroelectric layer and the active layer, which is beneficial to reducing the interface state density of the contact interface, thereby helping to improve the performance of the transistor. At the same time, the transistor of the present application is a back-gate structure, which can avoid the metal oxide as the active layer 4 being in a high temperature environment when the ferroelectric layer 3 is manufactured, which is beneficial to protect the metal oxide active layer 4 from the influence of the high temperature environment.

[0112] Figure 3 is a schematic cross-sectional view of a film layer obtained after manufacturing an isolation layer 6 on one side of a substrate 1; Figure 4It is a schematic diagram of the film layer cross section obtained after manufacturing the gate 2 on the side of the isolation layer 6 away from the substrate 1. By manufacturing the isolation layer 6 between the substrate 1 and the gate 2, it is helpful to avoid a short circuit in the gate 2. The material of the substrate 1 can be silicon or silicon germanium. The material of the isolation layer 6 can be silicon dioxide, and its thickness is not less than 80 nanometers and not more than 120 nanometers. The manufacturing process can be deposited by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic layer deposition) or furnace (furnace tube thermal oxidation method), and the subsequent deposition method is the same and will not be repeated. Specifically, the material of the gate 2 includes at least one of titanium nitride (TiN), ruthenium (Ru), tungsten (W), platinum (Pt), tantalum nitride (TaN) and P-type silicon.

[0113] Figure 5 FIG. 3 is a schematic cross-sectional view of the film layer obtained after the ferroelectric layer 3 and the sacrificial layer 71 are sequentially manufactured on the side of the gate 2 away from the isolation layer 6. Figure 5 The ferroelectric layer 3 includes hafnium oxide containing doping elements, and the doping elements include at least one of zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), and lanthanum (La). Optionally, the material of the sacrificial layer 71 includes at least one of titanium (Ti), tungsten (W), ruthenium (Ru), and gallium (Ga). Specifically, the material of the sacrificial layer 71 includes titanium nitride (TiN) or gallium nitride (GaN).

[0114] Figure 6 It is a schematic diagram of the cross-section of the film layer when the plasma 72 containing fluorine ions is injected into the sacrificial layer 71.

[0115] Figure 7 The entire substrate 1 is subjected to an annealing process to form a ferroelectric phase of the ferroelectric layer 3; at the same time, the fluorine ions are diffused to the contact interface between the ferroelectric layer 3 and the sacrificial layer 71, and chemical bonds between the fluorine ions and the metal ions in the ferroelectric layer 3 are obtained to form a contact layer 31 of the ferroelectric layer 3. Figure 6 and Figure 7 The entire substrate 1 is annealed so that the ferroelectric layer 3 forms a ferroelectric phase, thereby obtaining the ferroelectric layer 3. At the same time, the anions diffuse from the sacrificial layer 71 to the contact interface between the sacrificial layer 71 and the ferroelectric layer 3, thereby obtaining the contact layer 31.

[0116] Figure 8 FIG. 4 is a schematic cross-sectional view of the film layer obtained after removing the sacrificial layer 71 .

[0117] Optionally, step S2 includes: depositing metal oxide on the contact layer 31 of the ferroelectric layer 3 to form the active layer 4 .

[0118] In this embodiment, after removing the sacrificial layer 71, the active layer 4 is manufactured on the side of the ferroelectric layer 3 away from the gate 2. Specifically, the active layer 4 is arranged on the side of the contact layer 31 of the ferroelectric layer 3 away from the gate 2, and the active layer 4 is not directly in contact with the body layer 32. Because the bond energy of the chemical bond between the anion in the contact layer 31 and the hafnium ion in the ferroelectric layer 3 is greater than the bond energy of the hafnium oxygen bond in hafnium oxide, the chemical bond between the anion and the metal ion in the ferroelectric layer 3 can be made more stable, and it is beneficial to increase the valence band order, thereby helping to improve the performance of the transistor.

[0119] Moreover, the material of the active layer 4 of the transistor is metal oxide, which will not be oxidized by the oxygen source introduced when manufacturing the ferroelectric layer 3, thereby avoiding the formation of an interface layer with a low dielectric constant at the contact interface between the ferroelectric layer 3 and the active layer 4, thereby improving the fatigue characteristics and retention characteristics of the transistor and enhancing customer confidence.

[0120] Optionally, after step S2 , the manufacturing method further comprises: respectively manufacturing a first source / drain 51 and a second source / drain 52 at two ends of the active layer 4 along a direction parallel to the substrate 1 .

[0121] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0122] 1. The material of the active layer of the transistor in the embodiment of the present application is metal oxide, which will not be oxidized by the oxygen source introduced when the ferroelectric layer is manufactured, thereby avoiding the formation of an interface layer with a low dielectric constant at the contact interface between the ferroelectric 3 and the active layer, thereby improving the fatigue characteristics and retention characteristics of the transistor and enhancing customer trust.

[0123] 2. In the embodiment of the present application, anions are injected from the outside when manufacturing the ferroelectric layer, so that the anions combine with the metal ions in the ferroelectric layer to form chemical bonds, which can passivate the oxygen vacancies at the contact interface between the ferroelectric layer and the active layer, which is beneficial to reducing the interface state density of the contact interface, and further beneficial to improving the performance of the transistor.

[0124] 3. In the embodiment of the present application, the bond energy of the chemical bond between the anion and the hafnium ion in the ferroelectric layer is greater than the bond energy of the hafnium oxygen bond in hafnium oxide, which can make the chemical bond between the anion and the metal ion in the ferroelectric layer more stable, and is beneficial to increase the valence band order, thereby helping to improve the performance of the transistor.

[0125] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0126] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0127] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0128] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0129] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0130] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0131] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A transistor, characterized in that: include: A gate is disposed on one side of the substrate; A ferroelectric layer covering the gate; An active layer, disposed on a side of the ferroelectric layer away from the substrate; The material of the active layer includes metal oxide.

2. The transistor according to claim 1, characterized in that The ferroelectric layer includes a contact layer contacting the active layer and a body layer except the contact layer; the oxygen vacancy concentration of the contact layer is lower than the oxygen vacancy concentration of the body layer.

3. The transistor according to claim 1, characterized in that The body layer and the contact layer are an integrated structure, and both the body layer and the contact layer contain metal oxide ferroelectric materials; The contact layer further comprises anions, wherein the anions form chemical bonds with the metal in the contact layer, and the bond energy between the anions and the metal in the contact layer is greater than the bond energy between the metal and oxygen in the bulk layer.

4. The transistor according to claim 3, characterized in that The metal oxide ferroelectric material of the body layer and the contact layer includes hafnium oxide containing a doping element, and the doping element includes at least one of zirconium, silicon, yttrium, aluminum, and lanthanum; The bond energy of the chemical bond between the anion and the hafnium ion in the contact layer is greater than the bond energy of the hafnium oxygen bond in the hafnium oxide in the body layer.

5. The transistor according to claim 3 or 4, characterized in that: The anion includes a fluoride ion.

6. The transistor according to claim 1, characterized in that The metal in the metal oxide of the active layer includes at least one of indium, zinc, tin and gallium.

7. A transistor, characterized in that: include: Gate; Semiconductor layer; The ferroelectric layer is located between the gate and the semiconductor layer; wherein the material of the semiconductor layer includes metal oxide.

8. The transistor according to claim 7, characterized in that The ferroelectric layer comprises a metal oxide; The region of the semiconductor layer in contact with the ferroelectric layer contains anions, and the bond energy of the chemical bond formed by the anions and the metal in the metal oxide of the ferroelectric layer is greater than the bond energy between the metal in the metal oxide of the ferroelectric layer and oxygen.

9. The transistor according to claim 8, characterized in that The ferroelectric layer is a hafnium-based ferroelectric layer, and the anions are fluoride ions.

10. A memory, characterized in that: The invention comprises a transistor as described in any one of claims 1 to 6, or a transistor as described in any one of claims 7 to 9.

11. An electronic device, characterized in that: Comprising the memory as claimed in claim 10.

12. A method for manufacturing a transistor, characterized in that: include: forming a gate and a ferroelectric layer in sequence on one side of the substrate; An active layer is formed on a side of the ferroelectric layer away from the gate, and a material of the active layer includes metal oxide.

13. The manufacturing method according to claim 12, characterized in that: A gate and a ferroelectric layer are sequentially formed on one side of the substrate, including: forming an isolation layer on one side of the substrate, and sequentially forming a gate, a ferroelectric layer and a sacrificial layer on the isolation layer; doping a plasma containing fluorine ions into the sacrificial layer; Annealing the entire substrate to form a ferroelectric phase of the ferroelectric layer; at the same time, diffusing the fluorine ions to the contact interface between the ferroelectric layer and the sacrificial layer to obtain chemical bonds between the fluorine ions and the metal ions in the ferroelectric layer, thereby forming a contact layer of the ferroelectric layer; removing the sacrificial layer; And, an active layer is formed on a side of the ferroelectric layer away from the gate, wherein the material of the active layer comprises a metal oxide, including: A metal oxide is deposited on the contact layer of the ferroelectric layer to form an active layer.

14. The manufacturing method according to claim 13, characterized in that: The material of the sacrificial layer includes at least one of titanium, tungsten, ruthenium and gallium.

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