Formation method of semiconductor structure
By removing the sacrificial layer in the channel region before forming the source and drain structure during the semiconductor structure formation process and setting up an isolation structure, the problems of source and drain structure damage and leakage in the existing wrap-around gate devices are solved, and the device performance stability and performance are improved.
Patent Information
- Application Number
- CN202311007819.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-10
- Publication Date
- 2025-02-25
AI Technical Summary
The performance of existing wrap-around gate devices needs to be improved, especially in the damage and leakage of the source and drain structure.
By removing the sacrificial layer in the channel region before forming the source and drain structure, damage to the source and drain structure is avoided, and isolation structures are provided on both sides of the channel region to prevent the gate structure from contacting the source and drain structure and reduce leakage.
This method reduces the adverse effects of source and drain structure damage on device performance, expands the process window, improves device performance stability, and reduces leakage problems between source and drain structure and gate structure.
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Figure CN119521750A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] The gate-all-around (GAA) device has become a new direction of research and development in the industry. The characteristic of this technology is that the gate wraps around the channel on all four sides. The source and drain are no longer in contact with the substrate. Instead, multiple source and drain electrodes such as linear (which can be understood as stick-shaped) or flat or sheet-shaped are distributed horizontally and perpendicular to the gate to realize the basic structure and function of MOSFET. This design largely solves the various problems caused by the reduction of gate spacing, including capacitance effects, etc. In addition, the channel is wrapped by the gate on all four sides, so the channel current is smoother than the three-sided wrapping of FinFET.
[0003] However, the performance of existing all-around gate devices needs to be further improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, providing a substrate; forming a composite structure on the substrate, the composite structure including several overlapping composite layers, each of the composite layers including a first sacrificial layer and a channel layer located on the surface of the first sacrificial layer, the composite structure including source and drain regions arranged along a first direction and separated from each other, and a channel region located between the source and drain regions, the first direction being parallel to the substrate surface; removing the first sacrificial layer in the channel region to form a first trench between two adjacent channel layers; removing the source and drain regions to form source and drain openings on both sides of the channel region; after forming the first trench, forming a source and drain structure in the source and drain opening; after forming the source and drain structure, forming a gate structure on the surface of the channel layer in the channel region and in the first trench.
[0006] Optionally, the method for forming the semiconductor structure further includes: before forming the first trench, removing the source and drain regions, and forming source and drain openings on both sides of the channel region.
[0007] Optionally, after removing the source and drain regions and forming source and drain openings on both sides of the channel region, the method further includes: forming a second sacrificial layer on the substrate surface and in the source and drain openings, wherein the second sacrificial layer has a first gate opening exposing the channel layer; etching the first sacrificial layer exposed at the bottom of the first gate opening;
[0008] Optionally, the method for forming the semiconductor structure also includes: before forming a second sacrificial layer, forming a dummy gate structure across the channel region along a second direction on the side wall surface and the top surface of the composite structure, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; after forming the second sacrificial layer, removing the dummy gate structure to form the first gate opening.
[0009] Optionally, the method for forming a source-drain structure in the source-drain opening includes: forming a third sacrificial layer in the first gate opening and in the first trench; after forming the third sacrificial layer, removing the second sacrificial layer; after removing the second sacrificial layer, forming a source-drain structure in the source-drain opening.
[0010] Optionally, the method for forming the semiconductor structure further includes: after forming the first trench, removing the source and drain regions, and forming source and drain openings on both sides of the channel region.
[0011] Optionally, after removing the source and drain regions and forming source and drain openings on both sides of the channel region, the method further includes: forming a second sacrificial layer on the surface of the substrate and the surface of the composite structure, the second sacrificial layer having a first gate opening exposing the channel layer; and etching the first sacrificial layer exposed at the bottom of the first gate opening.
[0012] Optionally, the method for forming the semiconductor structure also includes: before forming a second sacrificial layer, forming a dummy gate structure across the channel region along a second direction on the side wall surface and the top surface of the composite structure, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; after forming the second sacrificial layer, removing the dummy gate structure to form the first gate opening.
[0013] Optionally, the method for forming a source-drain structure in the source-drain opening includes: forming a third sacrificial layer in the first gate opening and in the first trench; after forming the third sacrificial layer, removing the second sacrificial layer; after removing the second sacrificial layer, removing the source-drain region to form source-drain openings on both sides of the channel region; and forming a source-drain structure in the source-drain openings.
[0014] Optionally, the method for forming the semiconductor structure also includes: after forming the source-drain structure, forming a first interlayer dielectric layer on the surface of the substrate and the surface of the source-drain structure, the first interlayer dielectric layer exposing the third sacrificial layer; removing the third sacrificial layer, forming a second gate opening in the first interlayer dielectric layer, the bottom of the second gate opening exposing the first trench; and forming the gate structure in the second gate opening and in the first trench.
[0015] Optionally, the method for forming the gate structure in the second gate opening and the first trench includes: forming a gate dielectric material layer and a work function material layer located on the gate dielectric material layer in the first trench; the gate dielectric material layer is etched to form a first gate dielectric layer; the work function material layer is etched to form a work function layer to form a first gate structure.
[0016] Optionally, the method of forming the gate structure in the second gate opening and the first trench also includes: forming a gate material layer in the second gate opening, the top surface of the gate material layer being higher than the top surface of the first interlayer dielectric layer; and flattening the gate material layer until the top surface of the first interlayer dielectric layer is exposed to form a second gate structure.
[0017] Optionally, the method for forming the semiconductor structure also includes: after forming the second gate structure, forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer and the surface of the second gate structure; forming a first opening in the second interlayer dielectric layer; forming a first plug in the first opening, the first plug being connected to the surface of the second gate structure; forming a second opening in the first interlayer dielectric layer and the second interlayer dielectric layer; forming a second plug in the second opening, the second plug being connected to the surface of the source-drain structure.
[0018] Optionally, it also includes: before forming the first interlayer dielectric layer, forming an initial etch stop layer on the substrate surface, the source and drain structure surface and the third sacrificial layer surface, and flattening the initial etch stop layer until the third sacrificial layer is exposed to form an etch stop layer.
[0019] Optionally, before forming the first groove, the method further includes: removing a portion of the first sacrificial layer from a side wall of the first sacrificial layer to form a first groove and a second groove; and forming an isolation structure in the first groove and the second groove.
[0020] Optionally, the material of the third sacrificial layer includes high-temperature spin-on carbon.
[0021] Optionally, the material of the first sacrificial layer and the source / drain structure includes germanium silicon material.
[0022] Optionally, the process of removing the first sacrificial layer in the channel region includes one of a wet etching process and a dry etching process or a combination of both.
[0023] Optionally, the wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.
[0024] Optionally, the process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0mL / min to 2000mL / min, the reaction pressure range is 0mT to 3000mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0W to 1000W.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, before forming the source-drain structure, the sacrificial layer in the channel region ensures that the source-drain structure will not be damaged during the process of removing the sacrificial layer, thereby reducing the adverse effects of damage to the source-drain structure on device performance, expanding the process window, and improving device performance stability.
[0027] Furthermore, the technical solution of the present invention also isolates the source-drain structure from the sacrificial layer by setting an isolation structure on both sides of the sacrificial layer, thereby avoiding affecting the source-drain structure during the process of forming the gate structure in the first groove, reducing the leakage problem between the source-drain structure and the gate structure, and improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figures 1 to 6 It is a structural schematic diagram of the formation process of a semiconductor structure;
[0029] Figures 7 to 23 It is a structural schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION
[0030] As described in the background art, the method for forming a gate-all-around device needs to be improved. Now, an analysis and description will be given in conjunction with a specific embodiment.
[0031] Figures 1 to 6 It is a structural schematic diagram of the formation process of a semiconductor structure.
[0032] Please refer to Figure 1, providing a substrate 100; forming a composite structure on the substrate 100, the composite structure comprising a plurality of overlapping composite layers, each of the composite layers comprising a first sacrificial layer 102 and a channel layer 101 located on the surface of the first sacrificial layer 102, the composite structure comprising source and drain regions II arranged along a first direction X and separated from each other, and a channel region I located between the source and drain regions II, the first direction X being parallel to the surface of the substrate 100; forming a pseudo gate structure 103 and an inner sidewall 104 along a second direction (not shown in the figure) across the channel region I on the sidewall surface and the top surface of the composite structure, the second direction (not shown in the figure) being parallel to the substrate surface and perpendicular to the first direction X.
[0033] Please refer to Figure 2 , remove the source and drain region II, and form source and drain openings 105 on both sides of the channel region I.
[0034] Please refer to Figure 3 , remove portions of the first sacrificial layer on both sides of the first sacrificial layer to form a first groove (not shown in the figure), a second groove (not shown in the figure) and a sacrificial layer 106; and form an isolation structure 107 in the first groove and the second groove.
[0035] Please refer to Figure 4 , a source-drain structure 108 is formed in the source-drain opening (not shown in the figure); a second sacrificial layer 109 is formed on the surface of the source-drain structure 108 and the sidewall surface of the inner sidewall 104 .
[0036] Please refer to Figure 5 , remove the dummy gate structure 103 to form a first gate opening 111; remove the sacrificial layer of the channel region I to form a first trench 110.
[0037] Please refer to Figure 6 A gate dielectric material layer (not shown in the figure) and a work function material layer (not shown in the figure) located on the gate dielectric material layer are formed in the first groove 110; the gate dielectric material layer is etched to form a first gate dielectric layer 112; the work function material layer is etched to form a work function layer 113 to form a first gate structure; and a second gate structure 114 is formed in the first gate opening.
[0038] In the above solution, since the source-drain structure 108 has been formed before removing the sacrificial layer 106 in the channel region I, the source-drain structure 108 will be damaged during the process of removing the sacrificial layer 106 in the channel region I, thereby affecting the performance of the semiconductor device.
[0039] In order to solve the problem of source-drain structure damage in the above-mentioned semiconductor structure forming method, the present invention also provides a semiconductor structure forming method. Before forming the source-drain structure, the sacrificial layer in the channel region is provided, so that the source-drain structure will not be damaged during the removal of the sacrificial layer, thereby reducing the adverse effects of the source-drain structure damage on the device performance, expanding the process window, and improving the stability of device performance.
[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0041] Figures 7 to 17 It is a structural schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention.
[0042] Please refer to Figure 7 , providing a substrate 200; forming a composite structure on the substrate 200, the composite structure comprising a plurality of overlapping composite layers, each of the composite layers comprising a first sacrificial layer 201 and a channel layer 202 located on the surface of the first sacrificial layer 201, the composite structure comprising source and drain regions II arranged along a first direction X and separated from each other, and a channel region I located between the source and drain regions II, wherein the first direction X is parallel to the surface of the substrate 200.
[0043] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.
[0044] In this embodiment, the material of the channel layer 202 is silicon.
[0045] In this embodiment, the method for forming the channel layer 202 includes: forming a channel material layer (not shown in the figure) on the surface of the first sacrificial layer 201 ; and patterning the channel material layer to form the channel layer 202 .
[0046] Regarding the formation of source and drain openings, in one embodiment, before forming the first trench, the source and drain regions are removed, and source and drain openings are formed on both sides of the channel region.
[0047] In another embodiment, after forming the first trench, the source and drain regions are removed, and source and drain openings are formed on both sides of the channel region.
[0048] The following example takes the process of removing the source and drain regions and forming source and drain openings on both sides of the channel region before forming the first trench as an example, and combines Figures 8 to 17 The formation process of semiconductors is described in detail.
[0049] Please refer to Figure 8A pseudo gate structure 203 is formed on the sidewall surface and the top surface of the composite structure, spanning the channel region along a second direction (not shown in the figure), and the second direction (not shown in the figure) is parallel to the surface of the substrate 200 and perpendicular to the first direction X.
[0050] In this embodiment, the method for forming the dummy gate structure 203 includes: forming a dummy gate material layer (not shown in the figure) on the surface of the substrate 200, the side wall surface and the top surface of the composite structure; and patterning the dummy gate material layer to form the dummy gate structure 203.
[0051] The method for patterning the pseudo gate material layer includes: forming a hard mask layer (not shown in the figure) on the surface of the pseudo gate material layer, wherein the hard mask layer exposes a portion of the pseudo gate material layer; using the hard mask layer as a mask, etching the pseudo gate material layer until the surface of the substrate 200 is exposed.
[0052] The hard mask layer may be a single layer or a multi-layer structure. In this embodiment, the hard mask layer is a three-layer structure consisting of a silicon oxide material layer (not shown in the figure), a silicon nitride material layer (not shown in the figure) and a silicon oxide material layer (not shown in the figure).
[0053] In this embodiment, after forming the dummy gate structure 203 , the method further includes: forming an inner spacer 204 on the sidewall surface of the dummy gate structure 203 .
[0054] In this embodiment, the inner sidewall 204 is flush with the dummy gate structure 203 .
[0055] Please refer to Fig. 9 , remove the source and drain region II, and form source and drain openings 205 on both sides of the channel region I.
[0056] In this embodiment, the method for forming the source-drain opening 205 includes: etching back the source-drain region II on both sides of the inner sidewall 204 until the surface of the substrate 200 is exposed, thereby forming the source-drain opening 205 .
[0057] Please refer to Fig.10 , remove portions of the first sacrificial layer 201 on both sides of the first sacrificial layer 201 to form a first groove (not shown in the figure) and a second groove (not shown in the figure); and form an isolation structure 207 in the first groove and the second groove.
[0058] The function of the isolation structure 207 is that in the subsequent steps, a first trench 209 needs to be formed in the isolation structure 207, and a gate structure is formed in the first trench 209. If there is no isolation structure 207, the gate structure formed in the first trench 209 will contact the source-drain structure, thereby causing leakage. The existence of the isolation structure 207 can prevent the gate structure from contacting the source-drain structure.
[0059] Please refer to Fig.11 , a second sacrificial layer 206 is formed on the surface of the substrate 200 and in the source / drain openings 205 .
[0060] In this embodiment, the material of the second sacrificial layer 206 includes aluminum oxide or aluminum nitride. The advantage of using aluminum oxide or aluminum nitride as the material of the second sacrificial layer 206 is that in the subsequent wet etching process for removing the second sacrificial layer 206, aluminum oxide or aluminum nitride is easily removed by water, so water can be selected as the etching liquid of the wet etching process. It can be seen that the material of the second sacrificial layer 206 should be a material that is easy to remove, so that no residue will be generated when removing the second sacrificial layer 206 to affect the subsequent steps.
[0061] In this embodiment, the second sacrificial layer 206 is flush with the inner sidewall 204 .
[0062] Please refer to Fig.12 , remove the pseudo gate structure 203, and form the first gate opening 208 in the second sacrificial layer 206; remove the first sacrificial layer 201 of the channel region I, and form a first trench 209 between two adjacent channel layers I, and the second sacrificial layer 206 has a first gate opening 208 exposing the channel region I; and etch the channel layer 202 exposed at the bottom of the first gate opening 208.
[0063] In this embodiment, the process of removing the first sacrificial layer 201 in the channel region I includes one of a wet etching process and a dry etching process or a combination of the two.
[0064] In a specific embodiment, the wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.
[0065] In a specific embodiment, the process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0mL / min to 2000mL / min, the reaction pressure range is 0mT to 3000mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0W to 1000W.
[0066] Please refer to Fig.13 , a third sacrificial layer 210 is formed in the first gate opening 208 and in the first trench 209 .
[0067] In this embodiment, the material of the third sacrificial layer 210 includes high-temperature spin-coated carbon. The advantage of using high-temperature spin-coated carbon as the material of the third sacrificial layer 210 is that the high-temperature spin-coated carbon can be cured under mild conditions, has flow characteristics, and can fill high aspect ratio vias in a void-free manner. In addition, the high-temperature spin-coated carbon has significant thermal stability, and the shrinkage / quality loss at a temperature of 550°C is minimal. Therefore, high-temperature spin-coated carbon is selected to be filled into the first gate opening 208 and the first groove 209 to protect the channel and retain the area where the gate structure is formed.
[0068] Please refer to Fig.14 After forming the third sacrificial layer 210 , the second sacrificial layer 206 is removed; after removing the second sacrificial layer 206 , a source-drain structure 211 is formed in the source-drain opening 205 .
[0069] In this embodiment, the material of the first sacrificial layer 201 and the source-drain structure 211 includes germanium silicon material.
[0070] The source-drain structure 211 is flush with the composite layer of the plurality of overlapping layers.
[0071] Please refer to Fig.15 A first interlayer dielectric layer 212 is formed on the surface of the substrate 200 and the surface of the source-drain structure 211 , and the first interlayer dielectric layer 212 exposes the third sacrificial layer 210 .
[0072] In this embodiment, before forming the first interlayer dielectric layer, an initial etch stop layer (not shown in the figure) is formed on the surface of the substrate 200, the surface of the source and drain structure, and the surface of the third sacrificial layer 210, and the initial etch stop layer is flattened until the third sacrificial layer 210 is exposed to form an etch stop layer 213.
[0073] In this embodiment, the planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.
[0074] Please refer to Fig.16 , remove the third sacrificial layer 210, form a second gate opening (not shown in the figure) in the first interlayer dielectric layer 212, and expose the first groove (not marked in the figure) at the bottom of the second gate opening; form the gate structure in the second gate opening (not shown in the figure) and in the first groove.
[0075] In this embodiment, the method for forming the gate structure includes: forming a gate dielectric material layer (not shown in the figure) and a work function material layer (not shown in the figure) located on the gate dielectric material layer; the gate dielectric material layer is etched to form a first gate dielectric layer 215; the work function material layer is etched to form a work function layer 216 to form a first gate structure.
[0076] The material of the first gate dielectric layer 215 includes tungsten, and the material of the work function layer 216 includes titanium nitride.
[0077] In this embodiment, the thickness of the work function layer 216 ranges from 0.1 nm to 10 nm. The function of the work function layer 216 is to adjust the threshold voltage of the MOS transistor, and the thickness of the work function layer 216 depends on the threshold voltage required by the all-around gate device.
[0078] The method for forming the gate structure also includes: forming a gate material layer (not shown in the figure) in the second gate opening (not shown in the figure), the top surface of the gate material layer is higher than the top surface 212 of the first interlayer dielectric layer; flattening the gate material layer until the top surface of the first interlayer dielectric layer 212 is exposed to form a second gate structure 214.
[0079] The material of the second gate structure 214 includes metal. In this embodiment, the material of the second gate structure 214 is tungsten.
[0080] Please refer to Fig.17 After the second gate structure 214 is formed, a second interlayer dielectric layer 217 is formed on the top surface of the first interlayer dielectric layer 212 and the surface of the second gate structure 214; a first opening (not shown in the figure) is formed in the second interlayer dielectric layer 217; a first plug 218 is formed in the first opening, and the first plug 218 is connected to the surface of the second gate structure 214; a second opening (not shown in the figure) is formed in the first interlayer dielectric layer 212 and the second interlayer dielectric layer 217; a second plug 219 is formed in the second opening, and the second plug 219 is connected to the surface of the source-drain structure 211.
[0081] In this embodiment, the first opening (not shown in the figure) is used to provide a receiving space for a first plug 218 formed subsequently, and the second opening is used to provide a receiving space for a second plug 219 formed subsequently.
[0082] In this embodiment, the method for forming the first opening (not shown in the figure) includes: forming a mask layer (not shown in the figure) on the surface of the second interlayer dielectric layer 217, the mask layer exposing a portion of the surface of the second interlayer dielectric layer 217; using the mask layer as a mask, etching the second interlayer dielectric layer 217 to form a first opening in the second interlayer dielectric layer 217.
[0083] In this embodiment, the method for forming the second opening (not shown in the figure) includes: forming a mask layer (not shown in the figure) on the surface of the second interlayer dielectric layer 217, the mask layer exposing a portion of the surface of the second interlayer dielectric layer 217; using the mask layer as a mask, etching the first interlayer dielectric layer 212 and the second interlayer dielectric layer 217 to form a second opening in the first interlayer dielectric layer 212 and the second interlayer dielectric layer 217.
[0084] In this embodiment, the depth of the first opening is smaller than the depth of the second opening, and the top widths of the first opening and the second opening are larger than the bottom widths, that is, they are in an inverted trapezoidal shape.
[0085] In this embodiment, the material of the second interlayer dielectric layer 217 is the same as that of the first interlayer dielectric layer 212 .
[0086] Figures 18 to 23 It is a structural schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention.
[0087] The difference between this embodiment and the previous embodiment is that after forming the first trench, the source and drain regions are removed, and source and drain openings are formed on both sides of the channel region. Figures 18 to 23 The formation process of semiconductors is described in detail.
[0088] Please Figure 8 Continue to refer to Fig.18 A second sacrificial layer 301 is formed on the composite structure surface and inner sidewall of the source / drain region II.
[0089] Please refer to Fig.19 , remove the dummy gate structure, and form a first gate opening 302 in the second sacrificial layer 301 to expose the channel layer; and etch the first sacrificial layer 201 exposed at the bottom of the first gate opening 302 to form a first trench 303 .
[0090] In this embodiment, the process of etching the first sacrificial layer 201 includes one of a wet etching process and a dry etching process or a combination of the two.
[0091] In a specific embodiment, the wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.
[0092] In a specific embodiment, the process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0mL / min to 2000mL / min, the reaction pressure range is 0mT to 3000mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0W to 1000W.
[0093] Please refer to Fig. 20 , a third sacrificial layer 304 is formed in the first gate opening 302 and in the first trench 303 .
[0094] In this embodiment, the material of the third sacrificial layer 304 includes high temperature spin-coated carbon. The advantage of using high temperature spin-coated carbon as the material of the third sacrificial layer is that the high temperature spin-coated carbon can be cured under mild conditions, has flow characteristics, and can fill high aspect ratio vias in a void-free manner. In addition, the high temperature spin-coated carbon has significant thermal stability, and the shrinkage / mass loss at a temperature of 550°C is minimal. Therefore, high temperature spin-coated carbon is selected to be filled into the first gate opening and the first groove to protect the channel and retain the area where the gate structure is formed.
[0095] Please refer to Fig.21 , remove the second sacrificial layer 301 and the composite layer of the source and drain region II, and form source and drain openings 305 on both sides of the channel region I; remove part of the first sacrificial layer 201 on the side wall of the third sacrificial layer 304 to form a first groove (not shown in the figure) and a second groove (not shown in the figure); form an isolation structure 306 in the first groove and the second groove.
[0096] In this embodiment, the method for forming the source / drain opening 305 includes: forming a mask layer (not shown in the figure) on the surface of the third sacrificial layer 304 and the top surface of the inner wall 204, the mask layer exposing the surface of the second sacrificial layer 301; using the mask layer as a mask, etching the second sacrificial layer 301 and the composite layer of the source / drain region II until the surface of the substrate 200 is exposed to form the source / drain opening 305.
[0097] In this embodiment, the method for forming the isolation structure 306 includes: etching the first sacrificial layer 201 on the side wall of the third sacrificial layer 304 to form a first groove (not shown in the figure) and a second groove (not shown in the figure); depositing an isolation layer in the first groove, the second groove and on the surface of the substrate; and etching back the isolation layer until the surface of the substrate 200 is exposed to form an isolation structure 306.
[0098] The function of the isolation structure 306 is that in the subsequent steps, a first trench needs to be formed in the isolation structure 306, and a gate structure is formed in the first trench. If there is no isolation structure 306, the gate structure formed in the first trench will contact the source-drain structure, thereby causing leakage. The existence of the isolation structure 306 can prevent the gate structure from contacting the source-drain structure.
[0099] In this embodiment, the material of the second sacrificial layer 301 includes aluminum oxide or aluminum nitride. The advantage of using aluminum oxide or aluminum nitride as the material of the second sacrificial layer 301 is that in the subsequent wet etching process for removing the second sacrificial layer 301, aluminum oxide or aluminum nitride is easily removed by water, so water can be selected as the etching liquid of the wet etching process. It can be seen that the material of the second sacrificial layer 301 should be a material that is easy to remove, so that no residue will be generated when removing the second sacrificial layer 301 to affect the subsequent steps.
[0100] The second sacrificial layer 301 is flush with the inner sidewall 204 .
[0101] Please refer to Fig. 22 , a source-drain structure 307 is formed in the source-drain opening 305 .
[0102] In this embodiment, the material of the first sacrificial layer 201 and the source-drain structure 307 includes germanium silicon material.
[0103] The source-drain structure 307 is flush with the composite layer of the plurality of overlapping layers.
[0104] Please refer to Fig.23, forming a first interlayer dielectric layer 308 on the surface of the substrate 200, the surface of the source-drain structure 307 and the surface of the sidewall of the composite structure, wherein the first interlayer dielectric layer 308 exposes the third sacrificial layer (not shown in the figure); removing the third sacrificial layer (not shown in the figure), forming a second gate opening (not shown in the figure) in the first interlayer dielectric layer 308, and exposing the first trench (not shown in the figure) at the bottom of the second gate opening (not shown in the figure); forming a gate dielectric material layer (not shown in the figure) and a work function material layer (not shown in the figure) located on the gate dielectric material layer in the first trench; etching the gate dielectric material layer to form a first gate dielectric layer 309; etching the work function material layer to form a work function layer 310 to form a first gate structure; forming a gate material layer in the second gate opening (not shown in the figure), the top surface of the gate material layer is higher than the top surface of the first interlayer dielectric layer 308; the gate material layer is planarized until the top surface of the first interlayer dielectric layer 308 is exposed to form a second gate structure 311; a second interlayer dielectric layer 312 is formed on the top surface of the first interlayer dielectric layer 308 and the surface of the second gate structure 311; a first opening (not marked in the figure) is formed in the second interlayer dielectric layer 312; a first plug 313 is formed in the first opening, and the first plug 313 is connected to the surface of the second gate structure 311; a second opening (not marked in the figure) is formed in the first interlayer dielectric layer 308 and the second interlayer dielectric layer 312; a second plug 314 is formed in the second opening, and the second plug 314 is connected to the surface of the source and drain structure.
[0105] In this embodiment, before forming the first interlayer dielectric layer 308, an initial etch stop layer (not shown in the figure) is formed on the surface of the substrate 200, the surface of the source / drain structure 307 and the surface of the third sacrificial layer 304, and the initial etch stop layer is flattened until the third sacrificial layer 304 is exposed to form an etch stop layer 315.
[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: providing a substrate; forming a composite structure on the substrate, the composite structure comprising a plurality of overlapping composite layers, each of the composite layers comprising a first sacrificial layer and a channel layer located on a surface of the first sacrificial layer, the composite structure comprising source and drain regions arranged along a first direction and separated from each other, and a channel region located between the source and drain regions, wherein the first direction is parallel to a surface of the substrate; Removing the first sacrificial layer in the channel region to form a first trench between two adjacent channel layers; Removing the source and drain regions, and forming source and drain openings on both sides of the channel region; After forming the first trench, forming a source-drain structure in the source-drain opening; After forming the source-drain structure, a gate structure is formed on the surface of the channel layer in the channel region and in the first trench.
2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the first trench, the source and drain regions are removed, and source and drain openings are formed on both sides of the channel region.
3. The method for forming a semiconductor structure according to claim 2, wherein: After removing the source and drain regions and forming source and drain openings on both sides of the channel region, the method further includes: forming a second sacrificial layer on the substrate surface and in the source and drain openings, wherein the second sacrificial layer has a first gate opening exposing the channel layer; and etching the first sacrificial layer exposed at the bottom of the first gate opening.
4. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: Before forming the second sacrificial layer, a dummy gate structure is formed on the side wall surface and the top surface of the composite structure, spanning the channel region along a second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; after forming the second sacrificial layer, the dummy gate structure is removed to form the first gate opening.
5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming a source-drain structure in the source-drain opening includes: forming a third sacrificial layer in the first gate opening and the first trench; after forming the third sacrificial layer, removing the second sacrificial layer; after removing the second sacrificial layer, forming a source-drain structure in the source-drain opening.
6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first trench, the source and drain regions are removed, and source and drain openings are formed on both sides of the channel region.
7. The method for forming a semiconductor structure according to claim 6, wherein: After removing the source and drain regions and forming source and drain openings on both sides of the channel region, the method further includes: forming a second sacrificial layer on the surface of the substrate and the surface of the composite structure, wherein the second sacrificial layer has a first gate opening exposing the channel layer; and etching the first sacrificial layer exposed at the bottom of the first gate opening.
8. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: Before forming the second sacrificial layer, a dummy gate structure is formed on the side wall surface and the top surface of the composite structure, spanning the channel region along a second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; after forming the second sacrificial layer, the dummy gate structure is removed to form the first gate opening.
9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming a source-drain structure in the source-drain opening comprises: forming a third sacrificial layer in the first gate opening and in the first trench; after forming the third sacrificial layer, removing the second sacrificial layer; after removing the second sacrificial layer, removing the source-drain region, and forming source-drain openings on both sides of the channel region; A source-drain structure is formed in the source-drain opening.
10. The method for forming a semiconductor structure according to any one of claims 5 or 9, characterized in that: Also includes: After forming the source-drain structure, forming a first interlayer dielectric layer on the surface of the substrate and the surface of the source-drain structure, wherein the first interlayer dielectric layer exposes the third sacrificial layer; removing the third sacrificial layer, forming a second gate opening in the first interlayer dielectric layer, wherein the bottom of the second gate opening exposes the first trench; The gate structure is formed within the second gate opening and within the first trench.
11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the gate structure in the second gate opening and the first trench comprises: forming a gate dielectric material layer and a work function material layer on the gate dielectric material layer in the first trench; etching the gate dielectric material layer to form a first gate dielectric layer; etching the work function material layer to form a work function layer to form a first gate structure.
12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the gate structure in the second gate opening and the first trench also includes: forming a gate material layer in the second gate opening, the top surface of the gate material layer being higher than the top surface of the first interlayer dielectric layer; and planarizing the gate material layer until the top surface of the first interlayer dielectric layer is exposed to form a second gate structure.
13. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: After forming the second gate structure, forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer and on the surface of the second gate structure; forming a first opening in the second interlayer dielectric layer; forming a first plug in the first opening, wherein the first plug is connected to a surface of the second gate structure; A second opening is formed in the first interlayer dielectric layer and the second interlayer dielectric layer; a second plug is formed in the second opening, and the second plug is connected to the surface of the source-drain structure.
14. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: Before forming the first interlayer dielectric layer, an initial etch stop layer is formed on the substrate surface, the source-drain structure surface and the third sacrificial layer surface, and the initial etch stop layer is planarized until the third sacrificial layer is exposed to form an etch stop layer.
15. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the first groove, the method further includes: removing a portion of the first sacrificial layer from the sidewall of the first sacrificial layer to form a first groove and a second groove; and forming an isolation structure in the first groove and the second groove.
16. The method for forming a semiconductor structure according to claim 10, wherein: The material of the third sacrificial layer includes high temperature spin-on carbon.
17. The method for forming a semiconductor structure according to claim 1, wherein: The materials of the first sacrificial layer and the source-drain structure include germanium silicon material.
18. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first sacrificial layer in the channel region includes one of a wet etching process and a dry etching process or a combination of both.
19. The method for forming a semiconductor structure according to claim 18, wherein: The wet etching process parameters include: the etching solution includes at least two solutions of ammonia, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0wt% to 30wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.
20. The method for forming a semiconductor structure according to claim 19, wherein: The process parameters of the dry etching process include: the etching gas includes at least three gases among fluorine, hydrogen, nitrogen, argon and ammonia, and the flow rate range of each gas is 0mL / min to 2000mL / min, the reaction pressure range is 0mT to 3000mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0W to 1000W.