Load end detection circuit and load detection method

Abstract

The invention discloses a load end detection circuit and a load detection method, the load end detection circuit comprises a load end, a first load detection circuit and a second load detection circuit, and the first load detection circuit and the second load detection circuit are both connected with the load end; the first load detection circuit is connected with the second load detection circuit; the first load detection circuit is used for outputting a first level comparison signal according to the magnitude relationship between the voltage sensed by the load end and a first reference voltage set in the first load detection circuit; and the second load detection circuit is used for outputting a second level comparison signal under the control of the first level comparison signal according to the magnitude relationship between the voltage sensed by the load end and a second reference voltage set inside, so that the second level comparison signal and / or the first level comparison signal reflect the load module connection condition of the load end.

Description

Technical Field

[0001] The present application relates to the technical field of operational amplifier control circuits, and in particular to a load-end detection circuit and a load detection method. Background Art

[0002] The current load detection circuit generates a voltage by outputting a constant current source to the load or divides the voltage through a high-impedance resistor and the load, and then compares it with a reference voltage through an operational amplifier to generate a load detection signal. However, when the power consumption is low, the constant current source and the high-impedance resistor are easily interfered. For example, the reference voltage of the comparator input may be very low, increasing the noise ratio and easily causing interference. A large impedance or large capacitance may be detected, which may easily cause false detection and result in low detection accuracy. Summary of the invention

[0003] The present application discloses a load end detection circuit and a load detection method, including the following technical solutions: A load-end detection circuit, the load-end detection circuit comprises a load end, a first load detection circuit and a second load detection circuit, the first load detection circuit and the second load detection circuit are both connected to the load end, the load end is used to connect a load module outside the load-end detection circuit; the first load detection circuit is connected to the second load detection circuit; the first load detection circuit is used to output a first level comparison signal according to the magnitude relationship between the voltage sensed by the load end and a first reference voltage set internally; the second load detection circuit is used to output a second level comparison signal according to the magnitude relationship between the voltage sensed by the load end and a second reference voltage set internally under the control of the first level comparison signal, so that the second level comparison signal and / or the first level comparison signal reflect the connection status of the load module at the load end; wherein the second reference voltage is less than the first reference voltage. In summary, when the first load detection circuit senses a change in voltage at the load end so as to preliminarily determine that there is a capacitive / resistive load physically connected (such as plugging in a load module), the second load detection circuit can be enabled to perform relatively accurate load detection to determine whether the load module and the load-end detection circuit meet the conditions for establishing an electrical connection, thereby improving the detection accuracy of the load module, meeting the detection accuracy of more resistance values, and enhancing the anti-interference capability. Relative to the second load detection circuit, the second load detection circuit can use a relatively large power consumption current source to design a low-delay high-precision comparator; thus, relative to the load detection circuit composed of a single comparator, the detection accuracy of the load-end detection circuit composed of the first load detection circuit and the second load detection circuit disclosed in the technical solution is improved.

[0004] A load detection method, the load detection method uses the load end detection circuit to detect the access status of the load module; the load detection method includes: when the logic level of the first level comparison signal is set to logic 1, and the logic level of the second level comparison signal is set to logic 1, it is determined that the load end detection circuit and the load module meet the conditions for establishing electrical connection, so as to detect that the load module is connected to the load end detection circuit; when the logic level of the first level comparison signal is set to logic 0, it is determined that the load end detection circuit and the load module do not meet the conditions for establishing electrical connection, so as to detect that the load module is not connected to the load end detection circuit. In summary, the load detection method determines the electrical connection relationship between the load end detection circuit and the load module based on the level state of the second level comparison signal and / or the first level comparison signal, and determines whether the load module is plugged into the load end, which improves the detection accuracy compared to using a single load detection level state for detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 The present invention is a schematic diagram of the structure of a load-end detection circuit disclosed in an embodiment.

[0006] Figure 2 is based on Figure 1 The load-end detection circuit in the embodiment discloses a timing diagram among a first level comparison signal CMPOUT output by a first comparator CMP1, a target delay signal CMPOUT_DLY output by a delay device DLY, a target detection pulse signal EN output by a delay processing circuit, and an output signal LOADON of a trigger. Implementation

[0007] The specific implementation methods of the present application are further described below in conjunction with the accompanying drawings. In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0008] The terms "a" or "an", as used herein, are defined as one or more than one. The term "plurality", as used herein, is defined as two or more than two. The term "another", as used herein, is defined as at least a second or more. The terms "including" and / or "having", as used herein, are defined as "comprising" (i.e., open ended terms).

[0009] As an embodiment, a load end detection circuit is disclosed, referring to Figure 1 It can be known that the load-end detection circuit includes a load end Vout, a first load detection circuit and a second load detection circuit; the first load detection circuit and the second load detection circuit are both connected to the load end, specifically, the input end of the first load detection circuit and the input end of the second load detection circuit are both connected to the load end Vout; the load end Vout is used to connect the load module outside the load-end detection circuit; the load end Vout is used to sense the voltage of the load module outside the load-end detection circuit, including the voltage of the non-grounded end of the resistor or capacitor, and also includes sensing the voltage at the load end when the load module is not connected. Among them, the voltage sensed by the load end is used to share the input end of the first load detection circuit and the input end of the second load detection circuit, which can trigger the first load detection circuit and the second load detection circuit to start detecting the connection of the load end to the load module, including whether the load module is plugged into the load end, and whether the load module is suitable for establishing an electrical connection with the load end, which can be collectively referred to as whether the load module is connected. The load-end detection circuit plays an auxiliary role in detecting whether the load module is connected, and assists the control chip outside the load-end detection circuit to detect whether the load module is connected.

[0010] The first load detection circuit is connected to the second load detection circuit to form a two-stage load detection circuit connected in series, wherein the first load detection circuit and the second load detection circuit are both load detection modules formed by connecting a comparator and a current source. The first load detection circuit is used to enable and control the operation of the second load detection circuit; the second load detection circuit is used to select to start the detection of the access status of the load module at the load end Vout based on the voltage of the load end Vout when the first load detection circuit senses the voltage of the load end Vout, thereby improving the detection accuracy. In some embodiments, the current flowing in the second load detection circuit is greater than the current flowing in the first load detection circuit, wherein the detection accuracy of the second load detection circuit is higher than the detection accuracy of the first load detection circuit, but the power consumption of the second load detection circuit is higher than the power consumption of the first load detection circuit, so when the first load detection circuit starts to detect the load end, limiting the time for the second load detection circuit to continuously detect the load end can both ensure the detection accuracy and avoid consuming too much power.

[0011] In this embodiment, the first load detection circuit is used to output a first level comparison signal according to the magnitude relationship between the voltage sensed at the load end and the first reference voltage set internally. It can be understood that the first load detection circuit outputs the first level comparison signal according to the magnitude relationship between the voltage sensed at its input end and the first reference voltage set internally, so as to flip the first level comparison signal by comparing the magnitude relationship between the load end Vout and the first reference voltage VREF1, so as to preliminarily indicate the detection status of the load end Vout being connected to the load module, for example, detecting whether the load module is plugged into the load end Vout, and the load module can be a capacitive load (for example, a load capacitor) or a resistive load (for example, a load resistor). In some embodiments, when the first level comparison signal flips from a low level to a high level, it is determined that the first load detection circuit has started detection work, and preliminarily determines that the load module at the load end Vout is physically plugged in, but needs to enable control of the second load detection circuit for further detection to determine whether the load module and the load end Vout meet the conditions for electrical connection, including detecting the resistance range of the resistance value of the load module, thereby improving the detection accuracy. Therefore, the first level comparison signal can be used to enable control of the second load detection circuit and the first load detection circuit to perform a fine detection of the preliminary detection result of the load end Vout.

[0012] In this embodiment, the second load detection circuit is used to output the second level comparison signal according to the magnitude relationship between the voltage sensed at the load end and the second reference voltage set internally under the control of the first level comparison signal, so that the second level comparison signal and / or the first level comparison signal reflects the connection status of the load module; it can be understood that the first level comparison signal controls the second load detection circuit to output the second level comparison signal according to the magnitude relationship between the voltage sensed at its input end and the second reference voltage set internally, thereby flipping the second level comparison signal by comparing the magnitude relationship between the load end Vout and the second reference voltage VREF2, so as to combine the The first level comparison signal detects the load module connected to the load terminal Vout, so that the second level comparison signal and / or the first level comparison signal reflects the connection status of the load module of the load terminal Vout, including determining that the load terminal detection circuit and the load module meet the conditions for establishing electrical connection when the second level comparison signal and the first level comparison signal are both set to high levels within a certain pulse width, otherwise it is directly regarded that the load terminal Vout or the load terminal detection circuit is not connected to the load module, that is, it does not meet the conditions for establishing electrical connection, even if the load module may be plugged into the load terminal Vout, thereby eliminating electrical interference and preventing glitch-type false detection phenomena.

[0013] The high level generated or detected at each circuit port of the present application is a level signal of 3.3V to 5V, or even a higher voltage value, and the corresponding level logic value is logic 1; the low level generated or detected at each circuit port of the present application is 0V to 1.5V, and the corresponding level logic value is logic 0.

[0014] It should be noted that the second reference voltage is smaller than the first reference voltage to allow for the following situations: the second level comparison signal changes and the first level comparison signal does not change; however, when the first level comparison signal changes, the second level comparison signal has already changed; and this is performed in a circuit environment that automatically compares the magnitude relationship between the load terminal Vout and the second reference voltage VREF2, and the magnitude relationship between the load terminal Vout and the first reference voltage VREF1.

[0015] From the perspective of the voltage borne by the resistance value of the load module, the comparison voltage threshold required by the first load detection circuit to detect the load module is higher than the comparison voltage threshold required by the second load detection circuit to detect the load module. In some embodiments, the minimum voltage value of the load end allowed to be detected by the first load detection circuit is greater than the minimum voltage value of the load end detected by the second load detection circuit, so that: if the voltage at the load end changes under the condition of being lower than the comparison voltage threshold required by the first load detection circuit to detect the load module, even if the second level comparison signal changes, the logic level of the first level comparison signal is maintained at logic 1; if the voltage at the load end changes under the condition of being lower than the comparison voltage threshold required by the second load detection circuit to detect the load module, the logic level of the second level comparison signal and the logic level of the first level comparison signal are both maintained at logic 1.

[0016] It should be supplemented that, from the perspective of the resistance value of the load module, when the second reference voltage is less than the first reference voltage, the voltage threshold required for the first load detection circuit to detect the load module is higher than the voltage threshold required for the second load detection circuit to detect the load module, the minimum resistance value of the load module allowed to be detected by the first load detection circuit is greater than the minimum resistance value of the load module detected by the second load detection circuit, and the maximum resistance value of the load module allowed to be detected by the first load detection circuit is greater than the maximum resistance value of the load module detected by the second load detection circuit.

[0017] In summary, when the first load detection circuit senses a change in voltage at the load end so as to preliminarily determine that there is a physical connection of a capacitive / resistive load (such as plugging in a load module), the second load detection circuit can be enabled to perform relatively accurate load detection to determine whether the load module meets the conditions for establishing an electrical connection with the load-end detection circuit, thereby improving the detection accuracy of the load module, meeting the detection accuracy of a wider range of resistance values, and enhancing anti-interference capabilities.

[0018] Compared with the second load detection circuit, the second load detection circuit can utilize a current source with relatively large power consumption to design a low-delay and high-precision comparator; thus, compared with the load detection circuit composed of a single comparator, the detection accuracy of the load-end detection circuit composed of the first load detection circuit and the second load detection circuit disclosed in this embodiment is improved.

[0019] Based on the above embodiments, Figure 1As shown, the load-end detection circuit also includes a delay processing circuit and a trigger DFF. The trigger DFF adopts a D trigger and supports rising edge triggering; the output end of the first load detection circuit is connected to the enable end of the second load detection circuit through the delay processing circuit, and the delay processing circuit outputs the target detection pulse signal EN to the second load detection circuit and the trigger DFF respectively. The reset end RB of the trigger DFF and the data input end D of the trigger DFF are both connected to the output end of the first load detection circuit to receive the first level comparison signal CMPOUT, thereby resetting the trigger DFF through the first load detection circuit or providing the trigger DFF with the required collected data; the output end of the second load detection circuit is connected to the clock end CK of the trigger DFF, thereby driving the trigger DFF to work through the second load detection circuit. Preferably, the trigger DFF is configured to collect signals at the rising edge. Therefore, the delay processing circuit is used to delay the first level comparison signal CMPOUT to be a target detection pulse signal EN, and then output the target detection pulse signal EN to the reset terminal RB of the trigger DFF and the enable terminal of the second load detection circuit respectively, so as to enable the second load detection circuit to output the second level comparison signal and enable the trigger to transmit the first level comparison signal within the pulse width of the target detection pulse signal, and specifically enable the trigger DFF to transmit the first level comparison signal under the drive of the second level comparison signal output by the second load detection circuit, including that the clock terminal CK collects the first level comparison signal CMPOUT by the data input terminal D of the trigger DFF when receiving the rising edge; in fact, it realizes the control of the second load detection circuit by the first level comparison signal CMPOUT, controls the second load detection circuit to detect normally only within the pulse width of the target detection pulse signal, and also realizes that the signal LOADON output by the output terminal Q of the trigger DFF reflects the connection status of the load module at the load end within the pulse width of the target detection pulse signal EN or within the pulse width after a transmission delay.

[0020] It should be noted that after the data input terminal D of the trigger collects the first level comparison signal CMPOUT at the rising edge, the output terminal Q of the trigger DFF outputs the first level comparison signal CMPOUT, that is, the signal LOADON. The pulse width of the target detection pulse signal is the pulse duration in the target detection pulse signal, which can ensure the normal operation of the second load detection circuit; Figure 2The high-level duration length Tdly in the target detection pulse signal EN is the result of delay processing of the first level comparison signal CMPOUT in the delay processing circuit; thereby, the first level comparison signal CMPOUT and the second level comparison signal are combined to reflect the connection status of the load module at the load end, and the output signal LOADON of the trigger DFF can also be directly used to reflect the connection status of the load module at the load end.

[0021] In the specific implementation process, when the load end Vout is not connected to the load module, including when the load module is not in contact with the load end Vout, only the first load detection circuit works normally, and the second load detection circuit and the trigger DFF are not enabled to start working, then only the low-power load detection part is started to reduce the power consumption of the load end detection circuit. When the load end Vout is connected to the load module (including when the load module is plugged into the load end Vout), the first load detection circuit is used as the enable control circuit of the second load detection circuit to detect a smaller load resistance, and within a high level duration length Tdly after the load module is connected, taking into account both power consumption and detection accuracy. Since the relatively high power consumption load detection is only effectively implemented when the load module is connected for a long enough time; if the load module is not connected for a long enough time, it is considered that the load module is not connected, that is, the load module and the load end detection circuit do not meet the conditions for establishing an electrical connection, thereby eliminating interference and preventing glitch-type false detection.

[0022] As an example, Figure 1As shown, a first current source Ismall is provided inside the first load detection circuit; the first current source Ismall is used to provide a constant current, and drives the voltage received by the load terminal Vout to automatically adjust according to the change of the resistance value of the load module, so that the voltage at the input terminal of the first load detection circuit is adaptively adjusted under the combined effect of the current provided by the first current source Ismall and the resistance value of the load module connected to the load terminal Vout, in order to change the first level comparison signal; generally, the larger the resistance value of the load module, the larger the voltage at the load terminal Vout, and the current flowing through the load module may become smaller. In this embodiment, the input end of the first load detection circuit is regarded as the end to be compared of the first load detection circuit -, and can also be directly regarded as the load end Vout; when the voltage received by the input end (or the load end Vout) of the first load detection circuit is automatically adjusted by the first current source Ismall and / or the voltage of the load end Vout to be greater than the first reference voltage VREF1, the first level comparison signal is set to a low level; when the voltage received by the input end (or the load end Vout) of the first load detection circuit is automatically adjusted by the first current source Ismall and / or the voltage of the load end Vout to be less than the first reference voltage VREF1, the first level comparison signal is set to a high level.

[0023] like Figure 1 As shown, a second current source Ilarge is provided inside the second load detection circuit; the second current source Ilarge is used to provide a constant current under the control of the target detection pulse signal EN, and to drive the voltage received by the load terminal Vout to automatically adjust according to the change of the resistance value of the load module, so that the voltage at the input end of the second load detection circuit is adaptively adjusted under the joint action of the current provided by the second current source Ilarge and the resistance value of the load module connected to the load terminal Vout, so as to change the second level comparison signal under the control of the target detection pulse signal EN, and also make the first level comparison signal CMPOUT contribute to the adjustment of the second level comparison signal by the second load detection circuit. Generally, the smaller the resistance value of the load module, the smaller the voltage at the load terminal Vout, and the current flowing through the load module may become larger. In this embodiment, the input end of the second load detection circuit is regarded as the end to be compared of the second load detection circuit -, and can also be directly regarded as the load end Vout; when the voltage received by the input end (or the load end Vout) of the second load detection circuit is automatically adjusted by the second current source Ilarge and / or the voltage of the load end Vout to be greater than the second reference voltage VREF2, the second level comparison signal is set to a low level; when the voltage received by the input end (or the load end Vout) of the second load detection circuit is automatically adjusted by the second current source Ilarge and / or the voltage of the load end Vout to be less than the second reference voltage VREF2, the second level comparison signal is set to a high level.

[0024] In this embodiment, the constant current provided by the first current source is smaller than the constant current provided by the second current source, and the current value of the constant current provided by the first current source is smaller than the current value of the constant current provided by the second current source. It can be determined that the current required for the normal operation of the first load detection circuit is smaller than the current required for the normal operation of the second load detection circuit. The constant current provided by the first current source can be 500nA, and the constant current provided by the second current source can be 100mA, so that the power consumption generated by the first load detection circuit is lower than the power consumption generated by the second load detection circuit. The first load detection circuit can be set as a low-power load detection circuit, and the second load detection circuit can be set as a high-power load detection circuit, and the two power consumption types of load detection circuits are supplied with current successively to maintain normal detection operation.

[0025] If the load terminal Vout is not connected to a load module, the first level comparison signal output is a low level, the second load detection circuit is not enabled, and the second current source Ilarge is not controlled to output current to the load terminal Vout for further detection; if the load terminal Vout is connected to a load module with a larger resistance value, the second current source Ilarge is controlled to output current to the load terminal Vout for further detection. For example, Ilarge (a current source that can output 100mA) can be used to detect load resistances below 2 ohms, and load resistances above 2 ohms are considered not connected. Among them, a load resistance less than 2 ohms can adjust the voltage of the load terminal Vout to be sufficiently low, lower than the second reference voltage VREF2, so that the second level comparison signal becomes a high level, and when it is higher than 2 ohms, the voltage at the load terminal Vout can be adjusted to be higher than the second reference voltage VREF2, so that the second level comparison signal becomes a low level.

[0026] It is worth noting that since both the first load detection circuit and the second load detection circuit are connected to the load end, the first current source Ismall can provide a constant current for the second load detection circuit. However, the current required for the normal operation of the first load detection circuit is less than the current required for the normal operation of the second load detection circuit, and cannot meet the power consumption requirement of the second load detection circuit. Therefore, it is necessary to introduce a constant current provided by the second current source Ilarge.

[0027] Specifically, Figure 1As shown, the first load detection circuit includes a first comparator CMP1, the negative input terminal - of the first comparator CMP1 is connected to the output terminal of the first current source Ismall, and the first current source Ismall is also connected to the power supply voltage VCC; the negative input terminal - of the first comparator CMP1 is used to receive the voltage automatically adjusted due to the change of the resistance value of the load module, so as to provide the first load detection circuit with information that the load terminal Vout is connected to the load module; the positive input terminal + of the first comparator CMP1 is used to access the first reference voltage VREF1, and the output terminal of the first comparator CMP1 is connected to the input terminal of the delay processing circuit. The first comparator CMP1 is used to output the first level comparison signal CMPOUT to the delay processing circuit to generate the target detection pulse signal EN according to the magnitude relationship between the voltage received by its negative input terminal - and the first reference voltage VREF1, wherein the load terminal Vout is connected to the negative input terminal - of the first comparator, and the negative input terminal - of the first comparator can also be regarded as the load terminal Vout; the input terminal of the first load detection circuit is the negative input terminal - of the first comparator; the output terminal of the first comparator is the output terminal of the first load detection circuit.

[0028] When the magnitude relationship between the voltage received at the negative input terminal of the first comparator and the first reference voltage changes, the first level comparison signal changes; specifically, when the voltage received at the negative input terminal of the first comparator becomes greater than the first reference voltage VREF1, the first level comparison signal is set to a low level, indicating that the load end is sensed to have a larger resistance value, and it can be preliminarily determined that the load end is not connected to the load module, and it can be detected that the load module is not plugged into the load end. When the voltage received at the negative input terminal of the first comparator becomes less than the first reference voltage VREF1, the first level comparison signal is set to a high level, indicating that the load end is sensed to have a smaller resistance value, and it can be preliminarily determined that the load end is connected to the load module, and it can be detected that the load module is plugged into the load end. Thus, the magnitude relationship between the voltage at the load end Vout and the first reference voltage is compared by the first comparator, and the first level comparison signal represents the connection status of the load module based on the comparison result, which is suitable for detecting the scene of capacitive / resistive load access in a micro-power load detection circuit.

[0029] like Figure 1As shown, the second load detection circuit includes a second comparator CMP2 and a switch tube SWITCH, the two transmission ends of the switch tube SWITCH are respectively connected to the output end of the second current source Ilarge and the negative input end - of the second comparator CMP2, and the second current source Ilarge is also connected to the power supply voltage VCC; the control end of the switch tube SWITCH is connected to the output end of the delay processing circuit, and the switch tube SWITCH adopts an NMOS tube; the gate end of the NMOS tube is the control end of the switch tube SWITCH to support the target detection pulse signal EN output by the delay processing circuit to be turned on, the drain of the NMOS tube is connected to the output end of the second current source Ilarge, and the source of the NMOS tube is connected to the negative input end - of the second comparator CMP2, forming a switch path between the second current source Ilarge and the second comparator CMP2 (or the load end).

[0030] The positive input terminal + of the second comparator CMP2 is used to access the second reference voltage VREF2; the control terminal of the switch tube SWITCH and the enable terminal of the second comparator CMP2 are both connected to the output terminal of the delay processing circuit, so that the switch tube SWITCH and the second comparator CMP2 are both subject to the enable control of the delay processing circuit, and the second comparator CMP2 is started or stopped for comparison, wherein the control terminal of the switch tube SWITCH and the enable terminal of the second comparator CMP2 are both the enable terminals of the second load detection circuit, and the power consumption can be reduced when the target detection pulse signal EN stops the second comparator CMP2 from working.

[0031] In this embodiment, the control end of the switch tube SWITCH is used to receive the target detection pulse signal EN, and the target detection pulse signal EN controls the on and off of the switch tube SWITCH, so that the second current source Ilarge provides current to the load end Vout when the switch tube SWITCH is turned on, or stops providing current to the outside when the switch tube SWITCH is turned off to reduce power consumption.

[0032] The load terminal is connected to the negative input terminal of the second comparator, sharing a voltage corresponding to Figure 1In the embodiment, the negative input terminal of the second comparator CMP2 is connected to the negative input terminal of the first comparator CMP1, and the negative input terminal of the second comparator CMP2 and the negative input terminal of the first comparator CMP1 are both connected to the load terminal Vout; the negative input terminal of the second comparator CMP2 is used to receive the voltage automatically adjusted due to the change of the resistance value of the load module, especially to receive the voltage automatically adjusted due to the change of the resistance value of the load module within the pulse width of the target detection pulse signal EN, the adjusted voltage can reflect the connection status of the load module at the load terminal Vout, can affect the first level comparison signal CMPOUT, and then affect the on and off state of the switch tube SWITCH through the delay processing circuit.

[0033] The output end of the second comparator CMP2 is connected to the clock end CK of the trigger; wherein, the output end Q of the second comparator CMP2 is the output end of the second load detection circuit; thereby, the second level comparison signal output by the second comparator CMP2 is set as the driving clock signal of the trigger, and the second comparator CMP2 can adjust the second level comparison signal it outputs according to the voltage change at the load end Vout to control the transmission and latching state of the trigger for the first level comparison signal CMPOUT.

[0034] The second comparator CMP2 is used to output a second level comparison signal to the clock terminal CK of the trigger according to the magnitude relationship between the voltage received at its negative input terminal and the second reference voltage VREF2 under the control of the target detection pulse signal EN. The trigger DFF is configured to start collecting the first level comparison signal CMPOUT at the rising edge of the second level comparison signal; the delay processing circuit is used to delay the first level comparison signal CMPOUT to the target detection pulse signal EN, and then output the target detection pulse signal EN to the reset terminal RB of the trigger DFF and the enable terminal of the second comparator CMP2 respectively; thereby, under the control of the target detection pulse signal EN, the second level comparison signal is used to drive the trigger to transmit the first level comparison signal CMPOUT or reset the trigger.

[0035] When the magnitude relationship between the voltage received at the negative input terminal of the second comparator CMP2 and the second reference voltage VREF2 changes within the pulse width of the target detection pulse signal, the second level comparison signal changes. Specifically, when the voltage received at the negative input terminal of the second comparator becomes greater than the second reference voltage VREF2, the second level comparison signal is set to a low level, indicating that the load end is sensed to have a larger resistance value, and it can be determined that the load end is not connected to the load module, for example, it is detected that the load module and the load end detection circuit do not meet the conditions for establishing an electrical connection; when the voltage received at the negative input terminal of the second comparator becomes less than the second reference voltage VREF2, the second level comparison signal is set to a high level, indicating that the load end is sensed to have a smaller resistance value, and it is smaller than the resistance value detected when the first level comparison signal is set to a high level, then within the pulse width of the target detection pulse signal, combined with the situation that the first level comparison signal is set to a high level, it is more precisely determined that the load end has been connected to the load module, and it is detected that the physically connected load module and the load end detection circuit meet the conditions for establishing an electrical connection. Therefore, under the control of the target detection pulse signal EN, the second comparator CMP2 compares the size relationship between the load end Vout and the second reference voltage, and the second level comparison signal and the first level comparison signal jointly determine the connection status of the load module within a limited time to control the overall power consumption. This is suitable for accurately detecting the connection of capacitive / resistive loads in a large power consumption load detection circuit.

[0036] It is worth noting that only when the first comparator CMP1 outputs a high level, the switch tube between the second comparator CMP2 and the second current source Ilarge is turned on, and the current output by the second current source Ilarge is sent to the load module, so that the impedance element with a smaller resistance value connected to it can be detected at the load terminal Vout, provided that the second reference voltage VREF2 cannot be configured too small to prevent large detection errors. In order to prevent the second reference voltage VREF2 from being set too low, it is necessary to use a current source with a larger current value to power the load module, and then compare it with the second reference voltage VREF2. For example, if the second reference voltage VREF2 is 110mV, the constant current output by the second current source Ilarge is 100mA, and the resistance value of the load module connected to the load terminal Vout is below 1.1 ohms, the second comparator CMP2 can start to output a high level, and the corresponding logic level is logic 1.

[0037] When the load-end detection circuit is embedded in a low-power chip or connected to a low-power chip, if the first load detection circuit allows only a few hundred nA of current to flow through the load end, and the equivalent resistance of the human body is equal to several hundred K ohms, the voltage drop generated after receiving several hundred nA is still lower than the second reference voltage and the first reference voltage. Therefore, the present application designs the second comparator CMP2 and connects the second current source Ilarge (generating a current close to 100mA). After flowing through the human body, a large voltage will be generated at the load end Vout, which is higher than the second reference voltage. The second comparator CMP2 will not output a high level to detect the scenario of false detection of the human body. Even if the voltage generated by the load end Vout is lower than the first reference voltage, it can be determined that the load end Vout is not connected to the load module, that is, it is detected that the load module and the load-end detection circuit do not meet the conditions for establishing an electrical connection.

[0038] In summary, the first load detection circuit and the second load detection circuit divide the load end detection circuit into two parts according to the detection process, and can be divided into two parts of micro-power load detection and high-power load detection in combination with the first current source and the second current source. The micro-power load detection is used as an enable for the high-power load detection. When the micro-power load detection (corresponding to the first load detection circuit) detects that a capacitive / resistive load is connected, the high-power load detection (corresponding to the second load detection circuit) is enabled to limit the power consumption, thereby performing relatively accurate load detection. It not only enhances the anti-interference ability, but also can detect load modules with smaller resistance values.

[0039] like Figure 1 As shown, the delay processing circuit includes an AND gate AND and a delay device DLY; the AND gate AND includes two input terminals and one output terminal; the delay device DLY includes one input terminal and one output terminal; the input terminal of the delay device DLY is connected to one input terminal of the AND gate AND, and the common connection terminal is the input terminal of the delay processing circuit, then the delay device DLY is used to perform delay processing on the first level comparison signal CMPOUT to obtain a signal that can perform a logical operation with the first level comparison signal CMPOUT and changes with the change of the delay time length. The delay device is used to control the first level comparison signal CMPOUT to be inverted and output according to a certain delay time to obtain a target delay signal, such as Figure 2 As shown in CMPOUT_DLY, it is a high level before time t2, including the pulse width Tdly of the target detection pulse signal EN, and is a low level after time t2; wherein the pulse width of the target detection pulse signal EN is the certain delay time.

[0040] The output end of the delay device DLY is connected to the other input end of the AND gate AND, and one output end of the AND gate AND is the output end of the delay processing circuit. The AND gate is used to control the first level comparison signal CMPOUT and the target delay signal CMPOUT_DLY to perform an AND operation, and output the target detection pulse signal EN, so that the level logic value corresponding to the first level comparison signal CMPOUT and the level logic value corresponding to the target delay signal CMPOUT_DLY are equal within the pulse width Tdly of the target detection pulse signal EN, and are both equal to logic 1, corresponding to Figure 2 Therefore, the AND gate AND is used to perform an AND operation on the output signal of the delay device DLY and the first level comparison signal CMPOUT to extract the pulse width of the target detection pulse signal EN as a valid signal for enabling the second load detection circuit in the stage where the load module is connected to the load end.

[0041] In one embodiment, the delay device includes an odd number of inverters connected in series, each inverter generating a transmission delay for its input signal; the odd number of inverters are used to sequentially perform an inversion operation on the first level comparison signal CMPOUT, and then set the signal output by the last inversion as the target delay signal CMPOUT_DLY, the total cumulative transmission delay generated by the odd number of inverters is equal to the pulse width of the target detection pulse signal EN, so that the delay time generated by the target delay signal CMPOUT_DLY relative to the first level comparison signal CMPOUT is equal to the pulse width of the target detection pulse signal EN, and the pulse width of the target detection pulse signal is greater than a preset time threshold, thereby avoiding interference caused by too short a load module access time, that is, eliminating the interference of jitter phenomenon caused by short-time plugging and unplugging of load components.

[0042] As an embodiment, when the voltage received at the negative input terminal of the first comparator is less than the first reference voltage, and the voltage received at the negative input terminal of the second comparator is less than the second reference voltage, if the first level comparison signal and the second level comparison signal have rising edges successively, the logic level of the output terminal of the trigger is set to logic 1, and then it is detected that the load module and the load-end detection circuit meet the conditions for establishing electrical connection, and it is determined that the load module has been plugged into the load end within the pulse width of the target detection pulse signal. Specifically, in combination Figure 1 and Figure 2It can be seen that when the load terminal Vout is connected to the load module, the switch tube SWITCH is turned on within the pulse width of the target detection pulse signal EN, and the voltage received at the negative input terminal - of the second comparator CMP2 is less than the second reference voltage VREF2, so that the output terminal of the second comparator CMP2 generates a rising edge to the clock terminal CK of the trigger DFF, and then drives the trigger DFF to output the first level comparison signal CMPOUT, and sets the logic level of the output terminal of the trigger DFF to logic 1, corresponding to the signal LOADON shown in the figure, and completes the detection according to the logic level of the output terminal of the trigger within the pulse width Tdly of the target detection pulse signal shown in the figure, because the second comparator CMP2 is not enabled to work in the time period outside the pulse width Tdly of the target detection pulse signal shown in the figure; in this embodiment, the second level comparison signal includes a rising edge, so the signal output by the second comparator CMP2 needs to be flipped from logic 0 to logic 1, and the voltage received at the negative input terminal - of the second comparator CMP2 is less than the second reference voltage VREF2.

[0043] On the other hand, when the voltage received by the negative input terminal of the first comparator is greater than the first reference voltage, the logic level of the first level comparison signal is set to logic 0, so that the logic level of the output terminal of the trigger DFF is set to logic 0, and then it is detected that the load module has been unplugged from the load terminal. Figure 1 and Figure 2 It can be seen that when the load terminal Vout is not connected to the load module, the switch tube SWITCH is not turned on, and the logic level of the output terminal of the first comparator is set to logic 0, and the first level comparison signal CMPOUT is configured to a low level to reset the trigger DFF, and then the logic level of the output terminal of the trigger DFF is directly set to logic 0, which is not affected by the signal output by the second comparator CMP2; wherein, the voltage received by the negative input terminal - of the second comparator CMP2 is greater than the second reference voltage VREF2, so that the output terminal of the second comparator CMP2 does not generate a rising edge to the clock terminal CK of the trigger DFF, but sets the signal LOADON output by the second comparator CMP2 to a low level. Thereby, according to the magnitude relationship between the voltage received by its negative input terminal and the second reference voltage, the second level comparison signal is output to the clock terminal of the trigger to start the trigger, and the trigger is reset according to the first level comparison signal.

[0044] In summary, according to the change of the resistance value of the load module connected to the load end, the voltage received by the input end of the first load detection circuit is automatically adjusted to change the first level comparison signal. On this basis, within the pulse width of the target detection pulse signal, according to the change of the resistance value of the load module connected to the load end, the voltage received by the input end of the second load detection circuit is automatically adjusted to change the second level comparison signal and the logic level of the output end of the trigger. Then, within the pulse width of the target detection pulse signal, the logic level of the output end of the trigger, the second level comparison signal, and / or the first level comparison signal are used to reflect that the load module is plugged into the load end. Therefore, it is achieved that: when the logic level of the output end of the trigger is set to logic 1, it is detected that the load module and the load end detection circuit meet the conditions for establishing an electrical connection, and it is determined that the load module has been plugged into the load end; when the logic level of the output end of the trigger is set to logic 0, it is detected that the load module has been unplugged from the load end.

[0045] In some embodiments, Figure 2 As shown, the load module is plugged in at time t0, the first current source keeps providing current to the load end Vout, the first comparator CMP1 delays the output of the first level comparison signal CMPOUT by comparing the voltages of the positive and negative input ends, and the first level comparison signal CMPOUT output at time t1 is set to a high level, so that it can be determined that the load module is plugged in to the load end, but it has not yet been determined whether the load module and the load end detection circuit meet the conditions for establishing an electrical connection, and a higher precision detection is required; the first level comparison signal CMPOUT is processed by the delay device DLY to obtain a target delay signal CMPOUT_DLY, wherein the target delay signal CMPOUT_DLY has a falling edge at time t2, and generates a delay time Tdly relative to time t1, and the delay time Tdly is equivalent to the delay length performed by the delay device DLY on the rising edge of the first level comparison signal CMPOUT. The target delay signal CMPOUT_DLY and the first level comparison signal CMPOUT are ANDed to generate the target detection pulse signal EN. The pulse width of the target detection pulse signal EN is an enabling time of Tdly. Figure 1The second comparator CMP2 and the second current source Ilarge shown are turned on to more accurately detect the connection status of the load module of the load end Vout. If a load module with a smaller resistance value is connected at this time, such as a load element with a 1 ohm, the second comparator CMP2 outputs a rising edge. Starting from time t1, the trigger DFF is driven to collect the first level comparison signal CMPOUT. After the transmission delay inside the trigger, the output signal LOADON of the trigger DFF is flipped from a low level to a high level (the level logic value corresponds to logic 1), and it is detected that the load module and the load end detection circuit meet the conditions for establishing an electrical connection, and it is determined that the load module has been plugged into the load end. If the resistance value of the load module is large enough, such as a load element with a 3 ohm, the second comparator CMP2 does not generate a rising edge, and the signal LOADON remains at a low level (the level logic value corresponds to logic 0), and it is detected that the load module and the load end detection circuit do not meet the conditions for establishing an electrical connection, but the load module may have been plugged into the load end.

[0046] exist Figure 2 In the example, the pulse width Tdly of the target detection pulse signal EN is from time t1 to time t2, and the second comparator CMP2, the second current source Ilarge and the second load detection circuit in which they are located only work within the pulse width Tdly. The second comparator CMP2, the second current source Ilarge and the second load detection circuit in which they are located do not work from time t0 to time t1, and from time t2 to time t4, so as to reduce the power consumption of the load-end detection circuit and eliminate the interference of the false access shorter than Tdly.

[0047] Combination Figure 2It can be seen that if it is determined before time t3 that the load module has been plugged into the load terminal Vout, then at time t3, the load module is unplugged from the load terminal Vout, and after a transmission delay, at time t4, the level logic value of the first level comparison signal CMPOUT becomes logic 0, and the first comparator CMP1 outputs a low level to the reset terminal RB of the trigger DFF, causing the trigger DFF to be reset immediately, thereby directly setting the output signal LOADON to a low level (the level logic value corresponds to logic 0), and is not affected by the output signal of the second comparator CMP2 (the clock terminal CK of DFF). At this time, the first comparator CMP1, the second comparator CMP2 and the trigger DFF all output low levels, so the load module can be detected to be unplugged based on the first comparator CMP1 and the second comparator CMP2 both output low levels (also determined as the load module is not connected, the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection); or the load module can be detected to be unplugged only based on the trigger DFF outputting a low level (also determined as the load module is not connected, the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection). After time t4, wait for the next time the load module is plugged in, and repeat the circuit detection method from time t0 to time t4, so as to achieve the purpose of saving power consumption and improving detection accuracy.

[0048] As an embodiment, the load module includes at least one load resistor and / or at least one load capacitor. Figure 1 As shown, in the load module, the load resistor and the load capacitor are connected in parallel, one end of the load resistor is grounded, and the other end of the load resistor is connected to the load end Vout, one end of the load capacitor is grounded, and the other end of the load capacitor is connected to the load end Vout; then the load module will form a resistance value, which represents the equivalent impedance value formed by the load resistor and the load capacitor in parallel. In the case of the constant current provided by the first current source and the constant current provided by the second current source within the pulse width of the target detection pulse signal, the resistance value of the load module increases, and the voltage of the negative input end of the second comparator CMP2 and the voltage of the negative input end of the first comparator CMP1 both increase; conversely, the resistance value of the load module decreases, and the voltage of the negative input end of the second comparator CMP2 and the voltage of the negative input end of the first comparator CMP1 both decrease. It is still necessary to determine whether the load module and the load end detection circuit meet the conditions for establishing electrical connection.

[0049] Therefore, when the load module is plugged into the load end, there are: When the resistance value of the load module is greater than the second preset resistance value, the voltage at the negative input terminal of the second comparator CMP2 is greater than the second reference voltage VREF2, and the logic level of the output terminal of the second comparator is set to logic 0 (corresponding to the second comparator outputting a second level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the second reference voltage), and the voltage at the negative input terminal of the first comparator CMP1 is greater than the first reference voltage VREF1, and the logic level of the output terminal of the first comparator is set to logic 0 (corresponding to the first comparator outputting a first level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the first reference voltage), thereby determining that the load module and the load-end detection circuit do not meet the conditions for establishing an electrical connection in combination with the foregoing embodiment, so as to detect that the load module is not connected. At this time, it can be understood that the load module is unstably plugged into the load end and is not suitable for establishing an electrical connection and performing master-slave communication. However, in some scenarios, the range of the resistance value of the load module can be detected based on the logic level of the output terminal of the first comparator and the logic level of the output terminal of the second comparator.

[0050] The scenario in which the resistance value of the load module is greater than the second preset resistance value includes a human hand touching the load end, and it can be considered that the human hand is connected to the load end. At this time, in the first load detection circuit, the current provided by the first current source Ismall is only a few hundred nA, and the resistance value of the human body is equivalent to a resistance of a few hundred K ohms. The voltage generated at the load end is still less than the first reference voltage VREF1, and the first level comparison signal CMPOUT output by the first comparator CMP1 is set to a high level. However, the human body obviously cannot establish an electrical connection with the load end, so the high level output by the first comparator CMP1 cannot be used as a detection result; then in the second load detection circuit, the second current source Ilarge (generating a current close to 100mA) will generate a large voltage at the load end Vout after flowing through the human body. After comparison by the second comparator CMP2, the voltage generated at the load end Vout is higher than the second reference voltage VREF2, and the second comparator CMP2 will not output a high level, so that the human body and the load end detection circuit do not meet the conditions for establishing an electrical connection, and it is determined that the load module is not connected, so as to overcome the impact of human body false detection.

[0051] When the resistance value of the load module is greater than or equal to the first preset resistance value, and the resistance value of the load module is less than or equal to the second preset resistance value, the voltage at the negative input terminal of the second comparator is greater than the second reference voltage, and the logic level of the output terminal of the second comparator is set to logic 0 (corresponding to the second comparator outputting a second level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the second reference voltage, and the second level comparison signal is set to a low level), and the voltage at the negative input terminal of the first comparator is less than the first reference voltage, and the logic level of the output terminal of the first comparator is set to logic 1 (corresponding to the first comparator outputting a second level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the first reference voltage). Considering the size relationship between the voltages, a first level comparison signal is output, and the first level comparison signal is set to a high level), it is determined that the load-end detection circuit and the load module do not meet the conditions for establishing an electrical connection, so as to detect that the load module is not connected. Combined with the target detection pulse signal EN processed by the delay processing circuit for the first level comparison signal, it can be understood that the load module is unstably plugged into the load end within the pulse width Tdly, and is not suitable for establishing an electrical connection and performing master-slave communication. However, in some scenarios, the range of the resistance value of the load module can be detected based on the logic level of the output end of the first comparator and the logic level of the output end of the second comparator.

[0052] It should be noted that the first preset resistance value is less than the second preset resistance value; the load-end detection circuit is applied to an electronic cigarette or other atomization terminal, preferably, the second preset resistance value is 2 ohms, and the first preset resistance value is 1 ohm, because the heating wire is often 1 ohm or 2 ohms, so that the human body is not mistakenly detected. When the resistance value of the load module is greater than the second preset resistance value, it can be considered that the impedance of the load module is large enough; when the resistance value of the load module is less than the first preset resistance value, it can be considered that the impedance of the load module is small enough.

[0053] When the resistance value of the load module is less than the first preset resistance value, the voltage at the negative input terminal of the second comparator is less than the second reference voltage, and the logic level of the output terminal of the second comparator is set to logic 1 (corresponding to the second comparator outputting a second level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the second reference voltage, and the second level comparison signal is set to a high level), and the voltage at the negative input terminal of the first comparator is less than the first reference voltage, and the logic level of the output terminal of the first comparator is set to logic 1 (corresponding to the first comparator outputting a first level comparison signal according to the magnitude relationship between the voltage received at its negative input terminal and the first reference voltage, and the first level comparison signal is set to a high level), combined with the processing of the first level comparison signal by the delay processing circuit, it is determined that within the pulse width of the target detection pulse signal, the load module and the load-end detection circuit meet the conditions for establishing an electrical connection, so as to detect that the load module is connected, otherwise this detection method is not applicable outside the pulse width of the target detection pulse signal.

[0054] Based on the above embodiment, within the pulse width of the target detection pulse signal, if the logic level of the output end of the second comparator is set to logic 1, the logic level of the output end of the first comparator is set to logic 1, then it is determined that the load module and the load-end detection circuit meet the conditions for establishing an electrical connection, so that the load module is detected to be connected within the pulse width of the target detection pulse signal. Within the pulse width of the target detection pulse signal, if the logic level of the output end of the second comparator is set to logic 0, and the logic level of the output end of the first comparator is set to logic 1 or logic 0, then it is determined that the load module and the load-end detection circuit do not meet the conditions for establishing an electrical connection, so that the load module is detected to be not connected within the pulse width of the target detection pulse signal. Thus, the power consumption consumed by the load-end detection circuit in the process of detecting the load end is limited by setting the pulse width of the target detection pulse signal. In summary, the load-end detection circuit is adapted to a variety of load detection scenarios to improve detection accuracy.

[0055] Based on the above embodiments, the present application further discloses a load detection method, which is used to detect the access status of the load module using the load end detection circuit disclosed in the above embodiments, and the execution subject of the load detection method is a controller outside the load end detection circuit. The load detection method includes: When the logic level of the first level comparison signal is set to logic 1, and the logic level of the second level comparison signal is set to logic 1, it is determined that the load-end detection circuit and the load module meet the conditions for establishing an electrical connection, so as to detect that the load module is connected to the load-end detection circuit. At this time, based on the trigger and delay processing circuit included in the load-end detection circuit disclosed in the aforementioned embodiment, it can be known that the logic level of the second level comparison signal is set to logic 1, and the logic level of the first level comparison signal is set to logic 1, driving the logic level of the output end of the trigger to be set to logic 1. It can be understood that if the first level comparison signal and the second level comparison signal have rising edges successively, the logic level of the output end of the trigger is set to logic 1; then it is detected that the load module and the load-end detection circuit meet the conditions for establishing an electrical connection, and it is determined that the load module has been plugged into the load end within the pulse width of the target detection pulse signal.

[0056] It should be noted that, when the logic level of the second level comparison signal remains at logic 1, if the voltage at the load end increases because the load module is unplugged from the load end or contacts the human body, the logic level of the first level comparison signal will first be flipped to logic 0. Since there is a transmission delay between the first load detection circuit and the second load detection circuit, at the flipping moment of the first level comparison signal, the logic level of the second level comparison signal may still be set to logic 1. Therefore, when the logic level of the first level comparison signal is set to logic 0 and the logic level of the second level comparison signal is set to logic 1, it is determined that the load-end detection circuit and the load module do not meet the conditions for establishing an electrical connection.

[0057] When the logic level of the first level comparison signal is set to logic 0, it is determined that the load-end detection circuit and the load module do not meet the conditions for establishing an electrical connection, so as to detect that the load module is not connected to the load-end detection circuit. Specifically, when the voltage received by the load end becomes greater than the first reference voltage VREF1, the first level comparison signal is set to a low level, indicating that the load end is sensed to have a larger resistance value, and it can be preliminarily determined that the load end is not connected to the load module, and it can be detected that the load module is not plugged into the load end. At this time, based on the trigger and delay processing circuit included in the load-end detection circuit disclosed in the aforementioned embodiment, it can be known that the logic level of the second level comparison signal is also set to logic 0, and the logic level of the first level comparison signal is set to logic 0, so that the logic level of the output end of the trigger is set to logic 0, and it is detected that the load module has been unplugged from the load end.

[0058] To summarize, the load detection method determines the electrical connection relationship between the load-end detection circuit and the load module based on the level state of the second level comparison signal and / or the first level comparison signal, and determines whether the load module is plugged into the load end, thereby improving detection accuracy compared to using a single load detection level state for detection.

[0059] In some embodiments, when the logic level of the second level comparison signal remains at logic 1, the logic level of the first level comparison signal is set to logic 1; when the second level comparison signal changes, the logic level of the first level comparison signal is allowed to remain at logic 1. From the perspective of the voltage borne by the resistance value of the load module, the comparison voltage threshold required by the first load detection circuit to detect the load module is higher than the comparison voltage threshold required by the second load detection circuit to detect the load module. The minimum voltage value of the load end allowed to be detected by the first load detection circuit is greater than the minimum voltage value of the load end detected by the second load detection circuit, so that: if the voltage at the load end changes under the condition of being lower than the comparison voltage threshold required by the first load detection circuit to detect the load module, even if the second level comparison signal changes, the logic level of the first level comparison signal is maintained at logic 1; if the voltage at the load end changes under the condition of being lower than the comparison voltage threshold required by the second load detection circuit to detect the load module, the logic level of the second level comparison signal and the logic level of the first level comparison signal are both maintained at logic 1.

[0060] The maximum voltage value of the load end allowed to be detected by the first load detection circuit is greater than the maximum voltage value of the load end detected by the second load detection circuit; on this basis, if the voltage at the load end changes when it is higher than the comparison voltage threshold required by the first load detection circuit to detect the load module, the logic levels of the second level comparison signal and the first level comparison signal are both kept set to logic 0; if the voltage at the load end changes when it is higher than the comparison voltage threshold required by the second load detection circuit to detect the load module, even if the first level comparison signal changes, the logic level of the second level comparison signal is kept set to logic 0, and when the first load detection circuit enables control of the second load detection circuit through the first level comparison signal, after the first level comparison signal is flipped to logic 0, the logic level of the second level comparison signal will be set to 0.

[0061] In some embodiments, when the logic level of the first level comparison signal remains at logic 1, it is determined that the load module has been plugged into the load end, that the first load detection circuit has started detection, and that the load end Vout exists. It is preliminarily determined that the load module has been physically plugged in, but it is necessary to enable and control the second load detection circuit for further detection to determine whether the load module and the load end Vout meet the conditions for electrical connection, including detecting the resistance range of the resistance value of the load module, thereby improving the detection accuracy. Therefore, the first level comparison signal can be used to enable and control the second load detection circuit and the first load detection circuit to perform a fine detection of the preliminary detection result of the load end Vout.

[0062] It can be understood that when the voltage received by the load end becomes less than the first reference voltage VREF1, the first level comparison signal is set to a high level, indicating that the load end senses that the resistance value becomes smaller, and it can be preliminarily determined that the load end is connected to the load module, and it can be detected that the load module is plugged into the load end. Therefore, the first comparator compares the magnitude relationship between the voltage at the load end Vout and the first reference voltage, and based on this comparison result, the first level comparison signal represents the connection status of the load module, which is suitable for detecting the scene of the connection of a small resistance load.

[0063] In some embodiments, when the logic level of the first level comparison signal is set to logic 1 and the logic level of the second level comparison signal is set to logic 0, it is determined that the load-end detection circuit and the load module do not meet the conditions for establishing electrical connection, so as to detect that the load module is not connected to the load-end detection circuit. In this embodiment, when the logic level of the first level comparison signal is set to logic 1, when the voltage received by the load end becomes greater than the second reference voltage VREF2, the second level comparison signal is set to a low level, indicating that the resistance value sensed by the load end becomes larger, and it can be determined that the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection; specifically, within the pulse width of the target detection pulse signal, combined with the situation that the first level comparison signal is set to a high level, it is more accurately determined that the load module that has been physically connected to the load end (has been plugged into the load end) has not met the conditions for establishing electrical connection with the load-end detection circuit. Therefore, under the control of the target detection pulse signal EN, by comparing the magnitude relationship between the voltage at the load end Vout and the second reference voltage, the connection status of the load module is determined by the second level comparison signal and the first level comparison signal.

[0064] In some embodiments, when the time that the logic level of the second level comparison signal maintains logic 1 is less than the pulse width of the target detection pulse signal, the load module is set to be not connected to the load-end detection circuit, thereby setting the pulse width of the target detection pulse signal to the insertion error detection time threshold of the load module. When the load access time is shorter than the error detection time threshold, it is detected that the load-end detection circuit is not connected, thereby eliminating false access interference that is shorter than the error detection time threshold.

[0065] Furthermore, in the load-end detection circuit, the power consumption required for the first load detection circuit to work is less than the power consumption required for the second load detection circuit to work, thereby setting the first load detection circuit to a low-power detection circuit and setting the second load detection circuit to a high-power detection circuit; this embodiment utilizes the first load detection circuit as an enable control circuit for the second load detection circuit, and sets the high-power detection circuit to obtain a valid detection result only within a high-level duration length Tdly after the load module is connected, thereby limiting power consumption and taking into account accuracy. If the load module connection time is not long enough, it is considered that the load module is not connected, that is, the load module and the load-end detection circuit do not meet the conditions for establishing an electrical connection, thereby eliminating interference and preventing glitch-type false detection.

[0066] As an embodiment, when the load module is plugged into the load end, there exists: When the logic level of the first level comparison signal is set to logic 0 and the logic level of the second level comparison signal is set to logic 0, it is detected that the resistance value of the load module is greater than the second preset resistance value, thereby detecting the range of the resistance value of the load module; the relevant controller detects that the resistance value of the load module is too large, and it can even be considered that the load end is in contact with the human body or physically contacts the load module and is pulled up by the first current source to be greater than the first reference voltage; and then combined with the above-mentioned embodiment, it is determined that the load module and the load end detection circuit do not meet the conditions for establishing an electrical connection, so as to detect that the load module is not connected. At this time, it can be understood that the load module is unstably plugged into the load end and is not suitable for establishing an electrical connection and conducting master-slave communication.

[0067] In some embodiments, the scenario in which the resistance value of the load module is greater than the second preset resistance value includes a human hand touching the load end, and it can be considered that the human hand is connected to the load end. At this time, in the first load detection circuit, the current provided by the first current source Ismall is only a few hundred nA, and the resistance value of the human body is equivalent to a resistance of several hundred K ohms. The voltage generated at the load end is still less than the first reference voltage VREF1, and the first level comparison signal CMPOUT output by the first comparator CMP1 is set to a high level. However, the human body obviously cannot establish an electrical connection with the load end, so the high level output by the first comparator CMP1 cannot be used as a detection result; then in the second load detection circuit, the second current source Ilarge (generating a current close to 100mA) will generate a large voltage at the load end Vout after flowing through the human body. After comparison by the second comparator CMP2, the voltage generated at the load end Vout is higher than the second reference voltage VREF2, and the second comparator CMP2 will not output a high level, so that the human body and the load end detection circuit do not meet the conditions for establishing an electrical connection, and it can be determined that the load module is not connected to overcome the impact of human body false detection.

[0068] Within the pulse width of the target detection pulse signal disclosed in the aforementioned embodiment, when the logic level of the first level comparison signal is set to logic 1 and the logic level of the second level comparison signal is set to logic 0, it is detected that the resistance value of the load module is greater than or equal to the first preset resistance value, and the resistance value of the load module is less than or equal to the second preset resistance value, thereby detecting the range of the resistance value of the current load module, and determining that the load-end detection circuit and the load module do not meet the conditions for establishing an electrical connection, so as to detect that the load module is not connected. Combined with the target detection pulse signal processed by the delay processing circuit on the first level comparison signal, it can be understood that the load module is unstably plugged into the load end within the pulse width and is not suitable for establishing an electrical connection and conducting master-slave communication.

[0069] Wherein, the first preset resistance value is less than the second preset resistance value; the load-end detection circuit is applied to an electronic cigarette or other atomization terminal, preferably, the second preset resistance value is 2 ohms, and the first preset resistance value is 1 ohm, because the heating wire is often 1 ohm or 2 ohms, so that the human body is not mistakenly detected. When the resistance value of the load module is greater than the second preset resistance value, it can be considered that the impedance of the load module is large enough; when the resistance value of the load module is less than the first preset resistance value, it can be considered that the impedance of the load module is small enough.

[0070] Within the pulse width of the target detection pulse signal disclosed in the aforementioned embodiment, when the logic level of the first level comparison signal is set to logic 1 and the logic level of the second level comparison signal is set to logic 1, it is detected that the resistance value of the load module is less than the first preset resistance value, thereby detecting the range of the resistance value of the current load module; at the same time, combined with the processing of the first level comparison signal in the aforementioned embodiment, it is determined that within the pulse width of the target detection pulse signal, the load module and the load-end detection circuit meet the conditions for establishing an electrical connection, so as to detect that the load module is connected.

[0071] It should be noted that the load module includes at least one load resistor and / or at least one load capacitor. Figure 1 As shown, in the load module, the load resistor and the load capacitor are connected in parallel, one end of the load resistor is grounded, and the other end of the load resistor is connected to the load end Vout, one end of the load capacitor is grounded, and the other end of the load capacitor is connected to the load end Vout; then the load module will form a resistance value, which represents the equivalent impedance value formed by the load resistor and the load capacitor in parallel, and in the case of a constant current provided by the first current source and a constant current provided by the second current source within the pulse width of the target detection pulse signal, when the voltage at the negative input end of the second comparator CMP2 and the voltage at the negative input end of the first comparator CMP1 both increase, it is detected that the resistance value of the load module increases; conversely, when the voltage at the negative input end of the second comparator CMP2 and the voltage at the negative input end of the first comparator CMP1 both decrease, it is detected that the resistance value of the load module decreases.

[0072] In summary, the load-end detection circuit can be used to detect resistance values ​​with more precision and adapt to various load detection scenarios to improve detection accuracy.

[0073] The target detection pulse signal is a positive pulse signal of a certain time width output by the delay processing circuit, that is, a single output pulse of a specified width, that is, "high" or "low", which not only allows the switch tube set in the second load detection circuit to be turned on to the ground for rapid discharge, but also allows the comparator set in the second load detection circuit to periodically control the transmission and latching of the trigger to continuously detect the latest connected load module. Within the pulse width of the target detection pulse signal, if the logic level of the second level comparison signal is set to logic 1, and the logic level of the first level comparison signal is set to logic 1, it is determined that the load module and the load-end detection circuit meet the conditions for establishing electrical connection, so that the connection of the load module is detected within the pulse width of the target detection pulse signal. Within the pulse width of the target detection pulse signal, if the logic level of the second level comparison signal is set to logic 0, and the logic level of the first level comparison signal is set to logic 1 or logic 0, it is determined that the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection, so that the load module is detected to be not connected within the pulse width of the target detection pulse signal. Therefore, the power consumption of the load-end detection circuit in the process of detecting the load end is limited by setting the pulse width of the target detection pulse signal.

[0074] The device implementation described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present implementation scheme. Those of ordinary skill in the art may understand and implement it without creative work.

Claims

1. A load-end detection circuit, characterized in that: The load end detection circuit comprises a load end, a first load detection circuit and a second load detection circuit, wherein the first load detection circuit and the second load detection circuit are both connected to the load end; the load end is used to connect a load module outside the load end detection circuit; The first load detection circuit is connected to the second load detection circuit; A first load detection circuit, configured to output a first level comparison signal according to a magnitude relationship between a voltage sensed at the load end and a first reference voltage set internally; A second load detection circuit is used to output a second level comparison signal according to the magnitude relationship between the voltage sensed at the load end and a second reference voltage set internally under the control of the first level comparison signal, so that the second level comparison signal and / or the first level comparison signal reflects the connection status of the load module at the load end; The second reference voltage is lower than the first reference voltage.

2. The load-end detection circuit according to claim 1, characterized in that: The load-end detection circuit also includes a delay processing circuit and a trigger; The output end of the first load detection circuit is connected to the enable end of the second load detection circuit through the delay processing circuit, the reset end of the trigger and the data input end of the trigger are both connected to the output end of the first load detection circuit, and the output end of the second load detection circuit is connected to the clock end of the trigger; The delay processing circuit is used to delay the first level comparison signal into a target detection pulse signal, and then output the target detection pulse signal to the reset end of the trigger and the enable end of the second load detection circuit respectively, so as to enable the second load detection circuit to output the second level comparison signal and enable the trigger to transmit the first level comparison signal within the pulse width of the target detection pulse signal, and also to enable the signal output by the trigger to reflect the connection status of the load module at the load end within the pulse width of the target detection pulse signal.

3. The load-end detection circuit according to claim 2, characterized in that: A first current source is provided inside the first load detection circuit; the first current source is used to provide a constant current, and according to the change of the resistance value of the load module, the voltage received by the load end is automatically adjusted to change the first level comparison signal; A second current source is provided inside the second load detection circuit; The second current source is used to provide a constant current under the control of the target detection pulse signal, and to drive the voltage received by the load end to automatically adjust according to the change of the resistance value of the load module, so as to change the second level comparison signal; Among them, the constant current provided by the first current source is smaller than the constant current provided by the second current source, so that the power consumption generated by the first load detection circuit is lower than the power consumption generated by the second load detection circuit; and, the current value of the constant current provided by the first current source is smaller than the current value of the constant current provided by the second current source.

4. The load-end detection circuit according to claim 3, characterized in that: The first load detection circuit includes a first comparator, a negative input terminal of the first comparator is connected to the output terminal of the first current source, and the negative input terminal of the first comparator is used to receive the voltage automatically adjusted due to the change of the resistance value of the load module; the positive input terminal of the first comparator is used to access the first reference voltage, and the output terminal of the first comparator is connected to the input terminal of the delay processing circuit; The first comparator is used for outputting a first level comparison signal to the delay processing circuit to generate the target detection pulse signal according to the magnitude relationship between the voltage received at its negative input terminal and the first reference voltage; The load end is connected to the negative input end of the first comparator; the output end of the first comparator is the output end of the first load detection circuit.

5. The load end detection circuit according to claim 4, characterized in that: The second load detection circuit includes a second comparator and a switch tube, wherein two transmission terminals of the switch tube are respectively connected to the output terminal of the second current source and the negative input terminal of the second comparator, and the control terminal of the switch tube is connected to the output terminal of the delay processing circuit; The positive input terminal of the second comparator is used to access the second reference voltage; the control terminal of the switch tube and the enable terminal of the second comparator are both connected to the output terminal of the delay processing circuit, wherein the control terminal of the switch tube and the enable terminal of the second comparator are both enable terminals of the second load detection circuit; The control end of the switch tube is used to receive the target detection pulse signal, and the target detection pulse signal controls the on and off of the switch tube, so that the second current source provides current to the load end when the switch tube is on, or stops providing current when the switch tube is off; wherein the load end is connected to the negative input end of the second comparator; the negative input end of the second comparator is used to receive the voltage automatically adjusted due to the change of the resistance value of the load module; The output end of the second comparator is connected to the clock end of the trigger; wherein the output end of the second comparator is the output end of the second load detection circuit; The second comparator is used to output a second level comparison signal to the clock terminal of the trigger according to the magnitude relationship between the voltage received at its negative input terminal and the second reference voltage under the control of the target detection pulse signal; Within the pulse width of the target detection pulse signal, when the magnitude relationship between the voltage received by the negative input terminal of the second comparator and the second reference voltage changes, the second level comparison signal changes.

6. The load-end detection circuit according to claim 5, characterized in that: The delay processing circuit includes an AND gate and a delay device; The input end of the delay device is connected to an input end of the AND gate, and the common connection end thereof is the input end of the delay processing circuit; The output end of the delay device is connected to another input end of the AND gate, and the output end of the AND gate is the output end of the delay processing circuit; The delay device is used to control the first level comparison signal to be inverted and output according to a certain delay time to obtain a target delayed signal; wherein the pulse width of the target detection pulse signal is the certain delay time; The AND gate is used to control the first level comparison signal and the target delay signal to perform an AND operation, and output the target detection pulse signal, so that the level logic value corresponding to the first level comparison signal and the level logic value corresponding to the target delay signal are equal within the pulse width of the target detection pulse signal.

7. The load-end detection circuit according to claim 6, characterized in that: The delay device includes an odd number of inverters connected in series; the odd number of inverters are used to perform an inversion operation on the first level comparison signal in sequence, and then set the signal output by the last inversion as a target delay signal, so that the delay time generated by the target delay signal relative to the first level comparison signal is equal to the pulse width of the target detection pulse signal.

8. The load-end detection circuit according to claim 5, characterized in that: When the voltage received at the negative input terminal of the first comparator is less than the first reference voltage, and the voltage received at the negative input terminal of the second comparator is less than the second reference voltage, if the first level comparison signal and the second level comparison signal have rising edges successively, the logic level of the output terminal of the trigger is set to logic 1, and then it is detected that the load module meets the conditions for establishing electrical connection with the load-end detection circuit, and it is determined that the load module has been plugged into the load end within the pulse width of the target detection pulse signal; When the voltage received at the negative input terminal of the first comparator is greater than the first reference voltage, the logic level of the first level comparison signal is set to logic 0, so that the logic level of the output terminal of the trigger is set to logic 0, and it is detected that the load module has been unplugged from the load terminal.

9. The load-end detection circuit according to claim 5, characterized in that: When the load module is plugged into the load end, there exists: When the resistance value of the load module is greater than the second preset resistance value, the logic level of the output end of the second comparator is set to logic 0, and the logic level of the output end of the first comparator is set to logic 0, and it is determined that the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection, so as to detect that the load module is not connected; When the resistance value of the load module is greater than or equal to the first preset resistance value, and the resistance value of the load module is less than or equal to the second preset resistance value, the logic level of the output end of the second comparator is set to logic 0, and the logic level of the output end of the first comparator is set to logic 1, and it is determined that within the pulse width of the target detection pulse signal, the load module and the load-end detection circuit do not meet the conditions for establishing electrical connection, so as to detect that the load module is not connected; wherein the first preset resistance value is less than the second preset resistance value; When the resistance value of the load module is less than the first preset resistance value, the logic level of the output end of the second comparator is set to logic 1, and the logic level of the output end of the first comparator is set to logic 1, and it is determined that within the pulse width of the target detection pulse signal, the load module and the load-end detection circuit meet the conditions for establishing electrical connection, so as to detect that the load module is connected; Wherein, the load module includes at least one load resistor and / or at least one load capacitor.

10. A load detection method, characterized in that: The load detection method uses the load-end detection circuit described in any one of claims 1 to 9 to detect the access status of the load module; The load detection method includes: When the logic level of the first level comparison signal is set to logic 1, and the logic level of the second level comparison signal is set to logic 1, it is determined that the load-end detection circuit and the load module meet the conditions for establishing electrical connection, so as to detect that the load module is connected to the load-end detection circuit; When the logic level of the first level comparison signal is set to logic 0, it is determined that the load-end detection circuit and the load module do not meet the condition for establishing electrical connection, so as to detect that the load module is not connected to the load-end detection circuit.

11. The load detection method according to claim 10, characterized in that: When the logic level of the first level comparison signal is set to logic 1, and the logic level of the second level comparison signal is set to logic 0, it is determined that the load-end detection circuit and the load module do not meet the condition for establishing electrical connection, so as to detect that the load module is not connected to the load-end detection circuit; When the time during which the logic level of the second level comparison signal maintains logic 1 is shorter than the pulse width of the target detection pulse signal, it is determined that the load-end detection circuit and the load module do not meet the condition for establishing electrical connection.

12. The load detection method according to claim 10, characterized in that: When the load module is plugged into the load end, there exists: When the logic level of the first level comparison signal is set to logic 0 and the logic level of the second level comparison signal is set to logic 0, it is detected that the resistance value of the load module is greater than a second preset resistance value; When the logic level of the first level comparison signal is set to logic 1 and the logic level of the second level comparison signal is set to logic 0 within the pulse width of the target detection pulse signal, it is detected that the resistance value of the load module is greater than or equal to the first preset resistance value, and the resistance value of the load module is less than or equal to the second preset resistance value, wherein the first preset resistance value is less than the second preset resistance value; Within the pulse width of the target detection pulse signal, when the logic level of the first level comparison signal is set to logic 1 and the logic level of the second level comparison signal is set to logic 1, it is detected that the resistance value of the load module is less than the first preset resistance value.

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