Failure chip analysis method and device for system-in-package module
By identifying and analyzing the position and electrical parameters of the chips in the system-level packaging module, the problem of poor analysis accuracy of failure chips in the prior art is solved, achieving higher analysis accuracy and lower risk of chip damage.
Patent Information
- Application Number
- CN202411466774.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-28
AI Technical Summary
The analysis methods of failed chips in existing system-level packaging modules are poor in accuracy, and commonly used laser opening and physical cutting methods may cause physical damage to the lead and circuit connection.
By identifying the position of each chip in the system-level packaging module, determining the target open-closing position according to the type and position of the chip, obtaining the internal circuit schematic, and detecting the electrical parameters of the chip at the target open-closing position to determine the failed chip.
This method can ensure that different open sealing positions are determined for different types of chips, prevent chip damage, and improve the accuracy of failure chip analysis through electrical parameter analysis.
Smart Images
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Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technology, and in particular to a method and device for analyzing failed chips in a system-level packaging module. Background Art
[0002] System-in-Package is a technology that integrates multiple functional chips (such as processors, memory, sensors, etc.) into one package. The advantages of system-in-packaging technology are that it can improve integration, reduce volume, reduce costs, and enable high-speed interconnection between multiple chips. However, with the increase in integration, the complexity of the system-in-packaging module has also greatly increased, which has brought new challenges to failure analysis.
[0003] The existing analysis method for failed chips in system-level packaging modules is mainly achieved through laser decapsulation and physical cutting, but this may cause physical damage to the leads and circuit connections, resulting in poor accuracy of subsequent analysis. Summary of the invention
[0004] The present application provides a method and device for analyzing a failed chip of a system-level packaging module to solve the problem of poor accuracy of existing failed chip analysis.
[0005] The first aspect of the present application provides a method for analyzing failed chips in a system-level packaging module, comprising the following steps: identifying the position of each chip in the system-level packaging module, and determining a target unsealing position of the corresponding chip according to the position and type of each chip; obtaining an internal circuit schematic of the system-level packaging module; detecting electrical parameters of the chip at the target unsealing position, and determining the analysis results of failed chips in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip.
[0006] Optionally, locating the failed chip according to the internal circuit schematic and the electrical parameters of each chip includes: determining the reference parameters of each chip according to the internal circuit schematic; if the electrical parameters are consistent with the reference parameters, determining that the corresponding chip is not failed; if the electrical parameters are inconsistent with the reference parameters, determining that the corresponding chip is failed.
[0007] Optionally, determining the target unsealing position of the corresponding chip according to the position and type of each chip includes: determining the allowable unsealing range of the corresponding chip according to the type of each chip; and determining the target unsealing position of the corresponding chip according to the position of each chip and the allowable unsealing range of the corresponding chip.
[0008] Optionally, the chip types include wire bonding type and flip chip type. After determining the analysis results of the failed chips in the system-level packaging module based on the internal circuit schematic and the electrical parameters of each chip, it also includes: if the type of the failed chip is the wire bonding type, the failed chip is unsealed again.
[0009] Optionally, identifying the position of each chip in the system-level packaging module includes: using X-ray irradiation to identify the position of each chip in the system-level packaging module.
[0010] The second aspect of the present application provides a failed chip analysis device, including: an identification module, used to identify the position of each chip in a system-level packaging module, and determine the target unsealing position of the corresponding chip according to the position and type of each chip; an acquisition module, used to obtain the internal circuit schematic of the system-level packaging module; a determination module, used to detect the electrical parameters of the chip at the target unsealing position, and determine the failed chip analysis results in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip.
[0011] Optionally, the determination module is further used to: determine reference parameters of each chip according to the internal circuit schematic; if the electrical parameters are consistent with the reference parameters, determine that the corresponding chip is not failed; if the electrical parameters are inconsistent with the reference parameters, determine that the corresponding chip is failed.
[0012] Optionally, the identification module is further used to: determine the allowable unsealing range of the corresponding chip according to the type of each chip; determine the target unsealing position of the corresponding chip according to the position of each chip and the allowable unsealing range of the corresponding chip.
[0013] Optionally, the chip types include wire bonding interconnection type and flip chip interconnection type, and also include: an unsealing module, which is used to unseal the failed chip again after determining the analysis results of the failed chip in the system-level packaging module based on the internal circuit schematic and the electrical parameters of each chip, if the type of the failed chip is a wire bonding type.
[0014] Optionally, the identification module is further used to: identify the position of each chip in the system-level packaging module by using X-ray irradiation.
[0015] A third aspect of the present application provides a system-level packaging module for analyzing failed chips based on the failed chip analysis method of the above embodiment.
[0016] The fourth aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to perform a failed chip analysis method for a system-level packaging module as in the above-mentioned embodiment.
[0017] The fifth aspect of the present application provides a computer-readable storage medium having a computer program or instructions stored thereon, and the computer program or instructions are executed by a processor to perform a failed chip analysis method for a system-level packaging module as in the above-mentioned embodiment.
[0018] The sixth aspect of the present application provides a computer program product, including a computer program or instructions. When the computer program or instructions are executed, the method for analyzing failed chips of the system-level packaging module of the above embodiment is implemented.
[0019] Therefore, this application has at least the following beneficial effects:
[0020] The embodiment of the present application can determine the corresponding target unsealing position according to the type of each chip and the position in the system-level packaging module, ensure that different unsealing positions are determined for different types of chips to prevent damage to the chip, and detect the electrical parameters of the chip at the target unsealing position, and then determine the analysis results of the failed chip in the system-level packaging module according to the electrical parameters and the internal circuit schematic, ensure that the analysis method can cover all chips, and improve the accuracy of chip failure analysis. Therefore, the technical problem of poor accuracy of existing failed chip analysis is solved.
[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0023] Figure 1 A flowchart of a failed chip analysis method provided according to an embodiment of the present application;
[0024] Figure 2 This is an example diagram of a failed chip analysis device provided according to an embodiment of the present application;
[0025] Figure 3 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0026] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0027] The following describes the failed chip analysis method and device of the system-level packaging module of the embodiment of the present application with reference to the accompanying drawings. In view of the existing failed chip analysis method in the system-level packaging module mentioned in the above background technology, which is mainly implemented by laser unsealing and physical cutting, but may cause physical damage to the leads and circuit connections, resulting in poor accuracy and reliability of the analysis, the present application provides a failed chip analysis method, in which the corresponding target unsealing position can be determined according to the type of each chip and the position in the system-level packaging module, ensuring that different unsealing positions are determined for different types of chips to prevent damage to the chip, and detecting the electrical parameters of the chip at the target unsealing position, and then determining the failed chip analysis results in the system-level packaging module based on the electrical parameters, ensuring that the analysis method can cover all chips and improve the comprehensiveness and accuracy of chip failure analysis. As a result, the existing problems such as poor accuracy of failed chip analysis are solved.
[0028] Specifically, Figure 1 A flowchart of a method for analyzing failed chips in a system-level packaging module provided in an embodiment of the present application.
[0029] like Figure 1 As shown, the failed chip analysis method includes the following steps:
[0030] In step S101 , the position of each chip in the system-in-package module is identified, and a target unsealing position of the corresponding chip is determined according to the position and type of each chip.
[0031] Among them, the types of chips include wire bonding interconnection type and flip chip interconnection type.
[0032] It can be understood that the embodiments of the present application can identify the position of each chip in the system-level packaging module, and since different types of chips have different unsealing positions, the target unsealing position of the corresponding chip can be determined according to the position and type of each chip.
[0033] For example, a wire-bonded chip can be unsealed at the lead position, and a flip-chip chip can be opened on the back of the chip using a laser unsealing machine to expose the back of the chip (silicon substrate).
[0034] In an embodiment of the present application, identifying the position of each chip in the system-level packaging module includes: using X-ray irradiation to identify the position of each chip in the system-level packaging module.
[0035] It can be understood that the embodiments of the present application can identify the position of each chip in the system-level packaging module through X-ray irradiation. The principle is as follows: the chip has a high absorption rate for X-rays, which will form an obvious shadow in the X-ray image, and the shadows produced for different types of chips are different. For example, the leads of wire-bonded chips are usually in the shape of thin lines, and the solder balls or solder joints of flip-chip chips are usually in the shape of circles or dots. Therefore, the position of each chip in the system-level packaging module can be identified.
[0036] In an embodiment of the present application, the target unsealing position of the corresponding chip is determined according to the position and type of each chip, including: determining the allowable unsealing range of the corresponding chip according to the type of each chip; determining the target unsealing position of the corresponding chip according to the position of each chip and the allowable unsealing range of the corresponding chip.
[0037] It is understandable that different types of chips have corresponding allowable unsealing ranges different, so the embodiment of the present application can determine the target unsealing position of the corresponding chip according to the position of each chip and the allowable unsealing range of the corresponding chip.
[0038] For example, the allowable unsealing range of a wire-bonded chip may be the area of the leads, and the allowable unsealing range of a flip-chip solder core may be the entire back side of the chip.
[0039] Specifically, for wire-bonded chips, a laser sealer can be used to make holes at the lead position until the top of the arc is exposed. For flip-chip chips, a laser sealer can be used to make holes directly at the chip area to expose the back of the chip (silicon substrate).
[0040] In step S102, an internal circuit schematic diagram of the system-in-package module is obtained.
[0041] It is understandable that the embodiments of the present application can obtain the internal circuit schematic of the system-level packaging module and determine the connection relationship between each chip and pin to facilitate the subsequent analysis of the failed chip.
[0042] In step S103, electrical parameters of the chip are detected at the target unsealing position, and analysis results of failed chips in the system-level packaging module are determined according to the electrical parameters.
[0043] Among them, electrical parameters may include voltage, current, resistance, etc.
[0044] It is understandable that the embodiments of the present application can detect the electrical parameters of the chip at the target unsealing position, and then determine the analysis results of the failed chip in the system-level packaging module based on the electrical parameters to determine the failed chip.
[0045] In an embodiment of the present application, the failed chip is located according to the internal circuit schematic and the electrical parameters of each chip, including: determining the reference parameters of each chip according to the internal circuit schematic; if the electrical parameters are consistent with the reference parameters, determining that the corresponding chip is not failed; if the electrical parameters are inconsistent with the reference parameters, determining that the corresponding chip is failed.
[0046] The reference parameters are electrical parameters of the chip when it is normal.
[0047] It can be understood that the embodiment of the present application can determine the reference parameters of each chip based on the internal circuit schematic. If the measured electrical parameters are inconsistent with the reference parameters, the corresponding chip is determined to be failed. Otherwise, if they are consistent, the corresponding chip is determined to be not failed.
[0048] In an embodiment of the present application, after determining the chip analysis results in the system-level packaging module based on the internal circuit schematic and the electrical parameters of each chip, it also includes: if the type of the failed chip is a wire bonding type, the failed chip is unsealed again.
[0049] It can be understood that after determining the analysis results of the failed chip in the system-level packaging module based on the electrical parameters and the internal circuit schematic, the present application can unseal the chip again when it is determined that the type of the failed chip is a wire bonding type. For example, it can be unsealed by a chemical unsealing method to more thoroughly remove the packaging material, expose the internal structure of the chip, and facilitate more detailed observation of the physical state inside the chip and determination of the failure point.
[0050] It should be noted that although the laser opening method can quickly expose the leads, it may cause certain physical damage to the leads. The chemical opening method is relatively mild and can further expose the internal structure of the chip without damaging the leads and circuit connections. Therefore, laser opening is used for preliminary opening, and then the chemical opening method is used for secondary opening.
[0051] In summary, the failed chip method of the embodiment of the present application first marks the position of the wire-bonded chip and the flip-chip chip by Xray irradiation. The wire-bonded chip can be opened at the lead position using a laser opener until the top of the arc is exposed. The flip-chip chip can be opened directly in the chip range using a laser opener to expose the back of the chip (silicon substrate). In this way, the electrical connection can be completed through the external pins of the system-level package and the leads of the wire-bonded chip, and then the electrical failure location can be completed in combination with the internal circuit schematic diagram of the system-level package as a whole to confirm the failed chip. If the failed chip is a flip-chip chip, the flip-chip chip can be located from the back on the OBIRCH / EMMI device. If the failed chip is a wire-bonded chip, the chemical unsealing method is continued to be used to unseal each chip, and attention is paid to protecting the circuit connection of the leads and substrate. After unsealing, the wire-bonded chip is located from the front on the OBIRCH / EMMI device.
[0052] According to the failed chip analysis method of the system-level packaging module proposed in the embodiment of the present application, the corresponding target unsealing position can be determined according to the type of each chip and the position in the system-level packaging module, ensuring that different unsealing positions are determined for different types of chips to prevent damage to the chip, and the electrical parameters of the chip are detected at the target unsealing position. Then, the failed chip analysis results in the system-level packaging module are determined based on the electrical parameters, ensuring that the analysis method can cover all chips and improve the comprehensiveness, accuracy and reliability of chip failure analysis.
[0053] Next, a failed chip analysis device of a system-in-package module according to an embodiment of the present application will be described with reference to the accompanying drawings.
[0054] Figure 2 It is a block diagram of a failed chip analysis device of a system-level packaging module according to an embodiment of the present application.
[0055] like Figure 2 As shown, the failed chip analysis device 10 of the system-level packaging module includes: an identification module 100 , an acquisition module 200 and a determination module 300 .
[0056] Among them, the identification module 100 is used to identify the position of each chip in the system-level packaging module, and determine the target unsealing position of the corresponding chip according to the position and type of each chip; the acquisition module 200 is used to obtain the internal circuit schematic of the system-level packaging module; the determination module 300 is used to detect the electrical parameters of the chip at the target unsealing position, and determine the analysis results of the failed chips in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip.
[0057] In an embodiment of the present application, the determination module 300 is further used to: determine the reference parameters of each chip according to the internal circuit schematic; if the electrical parameters are consistent with the reference parameters, it is determined that the corresponding chip is not failed; if the electrical parameters are inconsistent with the reference parameters, it is determined that the corresponding chip is failed.
[0058] In the embodiment of the present application, the identification module 100 is further used to: determine the allowable unsealing range of the corresponding chip according to the type of each chip; determine the target unsealing position of the corresponding chip according to the position of each chip and the allowable unsealing range of the corresponding chip.
[0059] In the embodiment of the present application, the types of chips include wire bonding interconnection type and flip chip interconnection type. The device 10 of the embodiment of the present application also includes: an unsealing module, which is used to unseal the failed chip again after determining the analysis results of the failed chip in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip.
[0060] In the embodiment of the present application, the identification module 100 is further used to: identify the position of each chip in the system-level packaging module by using X-ray irradiation.
[0061] It should be noted that the above explanation of the embodiment of the method for analyzing a failed chip in a system-level packaging module is also applicable to the device for analyzing a failed chip in a system-level packaging module of this embodiment, and will not be repeated here.
[0062] According to the failed chip analysis device of the system-level packaging module proposed in the embodiment of the present application, the corresponding target unsealing position can be determined according to the type of each chip and the position in the system-level packaging module, ensuring that different unsealing positions are determined for different types of chips to prevent damage to the chip, and the electrical parameters of the chip are detected at the target unsealing position. Then, the failed chip analysis results in the system-level packaging module are determined based on the electrical parameters, ensuring that the analysis method can cover all chips and improve the comprehensiveness, accuracy and reliability of chip failure analysis.
[0063] The embodiment of the present application also provides a system-level packaging module for analyzing failed chips based on the above-mentioned valid chip analysis method.
[0064] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:
[0065] A memory 301 , a processor 302 , and a computer program stored in the memory 301 and executable on the processor 302 .
[0066] When the processor 302 executes the program, the failed chip analysis method of the system-in-package module provided in the above embodiment is implemented.
[0067] Furthermore, the electronic device further comprises:
[0068] The communication interface 303 is used for communication between the memory 301 and the processor 302 .
[0069] The memory 301 is used to store computer programs that can be run on the processor 302 .
[0070] The memory 301 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.
[0071] If the memory 301, the processor 302 and the communication interface 303 are implemented independently, the communication interface 303, the memory 301 and the processor 302 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.
[0072] Optionally, in a specific implementation, if the memory 301, the processor 302 and the communication interface 303 are integrated on a chip, the memory 301, the processor 302 and the communication interface 303 can communicate with each other through an internal interface.
[0073] The processor 302 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.
[0074] An embodiment of the present application also provides a computer-readable storage medium having a computer program or instruction stored thereon. When the computer program or instruction is executed by a processor, the method for analyzing failed chips of the system-level packaging module as described above is implemented.
[0075] An embodiment of the present application also provides a computer program product, including a computer program or instructions, which, when executed, implements the above-mentioned method for analyzing failed chips in a system-level packaging module.
[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0077] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0078] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0079] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one or a combination of multiple of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
[0080] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.
Claims
1. A method for analyzing failed chips in a system-level packaging module, characterized in that: The following steps are involved: Identify the position of each chip in the system-level packaging module, and determine the target unsealing position of the corresponding chip according to the position and type of each chip; Obtaining an internal circuit schematic diagram of the system-in-package module; The electrical parameters of the chip are detected at the target unsealing position, and the analysis results of the failed chips in the system-level packaging module are determined according to the internal circuit schematic and the electrical parameters of each chip.
2. The method for analyzing failed chips according to claim 1, characterized in that: The locating the failed chip according to the internal circuit schematic and the electrical parameters of each chip includes: Determining reference parameters of each chip according to the internal circuit schematic; If the electrical parameter is consistent with the reference parameter, it is determined that the corresponding chip is not failed; If the electrical parameter is inconsistent with the reference parameter, it is determined that the corresponding chip fails.
3. The method for analyzing failed chips according to claim 1, characterized in that: The step of determining a target unsealing position of each chip according to the position and type of each chip includes: Determining the allowable unsealing range of the corresponding chip according to the type of each chip; The target unsealing position of the corresponding chip is determined according to the position of each chip and the allowable unsealing range of the corresponding chip.
4. The method for analyzing failed chips according to claim 3, characterized in that: The types of the chips include wire bonding type and flip chip type. After determining the analysis results of the failed chips in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip, the method further includes: If the type of the failed chip is a wire bonding type, the failed chip is unsealed again.
5. The method for analyzing failed chips according to claim 1, characterized in that: The identifying the position of each chip in the system-level package module includes: X-ray irradiation is used to identify the position of each chip in the system-level packaging module.
6. A failed chip analysis device for a system-level packaging module, characterized in that: include: An identification module, used to identify the position of each chip in the system-level packaging module, and determine the target unsealing position of the corresponding chip according to the position and type of each chip; An acquisition module, used to acquire an internal circuit schematic diagram of the system-level packaging module; A determination module is used to detect the electrical parameters of the chip at the target unsealing position, and determine the analysis results of the failed chips in the system-level packaging module according to the internal circuit schematic and the electrical parameters of each chip.
7. A system-level packaging module, characterized in that: The system-level packaging module analyzes a failed chip based on the failed chip analysis method according to any one of claims 1 to 5.
8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for analyzing failed chips of a system-level packaging module as described in any one of claims 1 to 5.
9. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: The computer program or instruction is executed by a processor to implement the failed chip analysis method of the system-level packaging module as described in any one of claims 1-5.
10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed, the method for analyzing failed chips of the system-level packaging module as described in any one of claims 1 to 5 is implemented.