Multifunctional test module and method for packaged chip

Abstract

The invention provides a multifunctional test module and method for a packaged chip, and relates to the technical field of integrated circuits. The multifunctional test module for the packaged chip comprises a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group and an island test pin group which are respectively and electrically connected with the controller and are arranged at intervals; the controller can receive a test instruction from the terminal device from the communication port and respond to the test instruction. According to the invention, at least two of a test item for the connection relationship of the internal circuit of the packaged chip, a test item for the communication capability of the packaged chip, a test item for the output current of the packaged chip, and an island test item for the packaged chip can be automatically executed at one time, and the packaged chip does not need to be continuously mounted and dismounted. The time cost and the labor cost are saved, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multifunctional testing module and method for packaged chips. Background Art

[0002] At present, some packaged chips (such as driver chips of camera modules) need to be tested for various functions before leaving the factory, so that improvements can be made when defects exist in the packaged chips to ensure the pass rate of the packaged chips leaving the factory.

[0003] In some scenarios, the method of testing packaged chips is as follows: the staff places the packaged chip on test machine A and connects the packaged chip to test equipment A to complete the test of function A of the packaged chip; next, the staff disconnects the packaged chip from test equipment A and removes the packaged chip from the test machine, and the staff places the packaged chip on test machine B and connects the packaged chip to test equipment B to complete the test of function B of the packaged chip, and so on, until all functions of the packaged chip are tested. It can be understood that the above process requires the continuous installation and removal of packaged chips, which is particularly cumbersome, resulting in high time and labor costs, and extremely low efficiency. Summary of the invention

[0004] The present application provides a multifunctional testing module and method for packaged chips, which are used to solve the problem in the prior art that when multifunctional testing of packaged chips is required, the time and labor costs are high and the efficiency is extremely low.

[0005] In a first aspect, the present application provides a multifunctional test module for a packaged chip, comprising a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller and spaced apart;

[0006] Among them, the first I2C test pin group is used to electrically connect to the second I2C test pin group of the packaged chip to be tested, the first current test pin group is used to electrically connect to the second current test pin group of the packaged chip to be tested, and the island test pin group is used to electrically connect to the island pin group of the packaged chip to be tested;

[0007] The controller is used to receive a test instruction from the terminal device through the communication port, and complete at least two of the following test items in response to the test instruction:

[0008] Execute test items of connection relationship of internal circuits of the packaged chip based on the first I2C test pin group and the second I2C test pin group, the first current test pin group and the second current test pin group respectively;

[0009] Based on the first I2C test pin group and the second I2C test pin group, executing a test item on the communication capability of the packaged chip;

[0010] Based on the first current test pin group and the second current test pin group, executing a test item on the output current of the packaged chip;

[0011] Based on the island test pin group and the island pin group, an island test item for the packaged chip is performed.

[0012] In a possible implementation, the first I2C test pin group includes: a first serial data interface for electrically connecting to a second serial data interface of a second I2C test pin group of the packaged chip; and a first serial clock interface for electrically connecting to a second serial data interface of the second I2C test pin group of the packaged chip;

[0013] The controller is specifically used to control the first serial data interface to input a first test current lower than a set current threshold to the second serial data interface, and make the first test current flow through the first internal circuit of the packaged chip and then output from the second serial clock interface to the first serial clock interface; when it is detected that the first voltage of the first serial data interface is equal to the second voltage of the first serial clock interface, the test result that the packaged chip is in a short-circuit state is output; or when it is detected that the second voltage is zero, the test result that the first internal circuit of the packaged chip is in an open-circuit state is output, so as to execute the test items on the connection relationship of the internal circuit of the packaged chip.

[0014] In a possible implementation, the first current test pin group includes a first current test positive electrode interface for electrically connecting to a second current test positive electrode interface of the packaged chip; a first current test negative electrode interface for electrically connecting to a second current test negative electrode interface of the packaged chip,

[0015] The controller is specifically used to control the first current test positive electrode interface to input a first test current lower than a set current threshold to the second current test positive electrode interface, and make the first test current flow through the first internal circuit of the packaged chip and then output from the second current test negative electrode interface to the first current test negative electrode interface; when it is detected that the first voltage of the first current test positive electrode interface is equal to the second voltage of the first current test negative electrode interface, the test result that the packaged chip is in a short-circuit state is output; or when it is detected that the second voltage is zero, the test result that the first internal circuit of the packaged chip is in an open-circuit state is output, so as to execute the test items on the connection relationship of the internal circuit of the packaged chip.

[0016] In a possible implementation, the first current test pin group includes a first current test positive electrode interface, which is used to be electrically connected to the second current test positive electrode interface of the packaged chip; a first current test negative electrode interface, which is used to be electrically connected to the second current test negative electrode interface of the packaged chip, and a resistor with a target resistance value is connected in series between the output end of the first current test negative electrode interface and the input end of the first current test positive electrode interface;

[0017] The controller is specifically used to instruct the first current test positive electrode interface to output a target current of a target value to the second current test positive electrode interface, so that the actual current output by the first current test positive electrode interface to the second current test positive electrode interface passes through the second internal circuit of the packaged chip, and then returns to the first current test positive electrode interface through the second current test negative electrode interface, the first current test negative electrode interface, and the resistor with the target resistance value; and detect the voltage difference across the resistor with the target resistance value, and determine the actual value of the actual current based on the voltage difference and the target resistance value of the resistor; based on the difference between the actual value of the actual current and the target value of the target current, output the test result of the current of the packaged chip to execute the test item of the output current of the packaged chip.

[0018] In one possible implementation, the controller is specifically used to output a test result indicating that the current of the packaged chip is abnormal when it is detected that the difference between the actual value of the actual current and the target value of the target current is greater than a set difference threshold; and to output a test result indicating that the current of the packaged chip is normal when it is detected that the difference between the actual value of the actual current and the target value of the target current is less than or equal to the set difference threshold.

[0019] In one possible implementation, the controller is also used to send a first request to the second I2C test pin group of the packaged chip based on the first I2C test pin group, where the first request is used to indicate the device identification of the requested packaged chip; if the controller receives the device identification from the second I2C test pin group based on the first I2C test pin group, the controller outputs a test result indicating that the communication capability of the packaged chip is normal; if the controller does not receive the device identification from the second I2C test pin group, the controller outputs a test result indicating that the communication capability of the packaged chip is abnormal, so as to execute the test item for the communication capability of the packaged chip.

[0020] In one possible implementation, the controller is also used to identify whether the received device identification is consistent with a preset device identification when receiving a device identification from a second I2C test pin group; if they are consistent, output a correct test result of the connected packaged chip; if they are inconsistent, output an incorrect test result of the connected packaged chip.

[0021] In a possible implementation, the island test pin group includes a voltage output pin for electrically connecting to a first island pin of the island pin group of the packaged chip; and a voltage acquisition pin for electrically connecting to a second island pin of the island pin group of the packaged chip;

[0022] The controller is specifically used to output a third voltage to the first island pin based on the voltage output pin, and to collect a fourth voltage of the second island pin based on the voltage collection pin, and when the fourth voltage is equal to the third voltage, output a test result of a short circuit of the island test pin group to execute the island test item for the packaged chip.

[0023] In a possible implementation manner, the controller is further configured to send the test results of at least two completed test items to the terminal device for display based on the communication port.

[0024] In a second aspect, the present application further provides a multifunctional testing method for a packaged chip, which is applied to a multifunctional testing module for a packaged chip, wherein the multifunctional testing module for the packaged chip includes a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller and spaced apart; wherein the first I2C test pin group is used to electrically connect the second I2C test pin group of the packaged chip to be tested, the first current test pin group is used to electrically connect the second current test pin group of the packaged chip to be tested, and the island test pin group is used to electrically connect the island pin group of the packaged chip to be tested, and the method includes:

[0025] The controller receives a test instruction from the terminal device through the communication port, and completes at least two of the following test items in response to the test instruction:

[0026] Execute test items of connection relationship of internal circuits of the packaged chip based on the first I2C test pin group and the second I2C test pin group, the first current test pin group and the second current test pin group respectively;

[0027] Based on the first I2C test pin group and the second I2C test pin group, executing a test item on the communication capability of the packaged chip;

[0028] Based on the first current test pin group and the second current test pin, executing a test item on the output current of the packaged chip;

[0029] An island test item for the packaged chip is performed based on the island test pin group, a resistor with a target resistance value, and the island pin group.

[0030] The present application provides a multifunctional test module and method for a packaged chip, wherein the multifunctional test module for the packaged chip comprises a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller and spaced apart; and the first I2C test pin group is used to electrically connect to a second I2C test pin group of a packaged chip to be tested, the first current test pin group is used to electrically connect to a second current test pin group of a packaged chip to be tested, and the island test pin group is used to electrically connect to an island pin group of a packaged chip to be tested;

[0031] Furthermore, the controller can receive test instructions from the terminal device from the communication port, and in response to the test instructions, can automatically execute at least two of the test items of the connection relationship of the internal circuit of the packaged chip, the test items of the communication capability of the packaged chip, the test items of the output current of the packaged chip, and the island test items of the packaged chip at one time, without the need to constantly install and remove the packaged chip, thereby saving time and labor costs and improving testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0033] Figure 1 A circuit block diagram of a multifunctional testing module for packaged chips provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the interaction between the multifunctional test module for the packaged chip provided in the embodiment of the present application and the terminal device, the IO expansion card, and the PLC;

[0035] Figure 3 A flowchart of a multifunctional testing method for packaged chips provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0037] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0038] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0039] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0040] See also Figure 1 The embodiment of the present application provides a multifunctional test module for packaged chips, including a controller 102, a communication port 104, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller 102 and spaced apart. The multifunctional test module for packaged chips provided by the embodiment of the present application may include a box body 101, the controller 102 is located in the box body 101, and the communication port 104 and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller 102 and spaced apart, are located on the side of the box body 101 so as to lead out wires for electrical connection.

[0041] like Figure 2As shown, the first I2C test pin group is used to electrically connect the second I2C test pin group of the packaged chip 103 to be tested, the first current test pin group is used to electrically connect the second current test pin group of the packaged chip 103 to be tested, and the island test pin group is used to electrically connect the island pin group of the packaged chip 103 to be tested. The communication port 104 can be but is not limited to a USB interface (such as USB3.0), and the communication port 104 is used to connect to the communication interface (such as USB interface) of the terminal device 105, so as to interact with the terminal device 105. It should be noted that the "I2C" in the first I2C test pin group and the second I2C test pin group in the embodiment of the present application can be understood as an integrated circuit bus (Inter-Integrated Circuit, I2C), the first I2C test pin group can also be referred to as a "first integrated circuit bus test pin group", and the second I2C test pin group can also be referred to as a "second integrated circuit bus test pin group", which is not limited here.

[0042] Specifically, the packaged chip 103 may be, but is not limited to, a packaged chip 103 for driving a motor of a camera, or a packaged chip 103 for driving a motor of an audio device, etc. The island pin group of the packaged chip 103 to be tested may be used as a pin group of a local device connected to the camera when connected to the camera.

[0043] The packaged chip 103 may be a co-packaging technology (COP) chip, wherein the co-packaging technology is a new type of packaging technology, which packages multiple chips in the same package, thereby realizing highly integrated and high-performance electronic devices.

[0044] The controller 102 is used to receive a test instruction from the terminal device 105 through the communication port 104 .

[0045] The terminal device 105 may be, but is not limited to, a PC device. For example, a staff member may place the packaged chip 103 at a designated position on the test machine and align it, such as Figure 2 As shown, at this time, the packaged chip 103 is electrically connected to the programmable logic controller PLC107 (Programmable Logic Controller, PLC). When PLC107 detects that the packaged chip 103 is connected, it can send a prompt message that the packaged chip 103 is normally connected to the terminal device 105 through the IO expansion card 106. The terminal device 105 can be installed with a test application. After the staff browses the prompt message that the packaged chip 103 is normally connected on the test interface, the terminal device 105 can respond to the user's triggering operation on the test control of the display interface of the test application, and send a test instruction to the controller 102 via the communication port 104.

[0046] Furthermore, the controller 102 is used to complete at least two of the following test items in response to the test instruction:

[0047] Test items of the connection relationship of the internal circuit of the packaged chip 103 are performed based on the first I2C test pin group and the second I2C test pin group, and the first current test pin group and the second current test pin group, respectively.

[0048] Based on the first I2C test pin group and the second I2C test pin group, a test item for the communication capability of the packaged chip 103 is performed.

[0049] Based on the first current test pin group and the second current test pin group, a test item of the output current of the packaged chip 103 is performed.

[0050] Based on the island test pin group and the island pin group, an island test item is performed on the packaged chip 103 .

[0051] Furthermore, the controller 102 can complete four of the following test items at one time in response to the test instruction, which greatly saves time and labor costs.

[0052] In summary, the embodiment of the present application provides a multifunctional test module for a packaged chip, since the multifunctional test module for the packaged chip includes a controller 102, a communication port 104, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller 102 and spaced apart; and the first I2C test pin group is used to electrically connect to the second I2C test pin group of the packaged chip 103 to be tested, the first current test pin group is used to electrically connect to the second current test pin group of the packaged chip 103 to be tested, and the island test pin group is used to electrically connect to the island pin group of the packaged chip 103 to be tested;

[0053] Furthermore, the controller 102 can receive a test instruction from the terminal device 105 from the communication port 104, and in response to the test instruction, can automatically execute at least two of the test items of the connection relationship of the internal circuit of the packaged chip 103, the test item of the communication capability of the packaged chip 103, the test item of the output current of the packaged chip 103, and the island test item of the packaged chip 103 at one time, without the need to constantly install and remove the packaged chip 103, thereby saving time and labor costs and improving testing efficiency.

[0054] The following describes in detail how the controller 102 executes each of the above test items.

[0055] In some embodiments, method 1 for executing a test item on the connection relationship of the internal circuit of the packaged chip 103: the first I2C test pin group includes: a first serial data interface SCL1, used to electrically connect to the second serial data interface SCL2 of the second I2C test pin group of the packaged chip 103; and a first serial clock interface SDA1, used to electrically connect to the second serial data interface SCL2 of the second I2C test pin group of the packaged chip 103.

[0056] The controller 102 is specifically used to control the first serial data interface SCL1 to input a first test current lower than a set current threshold to the second serial data interface SCL2, and make the first test current flow through the first internal circuit of the packaged chip 103 and then output from the second serial clock interface SDA2 to the first serial clock interface SDA1; when it is detected that the first voltage of the first serial data interface SCL1 is equal to the second voltage of the first serial clock interface SDA1, the test result that the packaged chip 103 is in a short-circuit state is output; or when it is detected that the second voltage is zero, the test result that the first internal circuit of the packaged chip 103 is in an open-circuit state is output, so as to execute the test items on the connection relationship of the internal circuit of the packaged chip 103.

[0057] In some embodiments, a method 2 for executing a test item of the connection relationship of the internal circuit of the packaged chip 103 is as follows: the first current test pin group includes a first current test positive electrode interface AF1+, which is used to be electrically connected to the second current test positive electrode interface AF2+ of the packaged chip 103; and a first current test negative electrode interface AF1-, which is used to be electrically connected to the second current test negative electrode interface AF2- of the packaged chip 103. The controller 102 is specifically used to control the first current test positive electrode interface AF1+ to input a first test current lower than a set current threshold to the second current test positive electrode interface AF2+, and to make the first test current flow through the second internal circuit of the packaged chip 103 and then output from the second current test negative electrode interface AF2- to the first current test negative electrode interface AF1-; when it is detected that the first voltage of the first current test positive electrode interface AF1+ is equal to the second voltage of the first current test negative electrode interface AF1-, the test result that the packaged chip 103 is in a short-circuit state is output; or when it is detected that the second voltage is zero, the test result that the second internal circuit of the packaged chip 103 is in an open-circuit state is output, so as to execute the test item of the connection relationship of the internal circuit of the packaged chip 103.

[0058] In some embodiments, a third method for executing a test item on the connection relationship of the internal circuit of the packaged chip 103 is as follows: the multifunctional test module for the packaged chip further includes a first power supply pin VCCAF (used to provide a preset voltage (such as 1.8V)), which is used to be electrically connected to the second power supply pin VCC of the packaged chip 103; and a first ground pin GND1, which is used to be connected to the second ground pin GND2 of the packaged chip 103. The controller 102 is specifically used to control the first power supply pin VCCAF to input a first test current lower than a set current threshold to the second power supply pin VCC, and to make the first test current flow through the third internal circuit of the packaged chip 103 and then output from the second ground pin GND2 to the first ground pin GND1; when it is detected that the first voltage of the first power supply pin VCCAF is equal to the second voltage of the first ground pin GND1, a test result that the packaged chip 103 is in a short-circuit state is output; or when it is detected that the second voltage is zero, a test result that the third internal circuit of the packaged chip 103 is in an open-circuit state is output, so as to execute the test item on the connection relationship of the internal circuit of the packaged chip 103.

[0059] It should be noted that the above-mentioned method 1 for executing the test items on the connection relationship of the internal circuit of the packaged chip 103, the method 2 for executing the test items on the connection relationship of the internal circuit of the packaged chip 103, and the method 3 for executing the test items on the connection relationship of the internal circuit of the packaged chip 103 may all be executed, or one or two of them may be selected for execution, and are not limited here.

[0060] In some embodiments, the first current test pin group includes a first current test positive electrode interface AF1+, which is used to be electrically connected to the second current test positive electrode interface AF2+ of the packaged chip 103; a first current test negative electrode interface AF1-, which is used to be electrically connected to the second current test negative electrode interface AF2- of the packaged chip 103, and a resistor R1 with a target resistance value (such as 10 ohms) is connected in series between the output end of the first current test negative electrode interface AF1- and the input end of the first current test positive electrode interface AF1+.

[0061] The controller 102 is specifically used to instruct the first current test positive electrode interface AF1+ to output a target current of a target value to the second current test positive electrode interface AF2+, so that the actual current output from the first current test positive electrode interface AF1+ to the second current test positive electrode interface AF2+ passes through the second internal circuit of the packaged chip 103, and then returns to the first current test positive electrode interface AF1+ through the second current test negative electrode interface AF2-, the first current test negative electrode interface AF1-, and the resistor R1 of the target resistance value; and detect the voltage difference across the resistor R1 of the target resistance value, and determine the actual value of the actual current based on the voltage difference and the target resistance value of the resistor R1; and output the test result of the current of the packaged chip 103 based on the difference between the actual value of the actual current and the target value of the target current, so as to execute the test item of the output current of the packaged chip 103.

[0062] Exemplarily, the controller 102 is specifically used to output a test result indicating that the current of the packaged chip 103 is abnormal when it is detected that the difference between the actual value of the actual current and the target value of the target current is greater than a set difference threshold; and to output a test result indicating that the current of the packaged chip 103 is normal when it is detected that the difference between the actual value of the actual current and the target value of the target current is less than or equal to the set difference threshold.

[0063] In some embodiments, the controller 102 is also used to send a first request to the second I2C test pin group of the packaged chip 103 based on the first I2C test pin group, and the first request is used to indicate the device identification of the packaged chip 103 being requested; if the controller 102 receives the device identification from the second I2C test pin group based on the first I2C test pin group, the test result indicating that the communication capability of the packaged chip 103 is normal is output; if the device identification from the second I2C test pin group is not received, the test result indicating that the communication capability of the packaged chip 103 is abnormal is output, so as to execute the test item for the communication capability of the packaged chip 103.

[0064] In some embodiments, the controller 102 is also used to identify whether the received device identification is consistent with the preset device identification when receiving the device identification from the second I2C test pin group; if consistent, output the correct test result of the connected packaged chip 103; if inconsistent, output the wrong test result of the connected packaged chip 103.

[0065] In some embodiments, the island test pin group includes a voltage output pin VDDA, which is used to electrically connect to the first island pin pin1 of the island pin group of the packaged chip 103; and a voltage acquisition pin ADC, which is used to electrically connect to the second island pin pin2 of the island pin group of the packaged chip 103.

[0066] The controller 102 is specifically used to output a third voltage (such as 1.8V) to the first island pin pin1 based on the voltage output pin VDDA, and to collect a fourth voltage of the second island pin pin2 based on the voltage collection pin ADC. When the fourth voltage is equal to the third voltage, the controller 102 outputs a test result of a short circuit of the island test pin group to execute the island test item for the packaged chip 103.

[0067] In some embodiments, the controller 102 is further configured to send the test results of at least two completed test items to the terminal device 105 for display based on the communication port 104. Furthermore, the staff can browse the test results of each test item on the display interface of the test application.

[0068] In addition, the embodiment of the present application also provides a multifunctional testing method for a packaged chip, which is applied to a multifunctional testing module for a packaged chip. Figure 1 As shown, the multifunctional test module for the packaged chip includes a controller 102, a communication port 104, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller 102 and spaced apart; wherein the first I2C test pin group is used to electrically connect to the second I2C test pin group of the packaged chip 103 to be tested, the first current test pin group is used to electrically connect to the second current test pin group of the packaged chip 103 to be tested, and the island test pin group is used to electrically connect to the island pin group of the packaged chip 103 to be tested.

[0069] It should be noted that the basic principle and technical effects of the multifunctional testing method for packaged chips provided in the embodiment of the present application are the same as those in the above embodiment. For the sake of brief description, for the parts not mentioned in the embodiment of the present application, reference can be made to the corresponding contents in the above embodiment. Specifically, the method provided in the embodiment of the present application also includes:

[0070] Step 1: The controller 102 receives a test instruction from the terminal device 105 through the communication port 104, and completes at least two of the following test items in response to the test instruction:

[0071] Based on the first I2C test pin group and the second I2C test pin group, the first current test pin group and the second current test pin group, respectively, executing test items on the connection relationship of the internal circuit of the packaged chip 103;

[0072] Based on the first I2C test pin group and the second I2C test pin group, executing a test item on the communication capability of the packaged chip 103;

[0073] Based on the first current test pin group and the second current test pin, executing a test item on the output current of the packaged chip 103;

[0074] Based on the island test pin group and the island pin group, an island test item is performed on the packaged chip 103 .

[0075] The controller 102 is also connected to a GPIO port and a third power supply pin (capable of providing a preset power supply voltage (eg, 1.8V)). Figure 3 As shown, the specific process of step 1 above can be:

[0076] S301 : the controller 102 receives a test instruction from the terminal device 105 .

[0077] S302 : the controller 102 enters a first test mode. In the first test mode, a test item on the connection relationship of the internal circuit of the packaged chip 103 may be executed.

[0078] Exemplarily, the first test mode may be entered by controlling the GPIO of the multi-function test module of the packaged chip to be pulled high.

[0079] S303: The controller 102 executes test items on the connection relationship of the internal circuit of the packaged chip 103 based on the first I2C test pin group and the second I2C test pin group, and the first current test pin group and the second current test pin group, respectively.

[0080] S304: The controller 102 switches from the first test mode back to the normal mode.

[0081] Exemplarily, the GPIO of the multi-function test module of the packaged chip may be controlled to be pulled low to switch from the first test mode back to the normal mode.

[0082] S305 : The controller 102 switches from the normal mode to the second test mode. In the second test mode, test items for the communication capability of the packaged chip 103 can be executed.

[0083] Exemplarily, the normal mode can be switched to the second test mode by controlling the power-on of the third power supply pin of the multi-function test module of the packaged chip.

[0084] S306 : The controller 102 executes a test item on the communication capability of the packaged chip 103 based on the first I2C test pin group and the second I2C test pin group.

[0085] S307 : Based on the first current test pin group and the second current test pin, execute a test item on the output current of the packaged chip 103 .

[0086] S308 : performing an island test item on the packaged chip 103 based on the island test pin group, the resistor R1 with the target resistance, and the island pin group.

[0087] It should be noted that there is no order of precedence among the above S302-S305, S306, S307, and S308, and they can be selected according to actual needs. The specific implementation methods of S306, S307, and S308 can refer to the above embodiments and will not be repeated here.

[0088] In the above description, the technical details such as the patterning of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0089] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multifunctional test module for packaged chips, characterized in that: It includes a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller and arranged at intervals; Wherein, the first I2C test pin group is used to electrically connect to the second I2C test pin group of the packaged chip to be tested, the first current test pin group is used to electrically connect to the second current test pin group of the packaged chip to be tested, and the island test pin group is used to electrically connect to the island pin group of the packaged chip to be tested; The controller is used to receive a test instruction from the terminal device through the communication port, and complete at least two of the following test items in response to the test instruction: Execute test items of connection relationship of internal circuits of the packaged chip based on the first I2C test pin group and the second I2C test pin group, the first current test pin group and the second current test pin group respectively; Based on the first I2C test pin group and the second I2C test pin group, executing a test item on the communication capability of the packaged chip; Based on the first current test pin group and the second current test pin group, executing a test item on the output current of the packaged chip; Based on the island test pin group and the island pin group, an island test item for the packaged chip is performed.

2. The module according to claim 1, characterized in that The first I2C test pin group includes: a first serial data interface for electrically connecting to a second serial data interface of a second I2C test pin group of the packaged chip; and a first serial clock interface for electrically connecting to a second serial data interface of a second I2C test pin group of the packaged chip; The controller is specifically used to control the first serial data interface to input a first test current lower than a set current threshold to the second serial data interface, and make the first test current flow through the first internal circuit of the packaged chip and then output from the second serial clock interface to the first serial clock interface; when it is detected that the first voltage of the first serial data interface is equal to the second voltage of the first serial clock interface, the test result that the packaged chip is in a short-circuit state is output; or when it is detected that the second voltage is zero, the test result that the first internal circuit of the packaged chip is in an open-circuit state is output, so as to execute the test items on the connection relationship of the internal circuit of the packaged chip.

3. The module according to claim 1, characterized in that The first current test pin group includes a first current test positive electrode interface, which is used to be electrically connected to the second current test positive electrode interface of the packaged chip; a first current test negative electrode interface, which is used to be electrically connected to the second current test negative electrode interface of the packaged chip, The controller is specifically used to control the first current test positive electrode interface to input a first test current lower than a set current threshold to the second current test positive electrode interface, and to make the first test current flow through the second internal circuit of the packaged chip and then output from the second current test negative electrode interface to the first current test negative electrode interface; when it is detected that the first voltage of the first current test positive electrode interface is equal to the second voltage of the first current test negative electrode interface, output the test result that the packaged chip is in a short-circuit state; Alternatively, when it is detected that the second voltage is zero, a test result indicating that the second internal circuit of the packaged chip is in an open circuit state is outputted to execute a test item on the connection relationship of the internal circuit of the packaged chip.

4. The module according to claim 1, characterized in that The first current test pin group includes a first current test positive electrode interface, which is used to be electrically connected to the second current test positive electrode interface of the packaged chip; a first current test negative electrode interface, which is used to be electrically connected to the second current test negative electrode interface of the packaged chip, and a resistor with a target resistance value is connected in series between the output end of the first current test negative electrode interface and the input end of the first current test positive electrode interface; The controller is specifically used to instruct the first current test positive electrode interface to output a target current of a target value to the second current test positive electrode interface, so that the actual current output by the first current test positive electrode interface to the second current test positive electrode interface passes through the second internal circuit of the packaged chip, and then returns to the first current test positive electrode interface through the second current test negative electrode interface, the first current test negative electrode interface, and the resistor of the target resistance value; and detect the voltage difference across the resistor of the target resistance value, and determine the actual value of the actual current according to the voltage difference and the target resistance value of the resistor; According to the difference between the actual value of the actual current and the target value of the target current, the test result of the current of the packaged chip is output to execute the test item of the output current of the packaged chip.

5. The module according to claim 4, characterized in that The controller is specifically configured to output a test result indicating that the current of the packaged chip is abnormal when it is detected that the difference between the actual value of the actual current and the target value of the target current is greater than a set difference threshold; When it is detected that the difference between the actual value of the actual current and the target value of the target current is less than or equal to the set difference threshold, a test result indicating that the current of the packaged chip is normal is output.

6. The module according to claim 1, characterized in that The controller is also used to send a first request to the second I2C test pin group of the packaged chip based on the first I2C test pin group, wherein the first request is used to indicate a request for a device identification of the packaged chip; if the controller receives a device identification from the second I2C test pin group based on the first I2C test pin group, the controller outputs a test result indicating that the communication capability of the packaged chip is normal; if the controller does not receive the device identification from the second I2C test pin group, the controller outputs a test result indicating that the communication capability of the packaged chip is abnormal, so as to execute a test item for the communication capability of the packaged chip.

7. The module according to claim 6, characterized in that The controller is further configured to, upon receiving a device identification from the second I2C test pin group, identify whether the received device identification is consistent with a preset device identification; if consistent, output a correct test result of the connected packaged chip; If they are inconsistent, the wrong test result of the connected packaged chip is output.

8. The module according to claim 1, characterized in that The island test pin group includes a voltage output pin for electrically connecting to a first island pin of the island pin group of the packaged chip; and a voltage acquisition pin for electrically connecting to a second island pin of the island pin group of the packaged chip; The controller is specifically used to output a third voltage to the first island pin based on the voltage output pin, and to collect a fourth voltage of the second island pin based on the voltage collection pin, and when the fourth voltage is equal to the third voltage, output a test result of a short circuit of the island test pin group to execute an island test item for the packaged chip.

9. The module according to any one of claims 1 to 8, characterized in that: The controller is also used to send the completed test results of at least two of the test items to the terminal device for display based on the communication port.

10. A multifunctional testing method for packaged chips, characterized in that: A multifunctional test module for a packaged chip, wherein the multifunctional test module for the packaged chip comprises a controller, a communication port, and at least two of a first I2C test pin group, a first current test pin group, and an island test pin group, which are electrically connected to the controller and spaced apart; wherein the first I2C test pin group is used to electrically connect to a second I2C test pin group of a packaged chip to be tested, the first current test pin group is used to electrically connect to a second current test pin group of the packaged chip to be tested, and the island test pin group is used to electrically connect to an island pin group of the packaged chip to be tested, and the method comprises: The controller receives a test instruction from the terminal device through the communication port, and completes at least two of the following test items in response to the test instruction: Execute test items of connection relationship of internal circuits of the packaged chip based on the first I2C test pin group and the second I2C test pin group, the first current test pin group and the second current test pin group respectively; Based on the first I2C test pin group and the second I2C test pin group, executing a test item on the communication capability of the packaged chip; Performing a test item on the output current of the packaged chip based on the first current test pin group and the second current test pin; Based on the island test pin group and the island pin group, an island test item for the packaged chip is performed.

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