Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel structures. The plurality of scanning lines and the plurality of data lines are arranged on the substrate. The pixel structure is arranged on the substrate and electrically connected with the scanning line and the data line. The pixel structure comprises an active element, a pixel electrode, a capacitor electrode, a coating layer, a first common electrode, a second common electrode, a first passivation layer and a second passivation layer. The active element is electrically connected with a scanning line, a data line and the pixel electrode. The capacitor electrode extends from the drain electrode and is electrically connected with the pixel electrode. The cladding layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode and is located between the cladding layer and the capacitor electrode. The second common electrode overlaps the pixel electrode and is located between the cladding layer and the pixel electrode. The first passivation layer is disposed between the capacitor electrode and the first common electrode. The second passivation layer is disposed between the second common electrode and the pixel electrode.

Description

Technical Field

[0001] The present invention relates to a display panel and a manufacturing method thereof, and in particular to a display panel with a storage capacitor and a manufacturing method thereof. Background Art

[0002] The pixel structure is the smallest driving unit used by the display panel to present images. In order to maintain the driving signal of the pixel structure at a certain level within a predetermined time interval, the pixel structure is mostly equipped with a storage capacitor. In order to achieve better display quality, the size of the pixel structure is constantly shrinking, which also compresses the layout space of the storage capacitor. Therefore, how to increase the storage capacitor in a limited space without affecting the operating electrical properties of other components is a technical problem that panel manufacturers need to overcome. Summary of the invention

[0003] The present invention is directed to a display panel, which has better display quality when driven at a low frequency.

[0004] The present invention is directed to a method for manufacturing a display panel, wherein the manufacturing process integration of a plurality of storage capacitors is relatively high.

[0005] According to an embodiment of the present invention, a display panel includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel structures. The plurality of scan lines and the plurality of data lines are arranged on the substrate and intersect with each other. The plurality of pixel structures are arranged on the substrate and electrically connect the scan lines and the data lines. The pixel structures each include an active element, a pixel electrode, a capacitor electrode, a coating layer, a first common electrode, a second common electrode, a first passivation layer and a second passivation layer. The active element has a gate, a source and a drain. The gate is electrically connected to one of the scan lines. The source is electrically connected to one of the data lines. The pixel electrode is electrically connected to the drain of the active element. The capacitor electrode extends from the drain and is electrically connected to the pixel electrode. The coating layer is arranged between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode and is located between the coating layer and the capacitor electrode. The second common electrode overlaps the pixel electrode and is located between the coating layer and the pixel electrode. The first passivation layer is arranged between the capacitor electrode and the first common electrode. The second passivation layer is arranged between the second common electrode and the pixel electrode.

[0006] In the display panel according to the embodiment of the present invention, the first common electrode is electrically coupled to the capacitor electrode and forms a first storage capacitor, and the second common electrode is electrically coupled to the pixel electrode and forms a second storage capacitor.

[0007] In the display panel according to the embodiment of the present invention, the overlapping area between the second common electrode and the pixel electrode is larger than the overlapping area between the first common electrode and the capacitor electrode.

[0008] In the display panel according to the embodiment of the present invention, the capacitance value of the second storage capacitor is greater than the capacitance value of the first storage capacitor.

[0009] In the display panel according to the embodiment of the present invention, each of the plurality of pixel structures further includes a third common electrode overlapping the capacitor electrode and located between the capacitor electrode and the substrate. The third common electrode is electrically coupled to the capacitor electrode to form a third storage capacitor.

[0010] In the display panel according to the embodiment of the present invention, the display panel has a reflective area, the pixel electrode is located in the reflective area, and the material of the pixel electrode includes metal.

[0011] In a display panel according to an embodiment of the present invention, the display panel has a reflective region and a transmissive region. The pixel electrode is located in the reflective region and the transmissive region, and the material of the pixel electrode includes a transparent conductive material. Each of the plurality of pixel structures further includes a reflective layer electrically connected to the pixel electrode. The reflective layer is located in the reflective region, the reflective layer overlaps and covers a portion of the pixel electrode, and a portion of the pixel electrode not covered by the reflective layer is located in the transmissive region.

[0012] According to an embodiment of the present invention, a method for manufacturing a display panel includes forming a metal layer on a substrate, forming a first passivation material layer on the metal layer, forming another metal layer on the first passivation material layer, forming a coating layer on the first passivation material layer and the other metal layer, forming a transparent conductive layer on the coating layer, forming a second passivation material layer on the transparent conductive layer, etching the first passivation material layer and the second passivation material layer to generate a first passivation layer and a second passivation layer that expose a portion of a capacitor electrode, and forming a pixel electrode on the second passivation layer. The metal layer includes a capacitor electrode. The other metal layer includes a first common electrode, and the first common electrode overlaps the capacitor electrode. The coating layer has an opening that overlaps the capacitor electrode. The transparent conductive layer includes a second common electrode. The second passivation material layer extends into the opening and covers the first passivation material layer. The pixel electrode extends into the opening of the coating layer to electrically connect the capacitor electrode, and the pixel electrode overlaps the second common electrode.

[0013] In the manufacturing method of the display panel according to the embodiment of the present invention, the metal layer is the second metal layer, and the other metal layer is the third metal layer. Before the step of forming the second metal layer, the method further includes forming a first metal layer on the substrate and forming an insulating layer on the first metal layer. The first metal layer includes a third common electrode. After the step of forming the second metal layer, the second metal layer is located on the insulating layer.

[0014] In the manufacturing method of the display panel according to an embodiment of the present invention, the material of the coating layer includes a photosensitive material, and the step of forming the coating layer includes forming a coating material layer on a first passivation layer and another metal layer and performing an exposure process and a development process on the coating material layer to remove a portion of the coating material layer to form an opening.

[0015] In the method for manufacturing a display panel according to an embodiment of the present invention, the steps of etching the first passivation material layer and the second passivation material layer are performed in the same lithography and etching process.

[0016] In the method for manufacturing a display panel according to an embodiment of the present invention, the method for manufacturing a display panel further includes forming a reflective layer on the pixel electrode. The reflective layer is electrically connected to the pixel electrode.

[0017] Based on the above, in a display panel and a manufacturing method thereof according to an embodiment of the present invention, a common electrode is provided between the capacitor electrode electrically connected to the active element and the coating layer, and another common electrode is provided between the pixel electrode electrically connected to the capacitor electrode and the coating layer. Since a common electrode is also provided on the side of the coating layer closer to the pixel electrode, in addition to shortening the distance between the pixel electrode and the common electrode, the overlapping range between the common electrode and the pixel electrode can also be larger, thereby increasing the storage capacitance of the pixel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic top view of a display panel according to a first embodiment of the present invention;

[0019] Figure 2 yes Figure 1 A cross-sectional schematic diagram of a display panel;

[0020] FIG. 3A to FIG. 3I yes Figure 2 A cross-sectional view of a process of manufacturing a display panel;

[0021] 4A to 4H yes Figure 1 A schematic top view of each film layer of a display panel;

[0022] FIG. 5A to FIG. 5C yes Figure 1 A schematic top view of a portion of a film layer of a display panel;

[0023] Figure 6 is a cross-sectional schematic diagram of a display panel according to a second embodiment of the present invention;

[0024] Figure 7 is a schematic top view of a display panel according to a third embodiment of the present invention;

[0025] Figure 8 yes Figure 7 A cross-sectional schematic diagram of a display panel;

[0026] FIG. 9A to FIG. 9I yes Figure 7 A schematic top view of each film layer of a display panel.

[0027] Description of Reference Numerals

[0028] 10, 10A, 20: display panel;

[0029] 101, 102: substrate;

[0030] 101S: Surface;

[0031] 110: insulation layer;

[0032] 121, 122, 123, 124: passivation layer;

[0033] 121M, 122M, 123M, 124M: passivation material layer;

[0034] 130, 130A: coating layer;

[0035] 130M: coating material layer;

[0036] C1, C2, C3: storage capacitors;

[0037] CE1, CE1-A: first common electrode;

[0038] CE1op: hollowing part;

[0039] CE2, CE2-A: second common electrode;

[0040] CE2op, OP: Opening;

[0041] CE3, CE3-A: third common electrode;

[0042] CEL: common electrode layer;

[0043] CPE, CPE-A: capacitive electrode;

[0044] DE: drain;

[0045] DL: data line;

[0046] DME: dummy electrode;

[0047] GE: gate;

[0048] GL: scan line;

[0049] LCL: Liquid crystal layer;

[0050] ML1, ML2, ML3, ML1-A, ML2-A, ML3-A: metal layer;

[0051] PE, PE-A: pixel electrodes;

[0052] PX, PX-A: pixel structure;

[0053] RA: reflex area;

[0054] RL: reflective layer;

[0055] SC: semiconductor pattern;

[0056] SE: source;

[0057] T: active element;

[0058] TA: penetration area;

[0059] TCL, TCL1, TCL2: transparent conductive layer;

[0060] TH, TH-A, TH-B: contact holes;

[0061] X, Y, Z: direction;

[0062] A-A', B-B', C-C': section lines. DETAILED DESCRIPTION

[0063] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0064] Figure 1 is a schematic top view of a display panel according to a first embodiment of the present invention. Figure 2 yes Figure 1 A schematic cross-sectional view of a display panel. FIG. 3A to FIG. 3I yes Figure 2 A cross-sectional view of a process for manufacturing a display panel. 4A to 4H yes Figure 1 A schematic top view of each film layer of a display panel. FIG. 5A to FIG. 5C yes Figure 1 A schematic top view of part of the film layer of a display panel.

[0065] Figure 2 correspond Figure 1 For the sake of clarity, Figure 1 Omitted Figure 2 The substrate 101, the substrate 102, the common electrode layer CEL and the liquid crystal layer LCL are shown.

[0066] Please refer to Figure 1 and Figure 2 The display panel 10 includes a substrate 101, a substrate 102 and a liquid crystal layer LCL. The liquid crystal layer LCL is disposed between the substrates 102. That is, the display panel 10 of this embodiment is a liquid crystal display panel, but is not limited thereto.

[0067] The display panel 10 further includes a plurality of scan lines GL, a plurality of data lines DL, and a plurality of pixel structures PX disposed on the substrate 101. The pixel structure PX is electrically connected to one scan line GL and one data line DL. Figure 1 Only one display unit of the display panel 10 is shown, and the display panel 10 may be composed of a plurality of such display units. For example, a plurality of data lines DL may be arranged along a direction X and each data line DL extends in a direction Y, a plurality of scan lines GL may be arranged along a direction Y and each scan line GL extends in a direction X, wherein the direction X may be perpendicular to the direction Y. A plurality of pixel structures PX may be arranged in a plurality of rows and a plurality of columns along the directions X and Y, respectively.

[0068] The pixel structure PX includes an active element T, a capacitor electrode CPE, a first common electrode CE1, a second common electrode CE2, a third common electrode CE3 and a pixel electrode PE. The active element T has a source SE, a drain DE, a gate GE and a semiconductor pattern SC. The source SE is electrically connected to a corresponding data line DL. The drain DE is electrically connected to the capacitor electrode CPE. The gate GE is electrically connected to a corresponding scan line GL. More specifically, the portion of the scan line GL extending from the corresponding pixel structure PX can be used as the gate GE of the active element T, and the portion of the data line DL extending from the corresponding pixel structure PX can be used as the source SE of the active element T. The capacitor electrode CPE extends from the drain DE and is electrically connected to the pixel electrode PE.

[0069] The first common electrode CE1 is disposed between the capacitor electrode CPE and the pixel electrode PE in the direction Z, and overlaps the capacitor electrode CPE and the pixel electrode PE along the direction Z. The second common electrode CE2 is disposed between the first common electrode CE1 and the pixel electrode PE in the direction Z, and overlaps the pixel electrode PE and the first common electrode CE1 along the direction Z. The third common electrode CE3 is disposed between the capacitor electrode CPE and the substrate 101 in the direction Z, and overlaps the capacitor electrode CPE along the direction Z. In the present embodiment, the pixel structure PX is disposed on the surface 101S of the substrate 101, and the direction Z is a direction perpendicular to the surface 101S of the substrate 101.

[0070] In this embodiment, the pixel structure PX may further include an insulating layer 110, a passivation layer 121, a passivation layer 122, a passivation layer 123, a passivation layer 124 and a capping layer 130. Figure 2As shown, the insulating layer 110 is arranged between the third common electrode CE3 and the capacitor electrode CPE in the direction Z. The passivation layer 121 (i.e., the first passivation layer) is arranged between the capacitor electrode CPE and the first common electrode CE1 in the direction Z. The passivation layer 122 is arranged between the covering layer 130 and the first common electrode CE1 in the direction Z. The passivation layer 123 is arranged between the covering layer 130 and the second common electrode CE2 in the direction Z. The passivation layer 124 (i.e., the second passivation layer) is arranged between the second common electrode CE2 and the pixel electrode PE in the direction Z. The covering layer 130 is arranged between the second common electrode CE2 and the first common electrode CE1. Specifically, as Figure 2 As shown, the third common electrode CE3, the insulating layer 110, the capacitor electrode CPE, the passivation layer 121, the first common electrode CE1, the passivation layer 122, the covering layer 130, the passivation layer 123, the second common electrode CE2, the passivation layer 124 and the pixel electrode PE are arranged in sequence along the direction Z.

[0071] For example, the first common electrode CE1 can be electrically coupled to the capacitor electrode CPE and form a first storage capacitor C1 (i.e., the first storage capacitor C1 is formed by the first common electrode CE1, the capacitor electrode CPE and the insulating film layer located between the above two electrodes). The second common electrode CE2 can be electrically coupled to the pixel electrode PE and form a second storage capacitor C2 (i.e., the second storage capacitor C2 is formed by the pixel electrode PE, the second common electrode CE2 and the insulating film layer located between the above two electrodes). The third common electrode CE3 can be electrically coupled to the capacitor electrode CPE and form a third storage capacitor C3 (i.e., the third storage capacitor C3 is formed by the third common electrode CE3, the capacitor electrode CPE and the insulating film layer located between the above two electrodes).

[0072] More specifically, the storage capacitor of the pixel structure PX may be formed by connecting a first storage capacitor C1, a second storage capacitor C2, and a third storage capacitor C3 in parallel. In the present embodiment, the first storage capacitor C1 is formed by the first common electrode CE1, the capacitor electrode CPE, and a passivation layer 121 between the first common electrode CE1 and the capacitor electrode CPE, the second storage capacitor C2 is formed by the pixel electrode PE, the second common electrode CE2, and a passivation layer 124 between the pixel electrode PE and the second common electrode CE2, and the third storage capacitor C3 is formed by the third common electrode CE3, the capacitor electrode CPE, and an insulating layer 110 between the third common electrode CE3 and the capacitor electrode CPE.

[0073] First, it is explained that, in addition to the first common electrode CE1 provided between the coating layer 130 and the capacitor electrode CPE, a second common electrode CE2 is also provided between the coating layer 130 and the pixel electrode PE. Accordingly, in addition to shortening the distance between the pixel electrode PE and the common electrode, the overlapping area between the common electrode and the pixel electrode PE can also be larger, so the capacitance value of the second storage capacitor C2 formed by the pixel electrode PE and the second common electrode CE2 can be larger. For example, in the present embodiment, the capacitance value of the second storage capacitor C2 formed by the pixel electrode PE and the second common electrode CE2 can be greater than the capacitance value of the first storage capacitor C1 formed by the capacitor electrode CPE and the first common electrode CE1 and the capacitance value of the third storage capacitor C3 formed by the capacitor electrode CPE and the third common electrode CE3. In other words, by providing another common electrode (e.g., the second common electrode CE2) on the side of the coating layer 130 close to the pixel electrode PE, the overall storage capacitance of the pixel structure PX can be greatly increased. For example, in a comparative embodiment of a pixel structure in which the second common electrode CE2 and the passivation layer 124 are not provided, the storage capacitance of the pixel structure may be 199.23 femtofarads (fF), while the storage capacitance of the pixel structure PX of the present embodiment may be 847.45 femtofarads. Therefore, compared with the comparative embodiment, the storage capacitance of the pixel structure PX of the present embodiment may be increased by more than four times.

[0074] On the other hand, in the present embodiment, the second common electrode CE2 overlaps the active device T in the direction Z. In order to reduce the coupling effect between the active device T and the second common electrode CE2, so as to prevent the potential of the second common electrode CE2 from causing the active device T to be turned on and generate leakage, a dummy electrode DME may be further provided between the active device T and the second common electrode CE2. The dummy electrode DME overlaps the active device T along the direction Z. For example, the dummy electrode DME may have a floating potential, but is not limited thereto.

[0075] In addition, the display panel 10 may further include a common electrode layer CEL, which is disposed on the surface of the substrate 102 facing the liquid crystal layer LCL, that is, the common electrode layer CEL is located between the substrate 102 and the liquid crystal layer LCL. The material of the common electrode layer CEL may include a transparent conductive material, and the transparent conductive material may, for example, include a metal oxide (for example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above), but is not limited thereto. For example, the electric field formed between the pixel electrodes PE of each of the plurality of pixel structures PX and the common electrode layer CEL may control the direction of the liquid crystal molecules in the liquid crystal layer LCL to display the corresponding picture. In the present embodiment, the common electrode layer CEL, the first common electrode CE1, the second common electrode CE2 and the third common electrode CE3 may receive a common potential (Common Voltage), but is not limited thereto.

[0076] The following is an exemplary description of a method for manufacturing the display panel 10 .

[0077] Please refer to Figure 3A and FIG. 4A to FIG. 4C First, a first metal layer ML1 is formed on the substrate 101 . Figure 4A FIG. 1 is a schematic top view of the first metal layer ML1. In this embodiment, the first metal layer ML1 includes a scanning line GL (eg Figure 1 ), the gate GE and the third common electrode CE3. The material of the substrate 101 is, for example, glass, quartz, high polymer, or other suitable plates. The material of the first metal layer ML1 may include metal (such as molybdenum, aluminum, copper, nickel, chromium), alloy, nitride of metal material, oxide of metal material, oxynitride of metal material, or other suitable materials, or a stacked layer of metal material and other conductive materials.

[0078] An insulating layer 110 is formed on the first metal layer ML1. The insulating layer 110 is, for example, a gate insulating layer, and its material may include silicon oxide, silicon nitride or other suitable dielectric materials. A semiconductor pattern SC and a second metal layer ML2 are formed on the insulating layer 110. Figure 4B is a schematic top view of the semiconductor pattern SC, and Figure 4C FIG. 2 is a schematic top view of the second metal layer ML2. In this embodiment, the second metal layer ML2 includes a data line DL (eg Figure 1 As shown in FIG. 1 ), a source electrode SE, a drain electrode DE and a capacitor electrode CPE. The capacitor electrode CPE overlaps the third common electrode CE3 of the first metal layer ML1 in the direction Z.

[0079] The semiconductor pattern SC can be used as a channel layer of the active device T, and the source electrode SE and the drain electrode DE are electrically connected to two different regions of the semiconductor pattern SC respectively. Here, the gate electrode GE, the source electrode SE, the drain electrode DE and the semiconductor pattern SC can constitute the active device T. The material of the semiconductor pattern SC may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, or a metal oxide semiconductor. In the present embodiment, the active device T may be a thin film transistor, such as an amorphous silicon thin film transistor (a-Si TFT), but not limited thereto. In other embodiments, the active device T may also be a polycrystalline silicon thin film transistor (polycrystalline silicon TFT, poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT). In some embodiments, an ohmic contact layer may be provided between the source electrode SE and the semiconductor pattern SC and between the drain electrode DE and the semiconductor pattern SC, and the material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but not limited thereto.

[0080] In the present embodiment, the gate GE is optionally disposed below the semiconductor pattern SC to form a bottom-gate thin-film-transistor, but the present invention is not limited thereto. In other embodiments, the gate GE may also be disposed above the semiconductor pattern SC to form a top-gate thin-film-transistor. The material of the second metal layer ML2 may include metal (e.g., molybdenum, aluminum, copper, nickel, chromium), alloy, nitride of metal material, oxide of metal material, oxynitride of metal material, or other suitable materials, or a stacked layer of metal material and other conductive materials.

[0081] Next, a passivation material layer 121M (ie, a first passivation material layer) is formed on the second metal layer ML2. Figure 3B The material of the passivation material layer 121M may include, for example, silicon nitride, silicon oxide or aluminum oxide, but is not limited thereto.

[0082] Please refer to Figure 3C and Figure 4D , a third metal layer ML3 is formed on the passivation material layer 121M. Figure 4D: is a schematic top view of the third metal layer ML3. The third metal layer ML3 may include a first common electrode CE1 and a dummy electrode DME that are separated in structure, so that the first common electrode CE1 and the dummy electrode DME may be electrically insulated from each other. The material of the third metal layer ML3 may include a metal (e.g., molybdenum, aluminum, copper, nickel, chromium), an alloy, a nitride of a metal material, an oxide of a metal material, a nitride oxide of a metal material, or other suitable materials, or a stacked layer of a metal material and other conductive materials.

[0083] A passivation material layer 122M is formed on the third metal layer ML3. Figure 3D Next, a capping layer 130 is formed on the passivation material layer 122M, as shown in FIG. Figure 3E , Figure 3F and Figure 4E shown. Figure 4E 1 is a schematic top view of the opening OP of the covering layer 130. The covering layer 130 has an opening OP overlapping the capacitor electrode CPE, and the opening OP exposes a portion of the passivation material layer 122M. For example, in the present embodiment, the material of the covering layer 130 may include a photosensitive material (e.g., a photoresist material), and the step of forming the covering layer 130 includes forming the covering material layer 130M on the passivation material layer 122M and performing an exposure process and a development process on the covering material layer 130M to remove a portion of the covering material layer 130M to form the opening OP. In other words, the patterning process of the covering material layer 130M can be completed without an etching process, which helps to save the number of process steps.

[0084] In the present embodiment, the coating layer 130 is, for example, an organic insulating layer, and its material may include polyester, polyolefin, polyacryl, polycarbonate, polyalkylene oxide, polyphenylene, polyether, polyketone, polyol, polyaldehyde, or other suitable materials, or a combination thereof. The passivation material layer 122M is, for example, an inorganic insulating layer, and its material may include, for example, silicon nitride, silicon oxide, or aluminum oxide, but is not limited thereto. Therefore, by providing the passivation material layer 122M, the problem of peeling caused by the coating layer 130 directly contacting the third metal layer ML3 can be avoided.

[0085] After the step of forming the coating layer 130 is completed, a passivation material layer 123M and a transparent conductive layer TCL are sequentially formed on the coating layer 130. Figure 3G and Figure 4F shown. Figure 4F1 is a schematic top view of the transparent conductive layer TCL. In the present embodiment, the transparent conductive layer TCL includes a second common electrode CE2. The second common electrode CE2 has an opening CE2op, and the opening CE2op overlaps the opening OP of the cover layer 130 and the capacitor electrode CPE in the direction Z, and the opening CE2op exposes a portion of the passivation material layer 123M. The material of the transparent conductive layer TCL may include metal oxide (for example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above), but is not limited thereto.

[0086] Next, a passivation material layer 124M (ie, a second passivation material layer) is formed on the transparent conductive layer TCL. Figure 3H The material of the passivation material layer 124M may include, for example, silicon nitride, silicon oxide, or aluminum oxide, but is not limited thereto.

[0087] Please refer to Figure 3H , Fig. 3I and Figure 4G , the passivation material layer 121M, the passivation material layer 122M, the passivation material layer 123M and the passivation material layer 124M are etched to form the passivation layer 121, the passivation layer 122, the passivation layer 123 and the passivation layer 124 having the contact hole TH. Figure 4G 1 is a schematic top view of the contact holes TH of the passivation layers 121, 122, 123 and 124. The contact holes TH of the passivation layers overlap the opening OP of the cover layer 130 and the opening CE2op of the second common electrode CE2 in the direction Z, and the contact holes TH expose a portion of the capacitor electrode CPE.

[0088] For example, the steps of etching the passivation material layer 121M (i.e., the first passivation material layer), the passivation material layer 122M (i.e., the fourth passivation material layer), the passivation material layer 123M (i.e., the third passivation material layer) and the passivation material layer 124M (i.e., the second passivation material layer) to generate the contact hole TH are performed in the same photolithography and etching process. Therefore, in addition to saving the number of process steps, the number of process masks used can also be reduced. In the present embodiment, because the material of the coating layer 130 is a photosensitive material (such as a photoresist material), and the material of the second common electrode CE2 includes a metal oxide, in order to avoid these passivation material layers being blocked by the second common electrode CE2 and the coating layer 130 during etching, the size of the contact hole TH is preferably smaller than the size of the opening CE2op of the second common electrode CE2 and the size of the opening OP of the coating layer 130, and the contact hole TH is completely located in the opening CE2op and the opening OP in the top view direction (that is, the size of the projection of the contact hole TH on the substrate 101 is smaller than the size of the projection of the opening CE2op of the second common electrode CE2 on the substrate 101 and the size of the projection of the opening OP of the coating layer 130 on the substrate 101, and the projection of the contact hole TH on the substrate 101 is completely located in the projection of the opening CE2op and the opening OP on the substrate 101), but is not limited to this.

[0089] In the present embodiment, the coating layer 130 may also be referred to as a flat layer to reduce the unevenness of the upper surface of the passivation layer 122, that is, the unevenness of the upper surface of the coating layer 130 is less than the unevenness of the upper surface of the passivation layer 122 (that is, the flatness of the upper surface of the coating layer 130 is greater than the flatness of the upper surface of the passivation layer 122), but the present invention is not limited thereto. For example, the coating layer 130 may be an organic material and is formed on the passivation material layer 122M by a coating method (such as spin coating or slit coating), but the present invention is not limited thereto. The film thickness of the coating layer 130 in the direction Z is greater than the film thickness of the passivation layer 122 in the direction Z. In addition, in the present embodiment, the film thickness of the coating layer 130 in the direction Z is also greater than the film thickness of any one of the passivation layer 121, the passivation layer 123, the passivation layer 124 and the insulating layer 110 in the direction Z. For example, the thickness of the coating layer 130 may range from 1 micrometer to 5 micrometers, but is not limited thereto.

[0090] Please refer to Figure 2 and Figure 4H After the formation steps of the passivation layer 121, the passivation layer 122, the passivation layer 123 and the contact hole TH of the passivation layer 124 are completed, the pixel electrode PE is formed on the passivation layer 124 (i.e., the second passivation layer). The pixel electrode PE extends into the opening OP of the cover layer 130 and is electrically connected to the capacitor electrode CPE through the contact hole TH. Figure 4His a top view schematic diagram of the pixel electrode PE. In the present embodiment, the pixel electrode PE is, for example, a reflective electrode, that is, in addition to receiving the grayscale signal transmitted by the data line DL, the pixel electrode PE can also serve as a reflective layer to reflect ambient light or reflect the light of the front light module arranged on the light-emitting side of the display panel 10. Therefore, the pixel electrode PE of the present embodiment can define the reflective area RA of the pixel structure PX, that is, the display panel 10 of the present embodiment can be a reflective display panel, but is not limited to this. According to other embodiments, the display panel can also be a transflective display panel. The material of the pixel electrode PE of the present embodiment may include metals, alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or stacked layers of metal materials and other conductive materials.

[0091] Next, the substrate 101 and the substrate 102 are assembled, wherein a liquid crystal layer LCL is filled between the substrate 101 and the substrate 102. Figure 2 Herein, the manufacturing of the display panel 10 of this embodiment is completed.

[0092] Please refer to Figure 2 , Figure 5A , Figure 5B and Figure 5C It is particularly noted that, since the second common electrode CE2 is disposed on the side of the cover layer 130 close to the pixel electrode PE, the distance between the second common electrode CE2 and the signal line (e.g., the data line DL or the scan line GL) is increased, so that the capacitive coupling effect between the second common electrode CE2 and the signal line (e.g., the data line DL or the scan line GL) can be effectively reduced. Therefore, the setting range of the second common electrode CE2 can be further expanded. For example, Figure 1 , Figure 4A , Figure 4C and Figure 4F As shown, the second common electrode CE2 can overlap and cover the scan line GL and the data line DL electrically connected to the pixel structure PX in the direction Z. In this embodiment, the overlapping area of ​​the second common electrode CE2 and the pixel electrode PE along the direction Z (eg Figure 5A ) may be larger than the overlapping area of ​​the first common electrode CE1 and the capacitor electrode CPE along the direction Z (as shown Figure 5B ) and the overlapping area of ​​the third common electrode CE3 and the capacitor electrode CPE along the direction Z (as shown Figure 5C shown).

[0093] That is to say, by increasing the overlapping area between the second common electrode CE2 and the pixel electrode PE, the capacitance of the second storage capacitor C2 can be greatly increased, thereby improving the overall storage capacitance of the pixel structure PX. From another point of view, the second common electrode CE2 can also overlap and cover a data line DL along the direction Z, and the second common electrodes CE2 of any two adjacent pixel structures PX are connected to each other, but not limited thereto.

[0094] Other embodiments will be listed below to illustrate the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments, which will not be repeated below.

[0095] Figure 6 is a cross-sectional schematic diagram of a display panel according to a second embodiment of the present invention. Figure 6 The display panel 10A of this embodiment is Figure 2 The difference between the display panel 10 and the display panel 10A of the present embodiment is that the second common electrode CE2 of the display panel 10A of the present embodiment can be directly disposed on the cover layer 130, that is, no common electrode CE2 is disposed between the second common electrode CE2 and the cover layer 130. Figure 2 A passivation layer 123 is shown.

[0096] In the present embodiment, the passivation layers 121, 122 and 124 have contact holes TH-A. Similar to the contact holes TH of the passivation layers 121, 122, 123 and 124 of the first embodiment, the contact holes TH-A of the present embodiment overlap the opening OP of the cover layer 130 and the opening CE2op of the second common electrode CE2 in the direction Z, and the contact holes TH-A expose a portion of the capacitor electrode CPE.

[0097] The manufacturing method of the display panel 10A of this embodiment is similar to that of the first embodiment and can refer to the first embodiment. Figures 3A to 3G and Fig. 3I For example, the passivation material layer 121M (i.e., the first passivation material layer), the passivation material layer 122M (i.e., the fourth passivation material layer), and the passivation material layer 124M (i.e., the second passivation material layer) may be etched in the same lithography and etching process to form the contact hole TH-A. Therefore, in addition to saving the number of process steps, the number of process masks used may also be reduced.

[0098] Figure 7 is a schematic top view of a display panel according to a third embodiment of the present invention. Figure 8 yes Figure 7 A schematic cross-sectional view of a display panel. FIG. 9A to FIG. 9I yes Figure 7 A schematic top view of each film layer of a display panel. Figure 8 correspond Figure 7For the sake of clarity, Figure 7 Omitted Figure 8 The substrate 101, the substrate 102, the common electrode layer CEL and the liquid crystal layer LCL are shown.

[0099] Please refer to Figure 7 and Figure 8 , different from Figure 1 and Figure 2 The display panel 10 is a reflective display panel. In this embodiment, the display panel 20 may be a transflective display panel. That is, the pixel structure PX-A of this embodiment may have both a transmissive area TA and a reflective area RA.

[0100] In detail, the pixel structure PX-A may further include a reflective layer RL defining the reflective area RA, and the reflective layer RL is directly disposed on the pixel electrode PE-A, and the reflective layer RL and the pixel electrode PE-A are electrically connected to each other. Figure 9H and Fig.9I 1 and 1 are top views of the pixel electrode PE-A and the reflective layer RL, respectively. It is particularly noted that, in the present embodiment, the reflective layer RL overlaps and covers a portion of the pixel electrode PE-A along the direction Z, and the portion of the pixel electrode PE-A not covered by the reflective layer RL defines the penetration area TA of the pixel structure PX-A. That is, in the present embodiment, the pixel electrode PE-A of the pixel structure PX-A is a light-transmitting electrode, and the material of the light-transmitting electrode includes a transparent conductive material. For example, the material of the pixel electrode PE-A may include a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above, but not limited thereto. The reflective layer RL may be used to reflect ambient light or reflect the light of the front light module disposed on the light-emitting side of the display panel 20, while the light of the backlight module disposed on the side of the substrate 101 of the display panel 20 away from the liquid crystal layer LCL can pass through the portion of the pixel electrode PE-A not covered by the reflective layer RL.

[0101] In this embodiment, the step of forming the pixel structure PX-A may include: sequentially forming a first metal layer ML1-A (eg, Fig. 9A As shown), the insulating layer 110, the semiconductor pattern SC (as shown Fig. 9B As shown), the second metal layer ML2-A (as Fig. 9C As shown), the third metal layer ML3-A (as Fig.9D As shown), the coating layer 130A (as Fig.9E As shown), the first transparent conductive layer TCL1 (as Fig.9F As shown), the second transparent conductive layer TCL2 (as shown Figure 9H ) and the reflective layer RL (as shown Fig.9IAs shown). The first metal layer ML1-A includes a scan line GL, a gate GE, and a third common electrode CE3-A; the second metal layer ML2-A includes a data line DL, a source electrode SE, a drain electrode DE, and a capacitor electrode CPE-A; the third metal layer ML3-A includes a dummy electrode DME and a first common electrode CE1-A; the first transparent conductive layer TCL1 includes a second common electrode CE2-A; and the second transparent conductive layer TCL2 includes a pixel electrode PE-A.

[0102] Similar to Figure 2 In the display panel 10 of the present embodiment, a passivation layer 121 is provided between the second metal layer ML2-A and the third metal layer ML3-A, a passivation layer 122 is provided between the third metal layer ML3-A and the cover layer 130A, and a passivation layer 124 is provided between the first transparent conductive layer TCL1 and the pixel electrode PE-A. The difference is that in the display panel 20 of the present embodiment, the second common electrode CE2-A can be directly provided on the cover layer 130A, that is, no passivation layer 124 is provided between the second common electrode CE2-A and the cover layer 130A. Figure 2 In some other embodiments, a passivation layer 123 is shown, but is not limited thereto. Figure 2 A passivation layer 123 is shown.

[0103] In the present embodiment, the passivation layer 121, the passivation layer 122 and the passivation layer 124 have a contact hole TH-B. Similar to the contact hole TH-A of the passivation layer 121, the passivation layer 122 and the passivation layer 124 of the second embodiment, the contact hole TH-B of the present embodiment overlaps the opening OP of the cover layer 130A and the opening CE2op of the second common electrode CE2-A in the direction Z, and the contact hole TH-B exposes a portion of the capacitor electrode CPE-A.

[0104] The manufacturing methods of the first metal layer ML1-A, the insulating layer 110, the semiconductor pattern SC, the second metal layer ML2-A, the third metal layer ML3-A, the overcoat layer 130A, the first transparent conductive layer TCL1 and the passivation layers 121, 122 and 124 of the display panel 20 of the present embodiment are similar to the manufacturing methods of the first metal layer ML1, the insulating layer 110, the semiconductor pattern SC, the second metal layer ML2, the third metal layer ML3, the overcoat layer 130, the transparent conductive layer TCL and the passivation layers 121, 122 and 124 of the first embodiment, and can refer to the manufacturing methods of the first embodiment. Figures 3A to 3G and Fig. 3IFor example, the passivation material layer 121M (i.e., the first passivation material layer), the passivation material layer 122M (i.e., the fourth passivation material layer), and the passivation material layer 124M (i.e., the second passivation material layer) may be etched in the same lithography and etching process to form the contact hole TH-B. Therefore, in addition to saving the number of process steps, the number of process masks used may also be reduced.

[0105] After forming the contact hole TH-B of the passivation layer 121, the passivation layer 122 and the passivation layer 124, a second transparent conductive layer TCL2 is then formed on the passivation layer 124. The second transparent conductive layer TCL2 includes a pixel electrode PE-A, and the pixel electrode PE-A is formed through the opening OP of the cover layer 130A and the contact hole TH-B formed in the passivation layer 121, the passivation layer 122 and the passivation layer 123 in the same photolithography process (e.g., Figure 9G As shown) is electrically connected to the capacitor electrode CPE-A.

[0106] After forming the second transparent conductive layer TCL2, a reflective layer RL is then formed on the second transparent conductive layer TCL2. The reflective layer RL is located in the reflective area RA of the pixel structure PX-A, a portion of the pixel electrode PE-A is overlapped and covered by the reflective layer RL along the direction Z, and another portion of the pixel electrode PE-A not covered by the reflective layer RL is located in the transmissive area TA of the pixel structure PX-A.

[0107] In this embodiment, the first common electrode CE1-A overlaps the capacitor electrode CPE-A and the data line DL of the second metal layer ML2-A and the scan line GL of the first metal layer ML1-A. Figure 2 and Figure 4D The third metal layer ML3 of the present embodiment has a hollow portion CE1op, and the hollow portion CE1op overlaps Figure 7 It is particularly noted that the first common electrode CE1-A overlaps with the second common electrode CE2-A and covers the data line DL and the scan line GL, and can shield the interference of the signals of the data line DL and the scan line GL on the pixel electrode PE-A.

[0108] Since the configuration relationship among the first common electrode CE1-A, the second common electrode CE2-A, the third common electrode CE3-A, the capacitor electrode CPE-A and the pixel electrode PE-A of this embodiment is similar to Figure 1 For the first common electrode CE1, the second common electrode CE2, the third common electrode CE3, the capacitor electrode CPE and the pixel electrode PE, please refer to the relevant paragraphs of the above embodiment for detailed description, which will not be repeated here. Figure 8As shown, the third common electrode CE3-A, the insulating layer 110, the capacitor electrode CPE-A, the passivation layer 121, the first common electrode CE1-A, the passivation layer 122, the covering layer 130A, the second common electrode CE2-A and the passivation layer 124, the pixel electrode PE-A and the reflective layer RL are arranged in sequence along the direction Z.

[0109] In particular, if Figure 8 As shown, since the second common electrode CE2-A is disposed on the side of the coating layer 130A close to the pixel electrode PE-A, the distance between the second common electrode CE2-A and the signal line (e.g., the data line DL or the scan line GL) is increased, so that the capacitive coupling effect between the second common electrode CE2-A and the signal line (e.g., the data line DL or the scan line GL) can be effectively reduced. Therefore, the setting range of the second common electrode CE2-A can be further expanded. For example, Figure 7 , Fig. 9A , Fig. 9C and Fig.9F As shown, the second common electrode CE2-A can overlap and cover the scan line GL and the data line DL electrically connected to the pixel structure PX-A in the direction Z. In this embodiment, the overlapping area of ​​the second common electrode CE2-A and the pixel electrode PE-A along the direction Z (as shown in FIG. Fig.9F and Figure 9H ) may be larger than the overlapping area of ​​the first common electrode CE1-A and the capacitor electrode CPE-A along the direction Z (as shown Fig. 9C and Fig.9D ) and the overlapping area of ​​the third common electrode CE3-A and the capacitor electrode CPE-A along the direction Z (as shown Fig. 9A and Fig. 9C shown).

[0110] That is to say, by increasing the overlapping area between the second common electrode CE2-A and the pixel electrode PE-A, the capacitance value of the second storage capacitor C2 can be greatly increased, thereby improving the overall storage capacitance of the pixel structure PX-A. For example, in a comparative embodiment in which the second common electrode CE2-A and the passivation layer 124 are not provided, the storage capacitance of the pixel structure can be 137.54 femtofarads, while the storage capacitance of the pixel structure PX-A of the present embodiment can be 873.67 femtofarads. Therefore, compared with the comparative embodiment, the storage capacitance of the pixel structure PX-A of the present embodiment can be increased by more than four times.

[0111] In summary, in a display panel and a manufacturing method thereof according to an embodiment of the present invention, a common electrode is provided between the capacitor electrode electrically connected to the active element and the coating layer, and another common electrode is provided between the pixel electrode electrically connected to the capacitor electrode and the coating layer. Since a common electrode is also provided on the side of the coating layer closer to the pixel electrode, in addition to shortening the distance between the pixel electrode and the common electrode, the overlapping range between the common electrode and the pixel electrode can also be larger, thereby increasing the storage capacitance of the pixel structure.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of scan lines and a plurality of data lines are arranged on the substrate, and the plurality of scan lines intersect the plurality of data lines; as well as A plurality of pixel structures are disposed on the substrate and electrically connected to the plurality of data lines and the plurality of scan lines, each of the plurality of pixel structures comprising: An active element, comprising a gate, a source and a drain, wherein the gate is electrically connected to one of the plurality of scan lines, and the source is electrically connected to one of the plurality of data lines; A pixel electrode electrically connected to the drain of the active element; A capacitor electrode extending from the drain electrode and electrically connected to the pixel electrode; A coating layer, disposed between the pixel electrode and the capacitor electrode; A first common electrode overlaps the capacitor electrode and is located between the coating layer and the capacitor electrode; A second common electrode overlaps the pixel electrode and is located between the cover layer and the pixel electrode; A first passivation layer is disposed between the capacitor electrode and the first common electrode; and The second passivation layer is disposed between the second common electrode and the pixel electrode.

2. The display panel according to claim 1, characterized in that: The first common electrode is electrically coupled to the capacitor electrode and forms a first storage capacitor, and the second common electrode is electrically coupled to the pixel electrode and forms a second storage capacitor.

3. The display panel according to claim 2, characterized in that: An overlapping area between the second common electrode and the pixel electrode is larger than an overlapping area between the first common electrode and the capacitor electrode.

4. The display panel according to claim 3, characterized in that: The capacitance value of the second storage capacitor is greater than the capacitance value of the first storage capacitor.

5. The display panel according to claim 2, characterized in that: Each of the plurality of pixel structures further includes a third common electrode overlapping the capacitor electrode and located between the capacitor electrode and the substrate. The third common electrode is electrically coupled to the capacitor electrode to form a third storage capacitor.

6. The display panel according to claim 1, characterized in that: The display panel has a reflective area, the pixel electrode is located in the reflective area, and the material of the pixel electrode includes metal.

7. The display panel according to claim 1, characterized in that: The display panel has a reflective area and a transmissive area, the pixel electrode is located in the reflective area and the transmissive area, the material of the pixel electrode includes a transparent conductive material, the multiple pixel structures each also include a reflective layer electrically connected to the pixel electrode, the reflective layer is located in the reflective area, the reflective layer overlaps and covers a portion of the pixel electrode, and the portion of the pixel electrode not covered by the reflective layer is located in the transmissive area.

8. A method for manufacturing a display panel, characterized in that: include: forming a metal layer on a substrate, wherein the metal layer includes a capacitor electrode; forming a first passivation material layer on the metal layer; forming another metal layer on the first passivation material layer, wherein the another metal layer comprises a first common electrode, and the first common electrode overlaps the capacitor electrode; forming a coating layer on the first passivation material layer and the another metal layer, wherein the coating layer has an opening overlapping the capacitor electrode; forming a transparent conductive layer on the coating layer, wherein the transparent conductive layer includes a second common electrode; forming a second passivation material layer on the transparent conductive layer, wherein the second passivation material layer extends into the opening and covers the first passivation material layer; Performing an etching process on the first passivation material layer and the second passivation material layer to generate a first passivation layer and a second passivation layer that expose a portion of the capacitor electrode; as well as A pixel electrode is formed on the second passivation layer, wherein the pixel electrode extends into the opening of the cover layer to be electrically connected to the capacitor electrode, and the pixel electrode overlaps the second common electrode.

9. The method for manufacturing a display panel according to claim 8, characterized in that: The metal layer is a second metal layer, and the other metal layer is a third metal layer, wherein before the step of forming the second metal layer, the method further includes: forming a first metal layer on the substrate, wherein the first metal layer includes a third common electrode; and An insulating layer is formed on the first metal layer, wherein after the step of forming a second metal layer, the second metal layer is located on the insulating layer.

10. The method for manufacturing a display panel according to claim 8, wherein: The material of the coating layer includes a light-sensitive material, and the steps of forming the coating layer include: forming a coating material layer on the first passivation layer and the another metal layer; and An exposure process and a development process are performed on the coating material layer to remove a portion of the coating material layer to form the opening.

11. The method for manufacturing a display panel according to claim 8, wherein: The steps of etching the first passivation material layer and the second passivation material layer are performed in the same lithography and etching process.

12. The method for manufacturing a display panel according to claim 8, wherein: Also includes: A reflective layer is formed on the pixel electrode, wherein the reflective layer is electrically connected to the pixel electrode.

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