Array substrate and display screen

Abstract

The embodiment of the invention provides an array substrate and a display screen. An electrical test metal wire, an outer common electrode and an inner common electrode are arranged on the side, away from a conductive layer, of a first insulating layer; the inner common electrode is arranged on the side close to the display area, and the outer common electrode is arranged on the side away from the display area. The electrical test metal wire is arranged between the outer common electrode and the inner common electrode, and the first insulating layer is provided with at least one first via hole and at least one second via hole, so that the conductive layer can be connected with the inner Com metal and the outer Com metal through the via holes of the first insulating layer, and then an outer Com signal is introduced into the inner Com. And the attenuation of the inner Com signal is compensated to improve the display performance of the screen.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display screen. Background Art

[0002] TFT (Thin Film Transistor) LCD (Liquid Crystal Display) achieves the display effect by deflecting the liquid crystal through the electric field formed between the pixel electrode and the Com (common) electrode.

[0003] Usually, the display substrate is designed with two circles of Com routing, inner and outer, such as Figure 1 As shown, generally speaking, the array substrate includes an external common electrode (external Com) and an internal common electrode (internal Com), wherein the internal common electrode is arranged on a side close to the display area, and the external common electrode is arranged on a side away from the display area, and an electrical test metal trace (ET signal line). Figure 1 The display substrate also includes PLG (Propel Link Gate, gate link drive) wiring, Source IC (source chip) and Gate IC (gate chip).

[0004] The inner Com is used to form the electric field required for liquid crystal deflection with the pixel electrode, and the outer Com surrounds the outer edge of the substrate for shielding and protection. The inner Com voltage signal is usually provided by an IC (integrated circuit), and the outer Com voltage signal is provided by an FPC (Flexible Printed Circuit).

[0005] For the internal COM signal, due to the larger resistance of ITO (indium tin oxide) and more voltage division, the signal attenuation from IC output to the farthest pixel is greater than that of the external COM. When the internal COM signal strength attenuates to a certain extent, it will affect the display effect. For vertically long screens, this effect is more severe.

[0006] Therefore, conventional panel designs connect the metal layers of the inner and outer COMs together at a point far from the IC end, and use the voltage signal of the outer COM to compensate for the signal attenuation of the inner COM.

[0007] However, for the panel where the Gate IC (gate driver chip, row driver chip) and Source IC (source driver chip, column driver chip) are separately located, there is a metal routing of the ET (Electric Test) signal between the inner COM and the outer COM, so the metal layers of the inner and outer COM cannot be directly connected together. Summary of the invention

[0008] The purpose of the embodiments of the present application is to provide an array substrate and a display screen. The specific technical solution is as follows:

[0009] A first aspect of the present application provides an array substrate, comprising:

[0010] An outer common electrode, an inner common electrode, a first insulating layer, a conductive layer, and an electrical test metal trace;

[0011] The electrical test metal trace, the outer common electrode and the inner common electrode are arranged on a side of the first insulating layer away from the conductive layer; the inner common electrode is arranged on a side close to the display area, and the outer common electrode is arranged on a side away from the display area; the electrical test metal trace is arranged between the outer common electrode and the inner common electrode;

[0012] At least one first via hole and at least one second via hole are provided in the first insulating layer; and the conductive layer connects the outer common electrode and the inner common electrode through the at least one first via hole and the at least one second via hole.

[0013] In a possible implementation manner, the array substrate further includes a second insulating layer and a first metal layer; the first metal layer is disposed between the second insulating layer and the first insulating layer;

[0014] The electrical test metal trace, the outer common electrode and the inner common electrode are arranged on a side of the second insulating layer away from the first insulating layer.

[0015] In a possible implementation manner, the first metal layer includes: a first sub-metal layer and a second sub-metal layer; the first sub-metal layer and the second sub-metal layer are separated by the first insulating layer, the second sub-metal layer is arranged on a side close to the display area, and the first sub-metal layer is arranged on a side away from the display area;

[0016] The first sub-metal layer includes a first outer common electrode, and the second sub-metal layer includes a first inner common electrode;

[0017] At least one third via hole and at least one fourth via hole are arranged in the first insulating layer; wherein, the depth of the third via hole is less than the depth of the first via hole, the depth of the fourth via hole is less than the depth of the second via hole, and the conductive layer connects the first external common electrode and the first internal common electrode through at least one third via hole and at least one fourth via hole.

[0018] In a possible implementation manner, the conductive layer includes a block structure, and / or the conductive layer includes at least one strip structure;

[0019] The block structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes;

[0020] and / or

[0021] The strip structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes;

[0022] The angle between the strip structure and the electrical test metal wiring is greater than a preset angle threshold.

[0023] In a possible implementation manner, the strip structure is perpendicular to the electrical test metal trace.

[0024] In a possible implementation manner, the conductive layer includes a plurality of strip structures, and the plurality of strip structures have the same width.

[0025] In a possible implementation manner, the array substrate further includes a plurality of transfer structures, and the transfer structures are arranged between the binding area and the switch area of ​​the array substrate;

[0026] The transfer structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer;

[0027] The second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on the side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on the side of the first insulating layer away from the second metal layer;

[0028] The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length;

[0029] The conductive layer includes an ET conductive part and an IC conductive part, the first insulating layer is provided with a fifth via, the first insulating layer and the second insulating layer are provided with a sixth via, the first metal layer is connected to the ET conductive part through the fifth via, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via; the first insulating layer and the second insulating layer are provided with multiple seventh vias, and the IC conductive part is connected to the IC signal line in the second metal layer through the seventh via.

[0030] In a possible implementation manner, the array substrate further includes a plurality of transfer structures, and the transfer structures are arranged between the binding area and the switch area of ​​the array substrate;

[0031] The transfer structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer;

[0032] The second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on the side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on the side of the first insulating layer away from the second metal layer;

[0033] The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length;

[0034] The conductive layer includes an ET conductive part and an IC conductive part;

[0035] The first insulating layer is provided with a fifth via hole, the first insulating layer and the second insulating layer are provided with a sixth via hole, the first metal layer is connected to the ET conductive part through the fifth via hole, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via hole; the first insulating layer and the second insulating layer are provided with through holes, and the IC conductive part is connected to the IC signal line in the second metal layer through the through holes.

[0036] In a possible implementation, the plurality of switching structures form a plurality of switching structure rows in the first direction, and the switching structures between two adjacent switching structure rows in the second direction are staggered.

[0037] A second aspect of the present application provides a display screen, comprising the array substrate described in the first aspect.

[0038] Beneficial effects of the embodiments of the present application:

[0039] An array substrate and a display screen are provided in an embodiment of the present application, wherein an electrical test metal trace, an external common electrode and an internal common electrode are arranged on a side of a first insulating layer away from a conductive layer; the internal common electrode is arranged on a side close to a display area, and the external common electrode is arranged on a side away from the display area; the electrical test metal trace is arranged between the external common electrode and the internal common electrode, and at least one first via hole and at least one second via hole are arranged in the first insulating layer, so that the conductive layer can be connected to the internal Com metal and the external Com metal through the first insulating layer via hole, thereby introducing the external Com signal into the internal Com, compensating for the attenuation of the internal Com signal to improve the display performance of the screen.

[0040] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0042] Figure 1 A schematic diagram of the structure of an array substrate in the related art;

[0043] Figure 2-1 This is a schematic diagram of the first structure of the array substrate provided in the embodiment of the present application;

[0044] Figure 2-2 A second structural schematic diagram of the array substrate provided in an embodiment of the present application;

[0045] Figure 2-3 A third structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0046] Figure 2-4 This is a fourth structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0047] Figure 3 This is a fifth structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0048] Figure 4 A sixth structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0049] Figure 5 A schematic diagram of a process of an array substrate provided in an embodiment of the present application;

[0050] Figure 6-1 A schematic diagram of a structure of a chip coating of an array substrate provided in the related art;

[0051] Figure 6-2 for Figure 6-1 A-A' section view;

[0052] Figure 7-1 A schematic diagram of a first structure of a chip coating of an array substrate provided in an embodiment of the present application;

[0053] Figure 7-2 for Figure 7-1 Sectional view of the section B-B';

[0054] Figure 8-1 A schematic diagram of a second structure of a chip coating of an array substrate provided in an embodiment of the present application;

[0055] Figure 8-2 for Figure 8-1Cross-sectional view of section B-B'. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0057] like Figure 2-1 As shown, the present application provides an array substrate, including:

[0058] External common electrode 01, internal common electrode 03, first insulating layer 05, conductive layer 06, electrical test metal trace 02;

[0059] The electrical test metal trace 02, the outer common electrode 01 and the inner common electrode 03 are arranged on a side of the first insulating layer 05 away from the conductive layer 06; the inner common electrode 03 is arranged on a side close to the display area, and the outer common electrode 01 is arranged on a side away from the display area; the electrical test metal trace 02 is arranged between the outer common electrode 01 and the inner common electrode 03;

[0060] At least one first via hole 110 and at least one second via hole 120 are disposed in the first insulating layer 05 ; the conductive layer 06 connects the outer common electrode 01 and the inner common electrode 03 through the at least one first via hole 110 and the at least one second via hole 120 .

[0061] The first insulating layer can be a protective layer (PVX). An electrical test metal trace (ET signal metal trace) 02 is set between the inner Com and the outer Com. The inner and outer Com metals cannot be directly connected together. At least one first via 110 and at least one second via 120 are set in the first insulating layer (PVX) 05, wherein the first via 110 is located on the outer Com side, and the second via 110 is located on the inner Com side, that is, the projection of the first via on the first insulating layer overlaps with the projection of the outer common electrode 01 on the first insulating layer; the projection of the second via on the first insulating layer overlaps with the projection of the inner common electrode 03 on the first insulating layer.

[0062] The number of vias may be one or more. In one example, a first via 110 and a second via 120 are provided in the first insulating layer 05 , wherein the first via 110 is provided on the outer com side, and the second via 120 is provided on the inner com side.

[0063] In an example, the number of first vias is n, and the number of second vias is m, wherein n and m are both integers not less than 1, and m and n may be equal or unequal, and the specific setting may be based on actual conditions and is not limited here.

[0064] When there are multiple first via holes and / or multiple second via holes, the sizes of the first via holes may be the same or different, and the sizes of the second via holes may be the same or different.

[0065] That is to say, the conductive layer can be directly connected to the outer Com metal through the first via 110, and the conductive layer can be directly connected to the inner Com metal through the second via 120. In an example, a conductive material is deposited in the first via 110 and the second via 120, so that a conductive bridging layer is designed between the inner and outer Com metals, that is, the conductive layer can be connected to the inner Com metal and the outer Com metal through the vias of the first insulating layer, thereby introducing the external Com signal into the inner Com, compensating for the attenuation of the internal Com signal to improve the display performance of the screen.

[0066] The material of the conductive layer may be ITO (indium tin oxide). The conductive material deposited in the first via 110 and the second via 120 may be the same as the material of the conductive layer, or may be different. In one example, the conductive material deposited in the first via 110 and the second via 120 is the same as the material of the conductive layer. In this way, the external COM signal is effectively connected to the internal COM at the remote end of the IC without increasing any manufacturing cost or affecting the difficulty of the process, thereby compensating for the attenuation of the internal COM signal and improving the display effect.

[0067] In an example, the distance between the second via hole and the farthest pixel is not greater than a first preset distance threshold. The first preset distance threshold can be determined based on actual conditions.

[0068] Because the inner Com is used to form the electric field required for liquid crystal deflection with the pixel electrode, for the inner Com signal, due to the large resistance of ITO (indium tin oxide) and the large voltage division, the farthest pixel is the pixel that is shortest and farthest from the IC during the process from IC output to transmission to the farthest pixel. The signal attenuation is also greater than that of the outer Com. Therefore, in order to ensure that sufficient magnetic field is provided for the farthest pixel, the inner Com near the farthest pixel needs to be compensated. Therefore, the position of the second via can be determined based on the position of the farthest pixel. The external Com signal is introduced into the inner Com to compensate for the attenuation of the inner Com signal to improve the display performance of the screen. The preset distance threshold can be set based on actual conditions.

[0069] based on Figure 2-1 The embodiment shown, as Figure 2-2As shown, in a possible implementation manner, the array substrate further includes a second insulating layer 04 and a first metal layer 07; the first metal layer 07 is disposed between the second insulating layer 04 and the first insulating layer 05;

[0070] The electrical test metal trace 02 , the outer common electrode 01 and the inner common electrode 03 are disposed on a side of the second insulating layer 04 away from the first insulating layer 05 .

[0071] In a possible implementation manner, the array substrate further includes a second metal layer, wherein the outer common electrode 01 , the inner common electrode 03 , and the electrical test metal trace 02 are all disposed on the second metal layer.

[0072] like Figure 2-3 As shown, the array substrate includes a second metal layer 00, wherein 00 includes three areas, namely 001, 002, and 003, the outer common electrode 01 is set at 001, the electrical test metal trace 02 is set at 002, and the inner common electrode 01 is set at 003.

[0073] based on Figure 2-2 The embodiment shown, as Figure 2-4 As shown, in a possible implementation manner, the first metal layer 07 includes: a first sub-metal layer 071 and a second sub-metal layer 072; the first sub-metal layer 071 and the second sub-metal layer 072 are separated by the first insulating layer, the second sub-metal layer 072 is arranged on a side close to the display area, and the first sub-metal layer 071 is arranged on a side away from the display area;

[0074] The first sub-metal layer 071 includes a first outer common electrode, and the second sub-metal layer 072 includes a first inner common electrode;

[0075] At least one third via hole 130 and at least one fourth via hole 140 are provided in the first insulating layer 05; wherein, the depth of the third via hole 130 is less than the depth of the first via hole 110, and the depth of the fourth via hole 140 is less than the depth of the second via hole 120, and the conductive layer connects the first external common electrode and the first internal common electrode through at least one third via hole 130 and at least one fourth via hole 140.

[0076] The first sub-metal layer 071 and the second sub-metal layer 072 are separated by the first insulating layer 05, the first outer common electrode is arranged in the first sub-metal layer 071, and the first inner common electrode is arranged in the second sub-metal layer 072. At least one third via 130 and at least one fourth via 140 can be arranged in the first insulating layer 05, and the conductive layer 06 connects the first outer common electrode and the first inner common electrode through the third via 130 and the fourth via 140.

[0077] That is, the common electrode may be provided in the second metal layer or in the first metal layer. If the common electrode is provided in the second metal layer, the first metal layer far from the display area may be set as the first sub-metal layer 071, the first metal layer close to the display area may be set as the second sub-metal layer 072, the third via 130 is located on the side of the first sub-metal layer 071, and the fourth via 140 is located on the side of the second sub-metal layer 072, that is, the projection of the third via on the first insulating layer 05 overlaps with the projection of the first sub-metal layer 071 on the first insulating layer 05; the projection of the fourth via on the first insulating layer 05 overlaps with the projection of the second sub-metal layer 072 on the first insulating layer 05.

[0078] The number of the third via hole 130 and the fourth via hole 140 may be one or more. In an example, one third via hole 130 and one fourth via hole 140 are disposed in the first insulating layer 05 .

[0079] In an example, the number of the third vias is x, and the number of the fourth vias is y, wherein x and y are both integers greater than 1, and x and y may be equal or unequal, and the specific setting may be based on actual conditions and is not limited here.

[0080] When there are multiple third via holes and / or multiple fourth via holes, the sizes of the third via holes may be the same or different, and the sizes of the fourth via holes may be the same or different.

[0081] Conductive material is deposited in the third via hole 130 and the fourth via hole 140, so that a conductive bridge layer is designed between the first outer com and the first inner com, that is, the conductive layer can be connected to the first outer com and the first inner com through the via hole of the first insulating layer 05. The outer com signal is introduced into the inner com to compensate for the attenuation of the inner com signal to improve the display performance of the screen.

[0082] The material of the conductive layer may be ITO (indium tin oxide). The conductive material deposited in the first via 110 and the second via 120 may be the same as the material of the conductive layer, or may be different. In one example, the conductive material deposited in the third via 130 and the fourth via 140 is the same as the material of the conductive layer. In this way, the external COM signal is effectively connected to the internal COM at the remote end of the IC without increasing any manufacturing cost or affecting the difficulty of the process, thereby compensating for the attenuation of the internal COM signal and improving the display effect.

[0083] In an example, the distance between the second via hole and the farthest pixel is not greater than a first preset distance threshold. The first preset distance threshold can be determined based on actual conditions.

[0084] In a possible implementation manner, the conductive layer includes a block structure, and / or the conductive layer includes at least one strip structure;

[0085] The block structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes;

[0086] and / or

[0087] The strip structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes;

[0088] The angle between the strip structure and the electrical test metal wiring is greater than a preset angle threshold.

[0089] In one example, the conductive layer can be designed as a block structure, such as Figure 3 As shown, a large conductive layer partially covers the inner and outer Com metal layers at the far end of the IC, and a hole is punched through the first insulating layer 05 to connect the conductive layer with the inner and outer Com metal layers, thereby realizing the connection between the inner Com signal and the outer Com signal, and providing compensation for the inner Com signal through the outer Com signal to improve the screen display effect. The outer Com signal can be effectively connected to the inner Com at the far end of the IC without increasing any manufacturing cost or affecting the difficulty of the process, thereby compensating for the attenuation of the inner Com signal and improving the display effect.

[0090] In one example, the bridged bulk structure conductive layer is changed into at least one strip structure. Figure 4 As shown in the figure, the area of ​​the strip structure is smaller than that of the block structure, and the overlapping area of ​​the strip structure and the ET signal metal line is small, so the coupling capacitance formed by the two is also reduced. When the coupling capacitance is small, the attenuation of the external Com signal can be reduced when the bridge ITO crosses the ET signal metal line, ensuring that the external Com signal can play the maximum effect when compensating the internal Com signal, which helps to improve the display effect.

[0091] At least one first via hole 110 and at least one second via hole 120 are disposed on each strip structure.

[0092] In one example, the conductive layer includes multiple strip structures. Since the bridging conductive layer is located at the top layer of the array substrate process and is close to the edge of the substrate, if a foreign object scratches the conductive layer, it is easy for water vapor to enter and corrode and spread throughout the film layer, causing the bridging function to fail. Multiple strip-structured bridging conductive layers can each perform their bridging functions, and the corrosion of one or more strips due to scratches will not affect the normal operation of the remaining strips, thereby improving the reliability of the bridging function.

[0093] The angle between the strip structure and the electrical test metal trace must be greater than the preset angle threshold to minimize the overlapping area between the bridge conductive layer and the ET metal trace, and minimize the coupling capacitance formed between the two. When the coupling capacitance is small, the attenuation of the external COM signal can be reduced when the bridge ITO crosses the ET metal trace, ensuring that the external COM signal can play the maximum effect when compensating the internal COM signal, which helps to improve the display effect.

[0094] In a possible implementation manner, the strip structure is perpendicular to the electrical test metal trace.

[0095] The strip structure is perpendicular to the electrical test metal trace, which minimizes the overlap area between the bridge conductive layer and the ET metal trace, and the coupling capacitance formed between the two is also minimized. When the coupling capacitance is small, the attenuation of the external COM signal can be reduced when the bridge ITO crosses the ET metal trace, ensuring that the external COM signal can play the maximum effect when compensating the internal COM signal, which helps to improve the display effect.

[0096] In a possible implementation manner, the conductive layer includes a plurality of strip structures, and the plurality of strip structures have the same width.

[0097] The strip structures have the same width, which can simplify the process without affecting the difficulty of production.

[0098] In one example, the line width and gap between adjacent strip structures are as equal as possible to ensure that the overlapping area between the bridging conductive layer and the ET metal line is minimized, and the coupling capacitance formed between the two is also minimized.

[0099] Based on the above embodiments, see Figure 5 , Figure 5 A schematic diagram of a process for manufacturing an array substrate includes the following steps:

[0100] Making the second metal layer: deposit a metal conductive layer (Mo or Al) on the transparent glass substrate. The thickness is adjusted appropriately based on the actual situation according to the process capabilities and electrical requirements. For example, the thickness is 300nm-500nm. Subsequently, the required graphics are produced through processes such as photolithography, development, and etching.

[0101] Making a second insulating layer: Continue to deposit an insulating layer (silicon nitride) on the substrate with the Gate layer pattern, and the thickness is appropriately adjusted based on the actual situation according to the process capability and electrical requirements, for example, the thickness is 300nm-500nm;

[0102] Making the Active layer: A semiconductor layer (amorphous silicon) is deposited on the substrate on which the second insulating layer has been deposited. The thickness is determined based on the actual situation, for example, the thickness is 180nm. The required pattern is then produced through processes such as photolithography, development, and etching.

[0103] Depositing the first layer of ITO (1st_ITO): Depositing an oxide semiconductor layer (indium tin oxide) on the substrate with the Active layer pattern. The thickness is determined based on the actual situation, for example, the thickness is 40nm. The required pattern is subsequently produced through processes such as photolithography, development, and etching.

[0104] Making the first metal layer: Continue to deposit a metal conductive layer (Mo or Al) on the substrate with the ITO layer pattern. The thickness is appropriately adjusted based on the actual situation according to the process capability and electrical requirements. For example, the thickness is 300nm-500nm. The required pattern is subsequently produced through processes such as photolithography, development, and etching.

[0105] Making the first insulating layer: Continue to deposit an insulating layer (silicon nitride) on the substrate with the SD layer pattern. The thickness is appropriately adjusted based on the actual situation according to the process capability and electrical requirements. For example, the thickness is 400nm-500nm. The required pattern is subsequently produced through processes such as photolithography, development, and etching.

[0106] Depositing the second layer of ITO (2st_ITO): A layer of oxide semiconductor layer (indium tin oxide) is further deposited on the substrate with the first insulating layer pattern. The thickness is determined based on the actual situation. For example, the thickness is 80nm. The required pattern is subsequently produced through processes such as photolithography, development, and etching.

[0107] FT_LCD achieves the display effect by outputting electrical signals from the IC to the substrate to deflect the liquid crystal inside the substrate (Panel). Therefore, in order for TFT_LCD to display normally, the IC (chip) and the panel must be packaged together with high precision.

[0108] COG (Chip on Glass) packaging technology is the most widely used IC packaging technology in the TFT_LCD industry. It produces Panel Pins (substrate pins) that correspond to IC Pins (IC pins) on the surface glass of the Panel Array (array substrate), and then packages the IC and panel together in a Pin-to-Pin manner by hot pressing.

[0109] In order to avoid scrapping of IC after bonding due to panel defects, it is necessary to perform ET lighting test on the panel before IC bonding in the module process to intercept defective screens.

[0110] The ET signal needs to be transferred from the first metal layer to the second metal layer before it comes out of the Switch structure and passes through the Panel Pin.

[0111] The traditional design is to integrate the ET signal transfer structure and the Panel Pin together, as shown below: Figure 6-1 - Figure 6-2 As shown, Figure 6-1 It includes the transfer structure and the Switch structure, where Figure 6-2 for Figure 6-1 In the cross-sectional view of A-A', a is the IC signal transmission path, and b is the ET signal transmission path.

[0112] The ET test structure is only used in the detection stage and is discarded after the module process is completed. However, such a design will cause the transfer structure to occupy the effective contact area between the Panel Pin and the IC Pin, resulting in a reduction in the number of effective vias for transmitting IC signals to the Panel Pin. For example, Figure 6-2 As shown in the figure, assuming that the resistance of a single via resistor is R, the total resistance of the vias shown in the figure is R / 5. The number of effective vias for transmitting IC signals to the Panel Pins is reduced, which leads to an increase in resistance during IC signal transmission, and the fault tolerance in each process is reduced, and the reliability of the display module is also reduced.

[0113] In a possible implementation manner, the array substrate further includes a plurality of transfer structures, and the transfer structures are arranged between the binding area and the switch area of ​​the array substrate;

[0114] The transfer structure comprises a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; the second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on a side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on a side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on a side of the first insulating layer away from the second metal layer;

[0115] The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length, the conductive layer includes an ET conductive part and an IC conductive part, the first insulating layer is provided with a fifth via 150, the first insulating layer and the second insulating layer are provided with a sixth via 160, the first metal layer is connected to the ET conductive part through the fifth via 150, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via 160; the first insulating layer and the second insulating layer are provided with a plurality of seventh vias 170, and the IC conductive part is connected to the IC signal line in the second metal layer through the seventh via 170.

[0116] like Figure 7-1and Figure 7-2 As shown, Figure 7-2 for Figure 7-1 In the cross-sectional view of B-B', c is the ET signal transmission path, and d is the IC signal transmission path. The first metal layer is shortened to reserve more space to complete the binding of IC Pin and Panel Pin. That is, the transfer structure does not occupy the effective contact area between Panel Pin and IC Pin, resulting in an increase in the number of effective vias for IC signal transmission to Panel Pin. Assuming that the resistance value of a single via is R, then Figure 7-2 The total resistance of the via after the optimized design is R / 7. Figure 6-2 The design solution reduces the resistance during IC signal transmission by nearly 30%, and improves the reliability of the display module. By separating the ET signal transfer structure from the Panel Pin, the number of vias for IC signal transmission to the Panel is increased, which can reduce the resistance during IC signal transmission while improving the fault tolerance in each process and enhancing display reliability.

[0117] The preset length may be determined based on actual conditions, for example, the preset length is 15 μm-20 μm.

[0118] like Figure 8-1 to Figure 8-2 As shown, in a possible implementation manner, the array substrate further includes a plurality of transfer structures, and the transfer structures are arranged between the binding area and the switch area of ​​the array substrate;

[0119] The transfer structure comprises a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; the second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on a side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on a side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on a side of the first insulating layer away from the second metal layer;

[0120] The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length, and the conductive layer includes an ET conductive part and an IC conductive part;

[0121] The first insulating layer is provided with a fifth via 150, the first insulating layer and the second insulating layer are provided with a sixth via 160, the first metal layer is connected to the ET conductive part through the fifth via 150, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via 160; the first insulating layer and the second insulating layer are provided with a through hole 180, and the IC conductive part is connected to the IC signal line in the second metal layer through the through hole 180.

[0122] The multiple parallel vias of the Panel Pin are further optimized into a single large via design, which further reduces the via resistance and optimizes the display effect. This design can effectively increase the contact area between the Panel Pin and the IC Pin without increasing any manufacturing cost or affecting the difficulty of the process. The single large via design for transmitting IC signals to the Panel Pin can further reduce the resistance during IC signal transmission, which helps to improve the pixel charging rate and thus improve the display effect.

[0123] In a possible implementation, the plurality of switching structures form a plurality of switching structure rows in the first direction, and the switching structures between two adjacent switching structure rows in the second direction are staggered.

[0124] The layout of the transfer structure can be set based on actual conditions and is not limited here.

[0125] The present application also proposes a display screen, comprising the array substrate of any of the above embodiments.

[0126] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0127] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0128] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: An outer common electrode, an inner common electrode, a first insulating layer, a conductive layer, and an electrical test metal trace; The electrical test metal trace, the outer common electrode and the inner common electrode are arranged on a side of the first insulating layer away from the conductive layer; the inner common electrode is arranged on a side close to the display area, and the outer common electrode is arranged on a side away from the display area; the electrical test metal trace is arranged between the outer common electrode and the inner common electrode; At least one first via hole and at least one second via hole are provided in the first insulating layer; and the conductive layer connects the outer common electrode and the inner common electrode through the at least one first via hole and the at least one second via hole.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a second insulating layer and a first metal layer; the first metal layer is arranged between the second insulating layer and the first insulating layer; The electrical test metal trace, the outer common electrode and the inner common electrode are arranged on a side of the second insulating layer away from the first insulating layer.

3. The array substrate according to claim 2, characterized in that: The first metal layer includes: a first sub-metal layer and a second sub-metal layer; the first sub-metal layer and the second sub-metal layer are separated by the first insulating layer, the second sub-metal layer is arranged on a side close to the display area, and the first sub-metal layer is arranged on a side away from the display area; The first sub-metal layer includes a first outer common electrode, and the second sub-metal layer includes a first inner common electrode; At least one third via hole and at least one fourth via hole are arranged in the first insulating layer; wherein, the depth of the third via hole is less than the depth of the first via hole, the depth of the fourth via hole is less than the depth of the second via hole, and the conductive layer connects the first external common electrode and the first internal common electrode through at least one third via hole and at least one fourth via hole.

4. The array substrate according to claim 1, characterized in that: The conductive layer includes a block structure, and / or the conductive layer includes at least one strip structure; The block structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes; and / or The strip structure connects the outer common electrode and the inner common electrode through at least one of the first via holes and at least one of the second via holes; The angle between the strip structure and the electrical test metal wiring is greater than a preset angle threshold.

5. The array substrate according to claim 4, characterized in that: The strip structure is perpendicular to the electrical test metal wiring.

6. The array substrate according to claim 4, characterized in that: The conductive layer includes a plurality of strip structures, and the plurality of strip structures have the same width.

7. The array substrate according to claim 1, characterized in that: The array substrate further comprises a plurality of transfer structures, wherein the transfer structures are arranged between the binding area and the switch area of ​​the array substrate; The transfer structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; The second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on the side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on the side of the first insulating layer away from the second metal layer; The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length; The conductive layer includes an ET conductive part and an IC conductive part, the first insulating layer is provided with a fifth via, the first insulating layer and the second insulating layer are provided with a sixth via, the first metal layer is connected to the ET conductive part through the fifth via, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via; the first insulating layer and the second insulating layer are provided with multiple seventh vias, and the IC conductive part is connected to the IC signal line in the second metal layer through the seventh via.

8. The array substrate according to claim 1, characterized in that: The array substrate further comprises a plurality of transfer structures, wherein the transfer structures are arranged between the binding area and the switch area of ​​the array substrate; The transfer structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; The second insulating layer is arranged on one side of the second metal layer, the first metal layer is arranged on the side of the second insulating layer away from the second metal layer, the first insulating layer is arranged on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is arranged on the side of the first insulating layer away from the second metal layer; The length of the first metal layer extending in the second direction of the transfer structure is less than a preset length; The conductive layer includes an ET conductive part and an IC conductive part; The first insulating layer is provided with a fifth via hole, the first insulating layer and the second insulating layer are provided with a sixth via hole, the first metal layer is connected to the ET conductive part through the fifth via hole, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via hole; the first insulating layer and the second insulating layer are provided with through holes, and the IC conductive part is connected to the IC signal line in the second metal layer through the through holes.

9. The array substrate according to claim 7 or 8, characterized in that: The plurality of transfer structures form a plurality of transfer structure rows in the first direction, and the transfer structures between two adjacent transfer structure rows in the second direction are staggered.

10. A display screen, characterized in that: The display screen comprises the array substrate according to any one of claims 1 to 9.

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