Cross-layer glue stacking prevention method applied to panel production field
By preparing the OPC model and the second model in panel production, and predicting and updating the design layout, the problem of inconsistent with the design size after lithography of the current layer is solved, the risk of glue stacking problems is reduced, and the reliability and performance of the circuit are improved.
Patent Information
- Application Number
- CN202411621483.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-02-28
AI Technical Summary
During the panel production process, the actual size after lithography of the current layer is difficult to match the design size, which leads to glue stacking problems, affects the next etching process, and even causes problems such as circuit short circuits.
By collecting actual measurement data on the photoresist, prepare the OPC model and the second model, use the second model to predict whether the mask layout is generated and the severity of the glue stacking, update the design layout based on the simulated glue stacking data, ensure that the OPC corrected layout is close to the design size, and avoid glue stacking problems.
The problem of inconsistent with the design size after the current layer lithography is solved, which reduces the risk of smaller gaps caused by the glue stacking problem, and improves the overall reliability and performance of the circuit.
Smart Images
Figure CN119535905A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of display panel production, and in particular, relates to a method for preventing cross-layer glue accumulation applied in the field of panel production. Background Art
[0002] In the field of panel production, as the size of the circuit design in the screen becomes smaller and smaller, it will get closer to the exposure limit of the photolithography machine, and the optical proximity effect will become more and more obvious. Therefore, it is necessary to use OPC (optical proximity correction) to correct the design layout so that its size after exposure and development is close to the design target. However, in the field of panel generation, different film layers need to be stacked after being photolithographed and etched layer by layer. As the number of film layers increases, the bottom film layer will affect the photolithography imaging of the upper film layer, especially when there is a small gap between the current layer and the bottom layer or between the bottom layer. The photoresist of the current layer will not be cleaned up after development, resulting in residual photoresist and forming a glue pile problem. The glue pile problem is a unique phenomenon of the panel production process and cannot be avoided. The glue pile problem will cause the actual size of the current layer after photolithography to be inconsistent with the design size, resulting in the gap between the current layer graphics becoming smaller. In severe cases, it will affect the next etching process and cause serious circuit short circuits and other problems. Summary of the invention
[0003] In order to solve the above problems, the present invention proposes a cross-layer glue stacking prevention method applied in the field of panel production, which not only solves the problem that the actual size of the current layer after photolithography is difficult to be consistent with the design size, but also reduces the risk of gap reduction caused by the glue stacking problem, thereby improving the overall reliability and performance of the circuit.
[0004] A first aspect of the present invention provides a method for preventing cross-layer glue accumulation in the field of panel production, comprising:
[0005] Step S1, collecting actual measurement data A of various patterns on the photoresist, and collecting actual measurement data B of the stacking positions of various patterns;
[0006] Step S2, preparing an OPC model based on the actual measurement data A;
[0007] Step S3, preparing a second model based on the actual measurement data A and the actual measurement data B;
[0008] Step S4, preparing a design layout according to the design requirements, performing OPC correction on the design layout using the OPC model, generating a mask layout, and executing step S5;
[0009] Step S5, using the second model to predict whether the mask layout has glue accumulation and the severity of glue accumulation, and summarizing the simulated glue accumulation data. If the simulated glue accumulation data fails to pass the check, step S6 is executed; if the simulated glue accumulation data passes the check, step S7 is executed;
[0010] Step S6, updating the design layout based on the simulation stacking data, and executing step S4;
[0011] Step S7, determine the mask layout.
[0012] Furthermore, in step S1, after the panel is produced according to the design layout, relevant data of the photoresist actually produced is measured to form actual measurement data A, and relevant position and size data of the photoresist stacking effect actually produced are measured to form actual measurement data B.
[0013] Furthermore, the OPC model is used to predict the morphology of the layout after exposure and development.
[0014] Furthermore, the second model is used to predict the position and morphology of the glue accumulation on the layout, and predict the severity of the glue accumulation.
[0015] Furthermore, the step S5 specifically includes: using the second model to simulate the mask layout, generate a simulation contour, find the location and size of the glue pile in the published drawing, and summarize the simulation glue pile data. If the severity of the glue pile exceeds the preset value, the inspection fails, and the step S6 is executed to correct the design layout; if the severity of the glue pile is less than the preset value, the inspection passes, and the step S7 is executed.
[0016] Furthermore, the step S6, updating the design layout based on the simulation stacking data, specifically includes:
[0017] In the design layout, the position where glue accumulation is predicted to occur and the gap becomes smaller is enlarged to generate a new design layout.
[0018] Furthermore, it also includes, during the loop execution process of step S4 to step S6, clearing the positions where glue accumulation is predicted to occur and the gaps become smaller, so that the updated design layout and mask layout can pass the inspection of step S5 to obtain the final mask layout.
[0019] A second aspect of the present invention provides an electronic device, comprising:
[0020] at least one processor; and a memory in communication with the at least one processor; wherein,
[0021] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for preventing cross-layer glue accumulation in the field of panel production as described in the first aspect of the present invention.
[0022] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which can be loaded and executed by a processor to implement a method for preventing cross-layer glue accumulation in the field of panel production as described in the first aspect of the present invention.
[0023] Compared with the prior art, the present invention is beneficial in that:
[0024] The technical solution of the present invention not only solves the problem that the actual size of the current layer after photolithography is difficult to be consistent with the design size, ensures that the morphology of the layout after OPC correction is close to the design size after exposure and development, but also reduces the risk of gap reduction caused by the glue stacking problem. When there is a small gap between the current layer and the bottom layer, there will be no adhesion after exposure and development. Moreover, the design layout is only changed slightly, and only the size of the small gap position is modified. The change has been verified by the second model, thereby improving the panel yield and improving the overall reliability and performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It is a schematic diagram of the original design layout provided by an embodiment of the present invention.
[0026] Figure 2 yes Figure 1 Schematic diagram of the morphology on the photoresist after exposure and development after OPC correction.
[0027] Figure 3 Schematic diagram of actual measurement data B of the stacking position provided by an embodiment of the present invention.
[0028] Figure 4 It is a schematic diagram provided by an embodiment of the present invention.
[0029] Figure 5 This is a schematic diagram of the design layout after the size of the small gap position has been modified.
[0030] Figure 6 yes Figure 5 Schematic diagram of the morphology on the photoresist after exposure and development after OPC correction.
[0031] Figure 7 The present invention provides a flowchart of a method for preventing cross-layer glue accumulation in the field of panel production, which is provided by an embodiment of the present invention.
[0032] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0033] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0034] Method Embodiment
[0035] like Figure 1 The figure shows a schematic diagram of the original design layout. Figure 2 for Figure 1 Schematic diagram of the morphology of the photoresist after exposure and development after OPC correction. The OPC correction tool can ensure that the morphology after photolithography development is close to the design size, but it cannot avoid the occurrence of the problem of glue accumulation. Figure 2 The red frame is a small gap formed by the bottom layer 1, bottom layer 2 and the current layer. After exposure and development, photoresist residue will be found, which is the phenomenon of photoresist accumulation. The residual photoresist will cause the gap of the current layer to become smaller. In severe cases, adhesion will occur, which will lead to a short circuit. In other positions of the current layer, there is no photoresist accumulation problem. Therefore, it is necessary to invent a method that can predict where photoresist accumulation will occur in the revised layout and the severity of photoresist accumulation, so as to change the design layout in advance and then perform OPC correction, to ensure that the size after development in other positions can be close to the design size, and the photoresist accumulation position should avoid the occurrence of smaller gaps.
[0036] In order to solve the above problems, the first aspect of the present invention provides a method for preventing cross-layer glue accumulation in the field of panel production, such as Figures 5 to 7 shown.
[0037] A method for preventing cross-layer glue accumulation based on application in the field of panel production, comprising:
[0038] S1, collect the actual measurement data A of various patterns on the photoresist, and collect the actual measurement data B of the stacking positions of various patterns.
[0039] After the panel is produced and prepared according to the design layout, the relevant data of the actually prepared photoresist is measured to form the actual measurement data A, and the relevant position and size data of the actually generated photoresist stacking effect are measured to form the actual measurement data B.
[0040] S2, preparing an OPC model based on the actual measurement data A.
[0041] It is necessary to prepare an OPC model (optical proximity correction model) based on the actual measurement data A collected on the photoresist. The OPC model uses the simulation or experimental data of the lithography optical model through a rule base to adjust the pattern edge.
[0042] The OPC model is calculated using the parameters of the lithography machine, such as wavelength, numerical aperture size, type of mask, extinction coefficient, refractive index, thickness and other parameters of each film layer; and the photoresist model of the OPC model is fitted using the actual measurement data A, and the parameters and coefficients of each kernel in the photoresist model are calculated; finally, after superimposing the signals of the optical model and the photoresist model, the simulation value of the model is calculated, and if the simulation value is consistent with the actual measurement data A, the preparation of the OPC model is completed.
[0043] The OPC model is used to predict the morphology of the layout after exposure and development, but cannot predict the generation of glue accumulation.
[0044] S3: Based on the actual measurement data A and the actual measurement data B, prepare a second model.
[0045] In this step, the measurement data A on the photoresist and the measurement data B on the deposit position actually collected in the same batch are used, and a deposit prediction module is added on the basis of the OPC model to form a second model.
[0046] The second model is formed by adding a glue accumulation prediction module to the OPC model, which is used to predict whether glue accumulation occurs in a small space across layers on the layout, and the location and size of the glue accumulation. The second model can predict where the glue accumulation phenomenon occurs in the layout and the morphology of the glue accumulation, so it can predict the severity of the glue accumulation.
[0047] The glue pile prediction module is used to calculate the light intensity accumulation value of the local position of the glue pile according to the thickness of the current layer and the bottom layer, and the angle between the glue pile length and the current layer thickness.
[0048] Specifically, the formula for calculating the light intensity accumulation value of the local position of the glue heap prediction module is:
[0049]
[0050] For example, the actual measurement data B of the stacking position is as follows: Figure 3 The yellow line position is shown.
[0051] like Figure 3 to Figure 4 As shown, x' is the left starting point of the yellow line segment, x is any position within the stacking range, k(x.x') is the light intensity value at the x position to be calculated, and L is the stacking length.
[0052] y=(D / d)×sin(β)×δ, where D is the current layer thickness; d is the bottom layer thickness; β is the angle; δ is the optimization coefficient, ranging from (0.1-0.5), and the specific value is determined by parameter optimization based on the actual measurement data B.
[0053] S4, preparing a design layout according to the design requirements, performing OPC correction on the design layout using the OPC model, generating a mask layout, and executing step S5.
[0054] S5, using the second model to predict whether the mask pattern has glue accumulation and the severity of the glue accumulation, and summarizing the simulated glue accumulation data. If the simulated glue accumulation data fails to pass the check, step S6 is executed; if the simulated glue accumulation data passes the check, step S7 is executed.
[0055] In this step, the second model is used to simulate the mask layout, generate a simulation profile, find the location and size of the glue pile in the published drawing, and summarize the simulated glue pile data. If the severity of the glue pile exceeds the preset value, the inspection fails, and the S6 step is executed to correct the design layout. If the severity of the glue pile is less than the preset value and meets the production expectations, the inspection passes and the S7 step is executed.
[0056] Whether the buildup is serious is generally determined based on predicting the location where the buildup occurs and the gap becomes smaller, and judging whether the gap is too narrow.
[0057] S6, updating the design layout based on the simulation stacking data, and executing step S4.
[0058] This step is performed only when the severity of the glue accumulation is high. The glue accumulation problem is affected by the process, and the position and size of the glue accumulation are mainly related to the shape and size of the graphics of the design layout. Therefore, the degree of glue accumulation can be reduced by changing the design layout.
[0059] Change the design layout, such as Figure 5 As shown, the position where the gap is predicted to become smaller due to glue accumulation is enlarged, and multiple attempts are required. A large size change will cause a large change in the circuit performance of the graphic, and a small size change cannot improve the problem of the smaller gap. Therefore, each time the size of the small gap is changed, it is necessary to re-execute step S4 and use the OPC model to re-correct it, and then re-execute step S5 to simulate and predict the size of the new gap through the second model until the minimum size change and correction value of the gap position in the design layout are determined, so that the updated design layout can pass the inspection.
[0060] S7, determine the mask layout and finalize it.
[0061] During the cyclic execution of steps S4 to S6, the OPC model and correction process, as well as the prediction function of the second model, are utilized to gradually clear the positions where glue accumulation is predicted to occur and the gaps become smaller. Ultimately, the updated design layout and mask layout are able to pass the inspection of step S5, and the final mask layout is finalized for actual OLED panel mask production.
[0062] The final simulation morphology diagram of the gap position of the mask layout is as follows: Figure 6 As shown, in actual production, the gap after exposure and development will meet the design specification requirements.
[0063] The advantages of the present invention are that it ensures that the morphology of the OPC-corrected layout is close to the design size after exposure and development, and can avoid adhesion after exposure and development when there is a small gap between the current layer and the bottom layer, and the design layout is only changed slightly, only the size of the small gap position is modified, and the modified value has been verified by the second model, so the yield rate in subsequent production is greatly improved.
[0064] Electronic device embodiment
[0065] A second aspect of the present invention provides an electronic device, comprising:
[0066] at least one processor; and a memory in communication with the at least one processor; wherein,
[0067] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for preventing cross-layer glue accumulation in the field of panel production as described in the first aspect of the present invention.
[0068] Figure 8 Schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 8 As shown, the electronic device may include one or more ( Figure 8 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a microprocessor (Microprocessor Unit, referred to as MPU) or a programmable logic device (Programmable logic device, referred to as PLD)) and a memory 104 for storing data. In an exemplary embodiment, the electronic device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 8 The structure shown is for illustration only and does not limit the structure of the above terminal device. Figure 8 More or fewer components as shown, or with Figure 8 Equivalent functions or comparisons shown Figure 8 A different configuration with more features is shown.
[0069] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the methods in the embodiments of the present invention. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, that is, to implement the above-mentioned methods. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0070] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the switching device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.
[0071] Computer Readable Storage Medium Embodiments
[0072] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program can be loaded and executed by a processor to implement the method for preventing cross-layer glue accumulation in the field of panel production as described in the first aspect.
[0073] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
Claims
1. A method for preventing cross-layer glue accumulation in the field of panel production, characterized in that: include: Step S1, collecting actual measurement data A of various patterns on the photoresist, and collecting actual measurement data B of the stacking positions of various patterns; Step S2, preparing an OPC model based on the actual measurement data A; Step S3, preparing a second model based on the actual measurement data A and the actual measurement data B; Step S4, preparing a design layout according to the design requirements, performing OPC correction on the design layout using the OPC model, generating a mask layout, and executing step S5; Step S5, using the second model to predict whether the mask layout has glue accumulation and the severity of glue accumulation, and summarizing the simulated glue accumulation data. If the simulated glue accumulation data fails to pass the check, step S6 is executed; if the simulated glue accumulation data passes the check, step S7 is executed; Step S6, updating the design layout based on the simulation stacking data, and executing step S4; Step S7, determine the mask layout.
2. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: In step S1, after the panel is produced and prepared according to the design layout, the data of the photoresist actually prepared is measured to form actual measurement data A, and the position and size data of the photoresist stacking effect actually generated are measured to form actual measurement data B.
3. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: The OPC model is used to predict the morphology of the layout after exposure and development.
4. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: The second model is used to predict the position and morphology of the glue accumulation on the layout, and predict the severity of the glue accumulation.
5. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: The step S5 specifically includes: using the second model to simulate the mask layout, generate a simulation outline, find the location and size of the glue pile in the published drawing, and summarize the simulation glue pile data. If the severity of the glue pile exceeds the preset value, the inspection fails, and the step S6 is executed to correct the design layout; if the severity of the glue pile is less than the preset value, the inspection passes, and the step S7 is executed.
6. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: The step S6, updating the design layout based on the simulation stacking data, specifically includes: In the design layout, the position where glue accumulation is predicted to occur and the gap becomes smaller is enlarged to generate a new design layout.
7. The method for preventing cross-layer glue accumulation in the field of panel production according to claim 1, characterized in that: It also includes, during the loop execution process from step S4 to step S6, clearing the positions where glue accumulation is predicted to occur and the gaps become smaller, so that the updated design layout and mask layout can pass the inspection of step S5 to obtain the final mask layout.
8. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for preventing cross-layer glue accumulation in the field of panel production as described in any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which can be loaded and executed by a processor according to a method for preventing cross-layer glue accumulation in the field of panel production as described in any one of claims 1 to 7.