Cache management method and device of storage array, controller and medium

Abstract

The invention relates to the technical field of storage, in particular to a cache management method and device for a storage array, a controller and a medium. The method comprises the following steps: mapping a storage array into a virtual logic address space according to a namespace, and dividing the virtual logic address space into virtual logic address groups; determining the active degree of cache data in the virtual logic address group according to the storage state corresponding to the virtual logic address group; and determining a target virtual logic address group needing to be stored in the storage array according to the active degree. Therefore, the problem that the data reading and writing efficiency of the storage array data is low can be effectively solved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a cache management method, device, controller and medium for a storage array. Background Art

[0002] Independent redundant storage arrays can combine multiple physical hard disks into one logical hard disk, providing higher storage performance than a single hard disk by accessing multiple physical hard disks in parallel. In addition, data redundancy protection is also provided for the storage array, that is, the write data is encoded through the redundant computing unit to generate redundant check information, and finally the check information is stored in the storage array together with the original write data, so as to facilitate data recovery after a failure occurs.

[0003] In the prior art, the execution logic of the NVMe master is not designed based on the redundant storage array, but is only managed by a remote host, which makes it impossible for the entire data end to take advantage of the independent redundant storage array, resulting in a long processing time and low data processing efficiency. Summary of the invention

[0004] In view of this, embodiments of the present application provide a cache management method, device, controller and medium for a storage array, which can effectively solve the problem of low efficiency in reading and writing data in the storage array.

[0005] In a first aspect, an embodiment of the present application provides a cache management method for a storage array, which is applied to a storage array controller, comprising:

[0006] Mapping the storage array into a virtual logical address space according to the namespace, and dividing the virtual logical address space into virtual logical address groups;

[0007] Determining the activity level of cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group;

[0008] A target virtual logical address group that needs to be stored in the storage array is determined according to the activity level.

[0009] In some embodiments, dividing the virtual logical address space into virtual logical address groups comprises:

[0010] Dividing the virtual logical address space according to a preset number of namespaces to obtain virtual logical address subspaces of a number equal to the preset number;

[0011] The continuous logical address blocks in the virtual logical address subspace are divided into a namespace array according to the redundancy mode of the storage array; a row of the logical address blocks in the namespace array is used as a stripe, and the namespace array is divided into multiple virtual logical address groups, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the storage array, and the virtual logical address group includes one to more stripes.

[0012] In some embodiments, determining the target virtual logical address group to be stored in the storage array according to the activity level includes:

[0013] The target cache data in the target virtual logical address group that needs to be stored in the storage array is determined according to the storage status.

[0014] In some embodiments, the storage status includes a read / write status flag bit corresponding to each logical address block in the virtual logical address group;

[0015] The step of determining target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state includes:

[0016] The cache data of the logical address block corresponding to the read-write status flag bit in the target virtual logical address group is in the write state is determined as the target cache data.

[0017] In some embodiments, the method further comprises:

[0018] When writing the target cache data into the storage array, redundancy calculation is performed on the cache data in each logical address block in the stripe to obtain verification data and write it into the verification block in the stripe; and the read-write status flag corresponding to the verification block is set to the write status.

[0019] In some embodiments, the method further includes: updating the corresponding storage states respectively according to the read and write operations of the virtual logical address groups corresponding to each namespace in the cache, specifically including:

[0020] If the data stored in the cache of the logical address block is first data, setting the read / write status flag corresponding to the logical address block to a write state, wherein the first data is write data sent by the remote host;

[0021] If the data stored in the cache of the logical address block is second data, the read / write status flag corresponding to the logical address block is set to a read state; the second data is empty data or read data read from the storage array.

[0022] In some embodiments, the storage status includes a full flag bit corresponding to each virtual logical address group;

[0023] The method further comprises:

[0024] Determine whether each read / write status flag bit corresponding to each logical address block in the virtual logical address group is in the write state, and obtain the number of logical address blocks whose read / write status flag bit is in the write state;

[0025] If the number of blocks is greater than a preset threshold, determining that the full flag bit corresponding to the virtual logical address group is in a full state;

[0026] The method further includes: using the virtual logical address group corresponding to the full state of the full flag as the target virtual logical address group.

[0027] In some embodiments, determining the target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state includes:

[0028] The cache data in the target logical address block in the target virtual logical address group is used as the target cache data; wherein, the target logical address block is in the target virtual logical address group, and the read-write status flag is the logical address block corresponding to the write status.

[0029] In some embodiments, determining the target virtual logical address group to be stored in the storage array according to the activity level includes:

[0030] Determining the virtual logical address group with a low activity level as the target virtual logical address group;

[0031] And / or, when the cache space is full, the virtual logical address group at the middle activity level is determined as the target virtual logical address group.

[0032] In some embodiments, the storage state includes a number of activity factor flag bits corresponding to each virtual logical address group;

[0033] The method further includes: updating the corresponding storage states respectively according to the read and write operation commands of the virtual logical address groups corresponding to each namespace in the cache, specifically including:

[0034] According to the frequency of receiving the read and write operation commands for the virtual logical address group, the corresponding activity factor flag value is set.

[0035] In some embodiments, setting the activity factor flag value corresponding to the virtual logical address group according to the frequency at which the virtual logical address group receives the read and write operation commands includes:

[0036] Counting objects according to the virtual logical address group according to a preset frequency and counting period;

[0037] In the counting cycle, the activity factor flag value is updated according to a preset update rule based on whether the virtual logical address group receives a read or write operation command.

[0038] In some embodiments, the activity factor flag value is updated according to a preset update rule according to whether the virtual logical address group receives a read or write operation command within the counting period, including:

[0039] If the read / write operation command is not received within the counting period, the respective digits of the activity factor flag value are retrieved according to the set digit sequence, and the second state value is updated and written to the digit corresponding to the first state value; wherein, in the initial state, the values ​​of the respective digits of the activity factor flag value are all the first state values;

[0040] If the read / write operation command is received within the counting cycle, the respective digits of the activity factor flag value are retrieved in the reverse order of the set digits, and the first state value is updated and written to the digit corresponding to the first second state value.

[0041] In some embodiments, determining the activity level of cache data in the virtual logical address group according to the storage state corresponding to the virtual logical address group includes:

[0042] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the second state values, the activity level of the cache data in the virtual logical address group is determined to be a low activity level;

[0043] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the first state values, the activity level of the cache data in the virtual logical address group is determined to be a high activity level;

[0044] Counting the number of digits of each digit of the activity factor flag value that are the number of digits of the first state value;

[0045] If the number of digits is greater than a preset number, the activity level of the cache data in the virtual logical address group is determined to be an intermediate activity level.

[0046] In some embodiments, the virtual logical address group is the granularity of the read and write operation commands;

[0047] The storage state includes a number of lock flag bits equal to the number of groups of each virtual logical address group;

[0048] The method further comprises:

[0049] When operating the current virtual logical address group according to the read / write operation command, setting the lock flag bit corresponding to the current virtual logical address group to a lock state;

[0050] Delaying the read and write operation commands accessing the virtual logical address group in the locked state.

[0051] In some embodiments, determining the target virtual logical address group to be stored in the storage array according to the activity level includes:

[0052] Determining a target logical address for storing the target cache data in the storage array according to the virtual logical address group and a preset logical address mapping relationship;

[0053] The target cache data is written into the storage array according to the target logical address.

[0054] In a second aspect, an embodiment of the present application provides a cache management device for a storage array, including: an address group division module, an activity level determination module, and a disk placement module;

[0055] An address group division module, used for mapping the storage array into a virtual logical address space according to the namespace, and dividing the virtual logical address space into virtual logical address groups;

[0056] An activity level determination module, configured to determine the activity level of cached data in the virtual logical address group according to a storage state corresponding to the virtual logical address group;

[0057] The disk placement module is used to determine a target virtual logical address group that needs to be stored in the storage array according to the activity level.

[0058] In a third aspect, an embodiment of the present application provides a control system of a storage array, comprising: a redundancy module, a non-volatile memory interface controller, a cache and a non-volatile storage control module; one end of the non-volatile memory interface controller is used to connect to a remote host, and the other end is connected to the redundancy module, and the redundancy module is connected to the storage array through the non-volatile storage control module; the non-volatile memory interface controller is used to process the connection with the remote host, and maintain and manage the command queue between the remote host; the non-volatile storage control module interacts with the storage array to read and write data through direct memory access technology; the redundancy module is connected to the cache;

[0059] The redundancy module implements a cache management method for a storage array provided in the first aspect of the present application.

[0060] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, it implements a cache management method for a storage array provided in accordance with the first aspect of the present application.

[0061] The embodiments of the present application have the following beneficial effects:

[0062] The present application maps a storage array to a virtual logical address space according to a namespace, and divides the virtual logical address space into virtual logical address groups; determines the activity level of cached data in the virtual logical address group according to the storage status corresponding to the virtual logical address group; and determines the target virtual logical address group that needs to be stored in the storage array according to the activity level. The present application's remote host performs read and write access to the storage array according to the namespace, and the present application divides the virtual logical address space mapped by the namespace into virtual logical address groups, and determines to store the cached data in the virtual logical address group into the storage array according to the activity level. The present application manages virtual logical addresses in groups, thereby ensuring that there is enough cache space available in the cache, speeding up the processing speed of read and write operation commands, and in addition, writes the cached data to the disk according to the activity level, further ensuring that there is enough cache space available. Therefore, the present application can effectively solve the problem of low efficiency in reading and writing data to the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 A structural block diagram of a storage array controller according to an embodiment of the present application is shown;

[0065] Figure 2 Another structural block diagram of a storage array controller according to an embodiment of the present application is shown;

[0066] Figure 3 A flow chart of a cache management method for a storage array according to an embodiment of the present application is shown;

[0067] Figure 4 A schematic diagram of a redundancy group in a cache management method of a storage array according to an embodiment of the present application is shown;

[0068] Figure 5 A schematic diagram of a namespace array in a cache management method for a storage array according to an embodiment of the present application is shown;

[0069] Figure 6 A flow chart showing a case where the activity factor flag bits are all 0 in the cache management method of the storage array according to an embodiment of the present application is shown;

[0070] Figure 7 A schematic diagram showing a LBAG to be cleared with all active factor flag bits being 0 in the cache management method of the storage array according to an embodiment of the present application is shown;

[0071] Figure 8 A flow chart is shown in the cache management method of the storage array of the embodiment of the present application when the cache space corresponding to the current namespace is insufficient for use;

[0072] Fig. 9 A schematic diagram of the structure of a cache management device of a storage array according to an embodiment of the present application is shown;

[0073] Fig.10 A schematic diagram of a namespace array in a namespace-based cache management method according to an embodiment of the present application is shown;

[0074] Fig.11 A schematic diagram of a namespace group in a namespace-based cache management method according to an embodiment of the present application is shown;

[0075] Fig.12 A schematic diagram showing a division of controller memory in a namespace-based cache management method according to an embodiment of the present application is shown;

[0076] Fig.13 A schematic diagram of stripes in a storage array data reading and writing method according to an embodiment of the present application is shown.

[0077] Description of main component symbols:

[0078] 100-storage array controller; 200-non-volatile storage array; 300-remote host; 110-storage interface control module; 111-message parsing module; 112-command queue processing module; 113-processor; 120-redundancy module; 130-non-volatile storage control module; 140-controller memory; 150-protocol offloading engine; 910-address group division module; 920-activity determination module; 930-disk placement module. DETAILED DESCRIPTION

[0079] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0080] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0081] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0082] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0083] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0084] The following first introduces the keywords involved in this application:

[0085] PCIe: peripheral component interconnect express, high-speed serial computer expansion bus standard.

[0086] NVMe: non volatile memory express, non-volatile high-speed transmission bus.

[0087] NVMe oF specification: The non-volatile memory interface (non volatile memory expressover fabrics) specification based on optical fiber is referred to as NVMe oF specification. NVMe oF specification is a storage network protocol. At present, storage devices based on NVMe oF usually adopt a multi-node architecture (node ​​can also be understood as a controller) to implement host access to storage devices to improve the reliability and continuity of storage services. NVMe oF specification is a high-speed storage protocol based on NVMe protocol. NVMe oF is used to access NVMe storage media across networks. NVMe oF adds fabric-related commands on the basis of NVMe, so that the application scenarios of NVMe are not limited to a device, but can be extended to cross-network communication. Among them, the so-called "fabric" refers to the network between the host and the storage medium. Typical forms of fabric include Ethernet, Fibre Channel, InfiniBand (IB), direct memory access RDMA, etc.

[0088] SSD: Solid State Drive.

[0089] HBM: High Bandwidth Memory.

[0090] The storage array in the present application includes a non-volatile storage array, and the embodiments of the present application are described based on the non-volatile storage array as an example.

[0091] Figure 1 A structural block diagram of a storage array controller according to an embodiment of the present application is shown. Exemplarily, the storage array controller 100 includes: a storage interface control module 110 , a redundancy module 120 , a non-volatile storage control module 130 and a controller memory 140 .

[0092] The redundancy module 120 is respectively connected to the storage interface control module 110, the non-volatile storage control module 130 and the controller memory 140. Exemplarily, the controller memory 140 may adopt HBM.

[0093] The storage interface control module 110 is in communication connection with the remote host 300 , and is used for receiving and parsing the message data sent by the remote host 300 to obtain operation commands, and scheduling and managing the operation commands based on the namespace and then transmitting them to the redundancy module 120 .

[0094] Furthermore, if Figure 2As shown, the storage interface control module 110 includes a message parsing module 111 , a command queue processing module 112 and a processor 113 . The storage array controller 100 also includes a protocol offload engine 150 .

[0095] The protocol offload engine 150 is used to receive a protocol message of a preset protocol type sent by the remote host 300 , parse the protocol message, and send the message data obtained by parsing to the message parsing module 111 in the storage interface control module 110 .

[0096] The processor 113 is connected to both the message parsing module 111 and the command queue processing module 112 .

[0097] The message parsing module 111 is used to receive and parse the message data sent by the remote host 300, obtain operation commands, and send data transmission type operation commands to the command queue processing module 112, and send non-data transmission type operation commands to the processor 113.

[0098] The processor 113 is used to establish a connection with the remote host 300 according to the operation command, and configure and manage the scheduling function parameters of the command queue processing module 112.

[0099] The command queue processing module 112 is used to store the operation command into the corresponding namespace command queue according to the accessed target namespace for scheduling management, and transmit the operation command to the redundancy module 120 in sequence.

[0100] The redundancy module 120 is used to perform redundancy calculation on the data and then write the data into the controller memory 140 , and manage the logical address space of the non-volatile storage array 200 and the controller memory 140 based on the namespace.

[0101] The non-volatile storage control module 130 is in communication connection with the non-volatile storage array 200 , and in response to a data transmission request of the redundancy module 120 , maps the controller memory 140 to implement data interaction with the non-volatile storage array 200 .

[0102] By way of example, the storage array controller 100 of the embodiment of the present application is introduced by taking the operation command as a write command. In this example, the storage interface control module 110 adopts an NVMe-oF controller, the non-volatile storage control module 130 adopts an NVMe-PCIe host, the protocol offload engine 150 adopts a TOE module (TCP / IP Offload Engine), and the controller memory 140 adopts HBM. The specific processing process of the storage array controller 100 includes the following steps:

[0103] S111, the TOE module receives a protocol message of a preset protocol type sent by the remote host 300, parses the protocol message, and sends the message data obtained by parsing to the NVMe-oF controller. The protocol message of the preset protocol type may be a TCP / IP / Ethernet message, and the message data is the data portion of the TCP / IP / Ethernet message.

[0104] S112, the message parsing module 111 in the NVMe-oF controller receives and parses the message data sent by the remote host 300, obtains an operation command, and sends the operation command of the data transmission type to the IOQ processing module. The operation command includes a PDU (Protocol Data Unit), and the operation command is determined to be a data transmission type according to the PDU, that is, the operation command is a write operation command.

[0105] S113, the IOQ processing module stores the write operation command into the corresponding namespace command queue according to the accessed target namespace for scheduling management, and sequentially transmits the write operation command to the redundancy module 120. In addition, the write operation command may also be added to the read / write command queue, the priority command queue, etc. When the IOQ processing module executes the write operation command for writing data, it sends an indication command to the redundancy module 120 to indicate that the redundancy module 120 prepares the idle first cache subspace to receive the data to be written.

[0106] S114 , the redundancy module 120 queries the cache status table to determine whether there is enough cache space in the controller memory 140 to receive the data to be written.

[0107] The redundancy module 120 needs to determine whether the controller memory 140 has the address space of the corresponding LBA block. If so, but the LBA block is in a state where the previous command is not completed, the write command is temporarily suspended until the corresponding LBA block is unlocked; if the controller memory 140 does not have the address space of the corresponding LBA block, the redundancy module 120 allocates an idle first cache subspace in the controller memory 140 according to the target logical address of the write operation command, and replies an R2T command to the remote host 300, where the R2T command is used to instruct the remote host 300 to send the data to be written.

[0108] If there is not enough cache space, the data in the corresponding namespace will be actively flushed to disk to free up cache space.

[0109] S115, after receiving the R2T command, the remote host 300 sends the data to be written in the form of a TCP / IP / Ethernet message, which is then parsed by the TOE module and the message parsing module 111 and sent to the redundancy module 120 via the IOQ processing module.

[0110] S116 , the redundancy module 120 divides the data blocks and calculates the check blocks according to the current redundancy mode of the non-volatile storage array 200 .

[0111] First, the redundancy module 120 needs to perform a data integrity check on the data to be written, and check whether the DIF (Data Integrity Field) of the data is consistent.

[0112] After the integrity check is passed, redundancy calculation is performed. If the current redundancy mode is k+m, the data is divided into k parts, and m parts of verification data are obtained based on the k parts of data encoding calculation. The k+m parts of data obtained after the redundancy calculation are written into the controller memory 140.

[0113] Send the CQ (Completion Queque) corresponding to the completion of writing data to the remote host 300 to notify the remote host 300 that the data writing has been completed. Since the redundancy module 120 has completed the data integrity check and ensured the reliability of the data to be written in the cache, the remote host 300 can be directly notified that the data writing has been completed without waiting for the data to be actually written to the non-volatile storage array 200 (NVME hard disk). When an error occurs in the integrity check at the non-volatile storage array 200 during the subsequent disk placement process, the data can be read again from the controller memory 140.

[0114] S117, the redundancy module 120 generates a disk write command to inform the NVMe-PCIe host of the cache address of k+m copies of data (the data to be written and the verification data after the redundancy calculation).

[0115] S118, the NVMe-PCIe host maps the corresponding first cache subspace to the memory of the NVME-PCIe host.

[0116] For example, the cache address of k+m copies of data is A1-A5. The NVME-PCIe host writes the first address A1 and the data length into the DMA register of the corresponding namespace in the NVMe hard disk. Each namespace corresponds to a register, and the register address is exchanged when the NVMe-PCIe host and the NVME hard disk initialize and establish a DMA connection.

[0117] When a DMA register in the NVMe hard disk is enabled, the NVMe hard disk can directly read k+m copies of data from the cache mapped by the corresponding NVMe-PCIe host by writing the first address A1 and data length of the register through the NVMe-PCIe host.

[0118] After the data is read, the NVMe hard disk writes the DMA completion flag into the DMA register of the NVMe-PCIe host.

[0119] S119, the NVMe-PCIe host sends a disk write completion notification in response to the DMA completion to notify the redundancy module 120 that the cache space of A1-A5 has been released, and the cache space can be continued to be used by the redundancy module 120.

[0120] Exemplarily, the storage array controller 100 of the embodiment of the present application is introduced below based on a read command as an example. The specific processing process of the storage array controller 100 includes the following steps:

[0121] S121, the TOE module parses the received TCP / IP / Ethernet message and sends the parsed message data (data part) to the NVMe-oF controller.

[0122] S122, the message parsing module 111 in the NVMe-oF controller decapsulates the message data to obtain an operation command, which includes a PDU (Protocol Data Unit). According to the PDU, it is determined that the operation command is a data transmission type (read operation command), and then the read operation command is sent to the IOQ processing module (command queue processing module 112).

[0123] S123, the IOQ processing module adds the received read operation command to a command queue for management and scheduling, such as a read / write command queue, a priority command queue or an NS (NameSpace) command queue.

[0124] When the read operation command is executed, an indication command is sent to the redundant module 120 to instruct the redundant module 120 to check whether there is an address space of the corresponding LBA block in the controller memory 140. If so, and it is not in a locked state, data is directly read from the address space of the corresponding LBA block in the controller memory 140; if so, and the corresponding LBA block is in a locked state, execution of the command is temporarily suspended; if there is no address space of the corresponding LBA block in the controller memory 140, a second cache subspace is prepared and relevant data is read.

[0125] At the same time, the IOQ processing module generates a command for reading consecutive addresses in the same namespace and transmits it to the redundancy module 120 .

[0126] S124, the redundancy module 120 queries the cache status table to see whether there is enough cache space to receive the data to be read.

[0127] If yes, the NVMe-PCIe host is instructed to read data from the NVMe hard disk, and the address of the second cache subspace for receiving the data and the target address of the data to be read are informed.

[0128] If there is not enough cache space, the data in the corresponding namespace will be sent to the remote host 300 first to free up cache space.

[0129] S125, the NVMe-PCIe host sends a command to read data to the NVMe hard disk, and maps the cache space to the memory of the NVMe-PCIe host to receive the data to be read.

[0130] S126, after the NVMe hard disk prepares the data to be read, the first address and length of the data are written into the DMA register of the NVMe-PCIe host.

[0131] S127, the NVMe-PCIe host responds to the DMA register enable, directly reads data from the memory of the NVMe hard disk according to the data address and data length written by the NVMe hard disk, and notifies the redundancy module 120 to release the relevant cache after reading.

[0132] S128 , the redundancy module 120 merges data blocks or recovers data according to the redundancy mode of the current array, and sends the data to the remote host 300 .

[0133] In order to improve the efficiency of the redundancy module 120 in processing data on the controller memory 140 based on the namespace, the embodiment of the present application further provides a cache management method, device, controller and medium for a storage array. In the embodiment of the present application, the redundancy module implements a cache management method for a storage array provided by the present application.

[0134] The cache management method of the storage array is described below in conjunction with some specific embodiments.

[0135] Figure 3 A flow chart of a cache management method for a storage array in an embodiment of the present application is shown. In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (referred to as cache) according to the current redundancy mode and the number of NS (NameSpace). Exemplarily, the cache management method for the storage array includes the following steps:

[0136] S210, map the non-volatile storage array 200 to a virtual logical address space according to the namespace, and divide the virtual logical address space into virtual logical address groups. Map the logical addresses of the non-volatile storage array 200 one by one to obtain a virtual logical address space, which includes virtual logical addresses (also known as VIR_LBA addresses) corresponding to all logical addresses (also known as LBA addresses, logical block addresses, Logical Block Address) in the non-volatile storage array 200. There is a mapping relationship between the VIR_LBA address in the embodiment of the present application and the LBA address of the non-volatile storage array 200, and the relationship between the LBA address and the PBA address (Physics Block Address, physical block address) in the non-volatile storage array 200 is processed by the controller in the non-volatile storage array 200 after the disk is placed, and there is no limitation in comparison with the present application. The storage array controller 100 of the present application is an external controller of the non-volatile storage array 200.

[0137] In one embodiment, the present application supports HMB (Host Memory Buffer) technology, and the memory of the storage array controller 100 is open to the controller of the non-volatile non-volatile storage array 200 to store the FTL (Flash Translation Layer) table. When the non-volatile non-volatile storage array 200 is a DRAMless hard disk, enabling this function can significantly improve the performance of the storage array.

[0138] Further, dividing the virtual logical address space into virtual logical address groups includes:

[0139] The virtual logical address space is divided according to a preset number of namespaces to obtain virtual logical address subspaces of a number equal to the preset number.

[0140] That is, the redundancy module 120 allocates a fixed VIR_LBA address space (virtual logical address subspace) to each namespace, as shown in Table 1.

[0141] Table 1 Namespace and VIR_LBA address space

[0142] Namespace VIR_LBA Address NameSpace1 VIR_LBA0-VIR_LBA99 NameSpace2 VIR_LBA100-VIR_LBA249 … … NameSpacex VIR_LBAm-VIR_LBAn

[0143] A fixed mapping is established between each VIR_LBA address of each namespace and the LBA address of the non-volatile storage array 200. As shown in Table 2, the LBA addresses of NS1 in the non-volatile storage array 200 are LBA1050-LBA1149.

[0144] Table 2 Mapping relationship between VIR_LBA address and LBA address in non-volatile storage array

[0145] VIR_LBA address of NS1 LBA address in storage array NS1-VIR_LBA0 LBA1050 NS1-VIR_LBA2 LBA1051 … … NS1-VIR_LBA99 LBA1149

[0146] For example, when a write data command for NS1 is received, the size of the write data is 10, and a virtual logical address VIR_LBA0-VIR_LBA9 is allocated for the write data command, and sufficient cache space is requested from the controller memory 140 (e.g., HBM High Bandwidth Memory) for VIR_LBA0-VIR_LBA9 to prepare for receiving the write data, and VIR_LBA0-VIR_LBA9 is mapped to the logical address LBA1050-LBA1059 of the non-volatile storage array 200 (e.g., SSD hard disk). Further, each continuous logical address block in the virtual logical address subspace is divided into a namespace array according to the redundancy mode of the non-volatile storage array 200; a row of the logical address blocks in the namespace array is regarded as a stripe, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the non-volatile storage array 200, and the namespace array is divided into a plurality of virtual logical address groups, and the virtual logical address groups include one or more stripes.

[0147] If the current redundancy mode is k+m, that is, there are k+m i members in a redundancy group, such as Figure 4 As shown, SSD1-SSDi is a redundant group.

[0148] In order to improve performance, the embodiment of the present application divides the namespace array into multiple virtual logical address groups, that is, the continuous VIR_LBA address space in a namespace is defined as a VIR_LBA group, denoted as VIR_LBAG. When the array is a redundant array, each VIR_LBAG divides the array according to the current redundancy mode.

[0149] Divide the cache array according to the current redundancy mode Figure 5(A namespace array divided by a virtual logical address group in a namespace under a redundant group), each row in the NS array (namespace array) is a stripe, and the number of LBA_BLOCKs (logical address blocks, also known as LBA blocks) in the stripe is determined by the number of redundant group members. The VIR_LBA address of the namespace corresponds one-to-one to the LBA address of the SSD disk. The number of LBA_BLOCK blocks in each column is related to the total VIR_LBA capacity allocated to the current NS, the overall cache capacity, and the actual storage business characteristics. For example, a NS may be mainly small random IO, so the number of LBA_BLOCK blocks in the array can be designed to be very small, and the same cache space can be divided into more VIR_LBAGs. For devices that support redundancy features, the VIR_LBAG in its cache is at least one stripe ( Figure 5 In other cases, multiple stripes can be divided into one VIR_LBAG for management and operation as required.

[0150] The space size of a VIR_LBAG and the number of LBA_BLOCKs remain unchanged when the configuration of the redundant group remains unchanged. They will not change even if individual group members in the redundant group fail (for example, an SSD member is damaged and cannot be used, but the entire redundant group can still recover data normally).

[0151] S220: Determine the activity level of cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group.

[0152] S230: Determine a target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level.

[0153] In order to ensure that the cache space has enough free space, the present application stores data with low activity levels on disk. It can be understood that the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level includes:

[0154] The virtual logical address group with a low activity level is determined as the target virtual logical address group.

[0155] When the cache space is full, the virtual logical address group at the middle activity level may also be determined as the target virtual logical address group.

[0156] Further, the determining the target virtual logical address group to be stored in the non-volatile storage array 200 according to the activity level includes:

[0157] The target cache data in the target virtual logical address group that needs to be stored in the non-volatile storage array 200 is determined according to the storage status.

[0158] Further, the determining the target virtual logical address group to be stored in the non-volatile storage array 200 according to the activity level includes:

[0159] The target logical address at which the target cache data is stored in the non-volatile storage array 200 is determined according to the virtual logical address group and the preset logical address mapping relationship.

[0160] The target cache data is written into the non-volatile storage array 200 according to the target logical address.

[0161] In one implementation, the storage status includes a read / write status flag bit corresponding one-to-one to each logical address block in the virtual logical address group.

[0162] Exemplarily, in the embodiment of the present application, an LBAG status table (also called a virtual logical address group status table) is used to record the allocation and use of VIR_LBAG in each namespace. That is, the storage status is stored in the LBAG status table. The activity level of the cached data in the virtual logical address group is determined according to the storage status recorded in the LBAG status table. The LBAG status table includes read-write status flags that correspond one-to-one to each logical address block (LBA_BLOCK) in the virtual logical address group. Multiple read-write status flags are required depending on the number of LBA_BLOCKs in the current virtual logical address group, and each LBA_BLOCK corresponds to a 1-bit read-write status flag, as shown in Table 3.

[0163] Table 3 LBAG status table 1

[0164]

[0165] The step of determining the target cache data in the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the storage state includes:

[0166] The cache data of the logical address block corresponding to the read / write status flag bit in the target virtual logical address group is determined as the target cache data. That is, in the target virtual logical address group, the logical address block corresponding to the read / write status flag bit in the write state is first determined to obtain the target logical address block, and the cache data in the target logical address block is determined as the target cache data. The target cache data is stored in the non-volatile storage array 200 to complete the disk placement.

[0167] Furthermore, the method further includes: updating the corresponding storage states respectively according to the read and write operations of the virtual logical address groups corresponding to each namespace in the cache, specifically including:

[0168] If the data stored in the cache of the logical address block is the first data, the read-write status flag corresponding to the logical address block is set to the write status, and the first data is the write data sent by the remote host 300. For example, if the data in the logical address block is the write data from the NVMe-oF controller, the read-write status flag corresponding to the logical address block is set to 1, indicating the write status. Therefore, when the current virtual logical address group needs to be written to the disk, the data corresponding to the logical address block with the read-write status flag position 1 must be written to the disk.

[0169] If the data stored in the cache of the logical address block is the second data, the read / write status flag corresponding to the logical address block is set to the read state; the second data is empty data or read data read from the non-volatile storage array 200. For example, if the data in the logical address block is read data from the SSD, or the logical address block is not currently written with data, the read / write status flag corresponding to the logical address block is set to 0, indicating a read state. Therefore, when the current virtual logical address group needs to be written to the disk, the data in the logical address block set to 0 will not be written to the disk.

[0170] Furthermore, the method further comprises:

[0171] When writing the target cache data into the non-volatile storage array 200, redundancy calculation is performed on the cache data in each logical address block in the stripe to obtain verification data and write it into the verification block in the stripe; and the read-write status flag corresponding to the verification block is set to the write status.

[0172] In the redundant mode, when the IOQ processing module transmits the write data to the redundant module 120, the write data is only divided according to the current redundant mode and stored in the corresponding data block cache. The verification calculation is not performed temporarily, and the corresponding verification block is empty. The verification data is calculated and filled into the corresponding verification block when it needs to be written to the disk. The read-write status flag corresponding to the verification block used to store the verification data will be forced to be set to 1 to indicate that the LBA_BLOCK needs to be written to the disk. For example, if the current redundant mode is k+m, then the write data is written into the k data LBA_BLOCKs in a stripe, and the read-write status flag is set to 1. Although the m verification blocks are temporarily empty and the verification data does not come from the NVMe-oF controller, the verification data will be calculated when it needs to be written to the disk, and the verification block will be written and the corresponding read-write status flag will be set to 1, indicating that the LBA_BLOCK needs to be written to the disk.

[0173] In one embodiment, the storage state includes a full flag bit corresponding to each virtual logical address group. One virtual logical address group corresponds to one full flag bit. The full flag bit is stored in 1 bit.

[0174] The method further comprises:

[0175] Determine whether each read-write status flag bit corresponding to each logical address block in the virtual logical address group is in the write state, and obtain the number of logical address blocks whose read-write status flag bit is in the write state. If the number of blocks is greater than a preset threshold, determine that the full flag bit corresponding to the virtual logical address group is in the full state. For example, in the write state, the full flag bit is set to 1, indicating that the cache space corresponding to the virtual logical address group is full or about to be full.

[0176] The method also includes: using the virtual logical address group corresponding to the full state of the write-full flag as the target virtual logical address group, that is, the virtual logical address group that needs to be written to the disk, and then determining the target cache data that needs to be written to the disk according to the read-write status identification bit.

[0177] Exemplarily, the number of 1s in each read / write status flag bit in the virtual logical address group is counted. When the number exceeds a preset threshold (such as 2 / 3 of the logical address block), the full flag bit is set to 1 to indicate that the virtual logical address group has been fully written, as a condition for writing to the disk. In one embodiment, the storage state includes a number of activity factor flag bits corresponding to each virtual logical address group. One virtual logical address group corresponds to one activity factor flag bit, and the size of the activity factor flag bit is 1 to n bits.

[0178] The method further includes: updating the corresponding storage states respectively according to the read and write operation commands of the virtual logical address groups corresponding to each namespace in the cache, specifically including:

[0179] According to the frequency of receiving the read and write operation commands for the virtual logical address group, the corresponding activity factor flag value is set. The greater the frequency of the read and write operations, the more active the virtual logical address group is.

[0180] Furthermore, the step of setting the corresponding activity factor flag value according to the frequency at which the virtual logical address group receives the read and write operation commands includes:

[0181] Counting objects according to the virtual logical address group according to a preset frequency and counting period;

[0182] In the counting cycle, the activity factor flag value is updated according to a preset update rule based on whether the virtual logical address group receives a read or write operation command.

[0183] Furthermore, in the counting period, according to whether the virtual logical address group receives a read / write operation command, updating the activity factor flag value according to a preset update rule includes:

[0184] If the read / write operation command is not received within the counting period, the respective digits of the activity factor flag value are retrieved in the set digit order, and the second state value is updated and written to the digit corresponding to the first first state value; wherein, in the initial state, the values ​​of the respective digits of the activity factor flag value are all the first state values.

[0185] If the read / write operation command is received within the counting cycle, the respective digits of the activity factor flag value are retrieved in the reverse order of the set digits, and the first state value is updated and written to the digit corresponding to the first second state value.

[0186] For example, once a virtual logical address group is allocated, the activity factor flag value of the activity factor flag bit defaults to all 1s. Whether the individual digits in the activity factor flag value will be set to 0 depends on a counter that is constantly naturally accumulated, and the operating frequency of the counter (i.e., the speed of counting) can be set. A certain technical cycle is set based on the counter. If no read or write operation is received for the current virtual logical address group when the counter overflows, one of the bits of the activity factor flag value is set to 0; when a read or write operation is received for the current virtual logical address group within a counting cycle of the counter, the counter is reset to zero and counted again, and a 0 bit of the activity factor flag value is flipped to 1.

[0187] For example, set the 3-bit activity factor flag value, the counter count cycle is t, the counter will naturally accumulate from 0, and after the count cycle t time, the counter reaches the maximum value and overflows. After the current virtual logical address group is allocated, the activity factor flag value is 111, and the counter starts counting. After a count cycle t time, no read / write operation is received for the current virtual logical address group, the activity factor flips to 110; the counter resets to zero and counts again. After another count cycle t time, still no read / write operation is received for the current virtual logical address group, the activity factor flag value flips to 100; the counter resets to zero and counts again, and the count cycle has not ended. If a read / write operation is received for the current virtual logical address group, the activity factor flag value flips to 110, and so on. That is, when the activity factor flag value receives a read or write command within the count cycle, the value on the 0 digit flips to 1, and so on; when the activity factor flag value is all 1, it does not overflow and remains all 1. If no read or write operation command is received during the counting cycle, the value of the 1 digit is flipped to 0, and so on; when the activity factor flag value is all 0, it will not overflow and remain all 0.

[0188] Further, determining the activity level of cache data in the virtual logical address group according to the storage state corresponding to the virtual logical address group includes:

[0189] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the second state values, the activity level of the cache data in the virtual logical address group is determined to be a low activity level.

[0190] If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the first state values, the activity level of the cache data in the virtual logical address group is determined to be a high activity level.

[0191] Counting the number of digits of each digit of the activity factor flag value that are the number of digits of the first state value;

[0192] If the number of digits is greater than a preset number, the activity level of the cache data in the virtual logical address group is determined to be an intermediate activity level.

[0193] The size of the activity factor flag value represents the activity of the virtual logical address group, that is, the hotness or coldness of the data. The larger the activity factor flag value, the more active the virtual logical address group. Active data should be kept in the cache as much as possible. If the activity factor flag value is all 0, it means that the virtual logical address group is no longer active and needs to submit a write command to the SSD disk. When the cache space is insufficient, the cache data in the intermediate active virtual logical address group that is not all 0 can also be initiated to be written to the disk according to the activity.

[0194] In the embodiment of the present application, the activity factor flag value is used to characterize the activity level of the data in the current virtual logical address group. The data with high activity level is retained in the cache, which reduces the frequent operation of the SSD disk after the active data is stored on the disk, thereby reducing the wear on the SSD disk and increasing the life of the SSD disk. At the same time, it also reduces the bandwidth requirements of the back-end PCIe channel and greatly improves the IO command performance of active data.

[0195] In one implementation, the virtual logical address group is the granularity of the read and write operation commands.

[0196] The storage state includes a number of lock flag bits that is equal to the number of virtual logical address groups. One virtual logical address group corresponds to one lock flag bit, for example, the size of the lock flag bit is 1 bit.

[0197] The method further comprises:

[0198] When operating the current virtual logical address group according to the read-write operation command, the lock flag bit corresponding to the current virtual logical address group is set to a locked state; and the read-write operation command accessing the virtual logical address group in the locked state is delayed. That is, after a read-write operation command operates the current virtual logical address group, before the read-write operation command is completed, the virtual logical address group is in a locked state, for example, the lock flag position 1 indicates a locked state. When a read-write operation command accessing the virtual logical address group in the locked state is subsequently received, the subsequent read-write operation command is delayed to prevent the previous and next read-write operation commands from conflicting with each other, causing confusion in the data of the virtual logical address group.

[0199] The granularity of each read / write operation command is a virtual logical address group. Even if the cache space currently requested is only one logical address block in the virtual logical address group, the entire virtual logical address group will be locked until the current command is completed, and the next read / write operation command for the current virtual logical address group can be executed. Although some I / O execution speed is sacrificed, a large number of repeated and frequent redundant calculations and access wear on the SSD are reduced.

[0200] The cache management method of the storage array of the embodiment of the present application is introduced below with reference to an example. In this example, the storage status includes a read-write status flag, a full flag, an activity factor flag and a lock flag, as shown in Table 4.

[0201] Table 4 LBAG status Table 2

[0202]

[0203] Among them, the active factor flag bit of the current virtual logical address group is all 0, indicating that the current virtual logical address group has been inactive for a long time and needs to be cleared, such as Figure 6 As shown, the specific steps include:

[0204] S301, the redundancy module 120 checks that the activity factor flag bits of the virtual logical address group are all 0, and determines that the virtual logical address group is at a low activity level.

[0205] S302, for the virtual logical address group of the low activity level, the redundancy module 120 calculates redundant check data according to the data of each LBA_BLOCK in the stripe and writes the redundant check data into the LBA_BLOCK corresponding to the check block, and sets the read / write status flag position of the LBA_BLOCK corresponding to the check block to 1.

[0206] S303, for the virtual logical address group with low activity level, the redundant module 120 takes the cache data in the LBA_BLOCK with the read / write status flag position 1 as the target cache data, submits the write operation instruction to the SSD disk, and writes the target cache data to the disk. After writing to the disk, the target cache data needs to be cleared, and then the read / write status flag position is set to 0.

[0207] For example, the current redundancy mode is 4+2, 4 data blocks and 2 redundancy check blocks, and the number of members of a stripe in the namespace is 6. Then the number of members of a stripe in the corresponding virtual logical address group is also 6.

[0208] like Figure 7 As shown, a virtual logical address group to be written to disk with all active factor flag bits 0 performs redundancy calculation based on the data in the logical address blocks: LBA_BLOCK5, LBA_BLOCK2, LBA_BLOCK1, and LBA_BLOCK0, writes the calculated check data into the check blocks LBA_BLOCK4 and LBA_BLOCK3, and sets the read-write flag bits of LBA_BLOCK4 and LBA_BLOCK3 to 1, then the current read-write flag bits change from 100001 to 111001. Then, an SSD write-to-disk operation instruction is issued based on its read-write flag bits, and the data of LBA_BLOCK5, LBA_BLOCK4, LBA_BLOCK3, and LBA_BLOCK0 with the read-write flag bits set to 1 are written to the SSD. After the write-to-disk operation is completed, the cache occupied by the virtual logical address group is released.

[0209] The following is an introduction to the cache management method of the storage array of the embodiment of the present application in conjunction with another example. In this example, when the cache space corresponding to the current namespace is insufficient, it is necessary to sort out the virtual logical address group that can be cleared as soon as possible to release the cache space to store data of other read / write commands, such as Figure 8 As shown, the specific steps are:

[0210] S401: The redundancy module 120 detects that the cache space corresponding to the current namespace is insufficient.

[0211] S402, the redundancy module 120 checks the full flag corresponding to each virtual logical address group in the LBAG status table, and uses the virtual logical address group with the full flag being 1 as the target virtual logical address group that needs to be written to disk.

[0212] S403, the redundancy module 120 checks the activity factor flag value of the activity factor flag corresponding to the target virtual logical address group, determines the activity level of the target virtual logical address group according to the activity factor flag value, and selects a target virtual logical address group with a low activity level.

[0213] S404, for the target virtual logical address group with low activity level, the redundancy module 120 calculates the redundant check data according to the data of each LBA_BLOCK of the stripe and writes it into the LBA_BLOCK corresponding to the check block. In addition, the read / write status flag corresponding to the LBA_BLOCK of the check data needs to be set to 1.

[0214] S405, for the target virtual logical address group with low activity level, the redundancy module 120 takes the cache data in the LBA_BLOCK with the read / write status flag position 1 as the target cache data, submits the write SSD disk operation instruction, and writes the target cache data to the disk. After writing to the SSD disk, the target cache data is cleared. In addition, after sending the data read from the non-volatile storage array 200 to the remote host 300, the cache data of the LBA_BLOCK with the read / write status flag position 0 needs to be directly cleared.

[0215] Fig. 9 A schematic diagram of the structure of a cache management device for a storage array according to an embodiment of the present application is shown. Exemplarily, the cache management device for a storage array includes: an address group division module 910 , an activity level determination module 920 , and a disk write module 930 .

[0216] An address group division module 910, configured to map the non-volatile storage array 200 into a virtual logical address space according to the namespace, and to divide the virtual logical address space into virtual logical address groups;

[0217] An activity level determination module 920, configured to determine the activity level of cache data in the virtual logical address group according to a storage state corresponding to the virtual logical address group;

[0218] The disk placement module 930 is used to determine the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level.

[0219] It can be understood that the device of this embodiment corresponds to the cache management method of the storage array of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0220] In order to improve the management efficiency of the controller memory by the redundancy module, the present application further provides a cache management method, storage array controller, device, equipment and medium. In the embodiment of the present application, the redundancy module implements a namespace-based cache management method of the present application.

[0221] In a cache management method based on namespace in an embodiment of the present application, for simplicity, the cache in the redundancy module 120 does not divide the read and write cache space separately, and the data in the cache space may come from the remote host 300 or the non-volatile storage array 200. The cache is only divided and managed by namespace, and each namespace is allocated a separate cache to store data. Namespaces belonging to different hard disks can write data in parallel, and independent namespace caches can prevent data in a certain namespace from occupying too much of the entire cache and slowing down the overall read and write speed.

[0222] The namespace-based cache management method is described below in conjunction with some specific embodiments.

[0223] In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (referred to as cache) according to the current redundancy mode and the number of NS (NameSpace). Exemplarily, the cache management method based on the namespace includes the following steps:

[0224] S2210: Allocate a cache area for the access command in a static cache subspace according to the namespace to be accessed by the access command.

[0225] The controller memory 140 in the embodiment of the present application includes a static cache space. It can be understood that the present application utilizes a preset capacity allocation rule to divide the static cache space according to the number of namespaces, and obtains static cache subspaces corresponding to each of the namespaces, as shown in Table 1. Thus, a static cache subspace is obtained. For example, a certain device supports i NS (NameSpace), and the static cache space is divided into i NS, as shown in Table 2-1. Each namespace corresponds to a static cache subspace. Thus, it is ensured that each NS has a certain cache space. Once a read or write operation command accesses the NS, the remote host 300 can be immediately notified that there is enough cache space to instruct the remote host 300 to send write data; the cache space will not be used up by other NSs and cannot respond to the command.

[0226] Table 2-1 Correspondence between namespace and static cache subspace

[0227] Namespace Static cache space NS1 Static cache subspace 1 NS2 Static Cache Subspace 2 … … NSi Static cache subspace i

[0228] Furthermore, the use of a preset capacity allocation rule to divide the static cache space according to the number of namespaces includes:

[0229] The static cache space is evenly divided according to the number of namespaces to obtain various static cache subspaces, and the static cache subspaces are fixed.

[0230] Alternatively, the namespaces may be divided according to a preset capacity ratio of each namespace, for example, a ratio of static cache space occupied is set for each namespace, and a fixed static cache subspace is divided for each namespace according to the ratio. However, once the static cache subspace is divided, the capacity is fixed and will not be adjusted according to the actual usage of the cache, nor will it change due to whether the NS is valid.

[0231] Further, the non-volatile storage array 200 is mapped into a virtual logical address space according to each of the namespaces. All logical addresses of the non-volatile storage array 200 are mapped with equal size to obtain a virtual logical address space. The virtual logical address space includes virtual logical addresses (referred to as VIR_LBA addresses) that correspond one to one with each logical address (referred to as LBA addresses) in the non-volatile storage array 200, as shown in Table 2-2.

[0232] Table 2-2 Mapping relationship between VIR_LBA address and LBA address in non-volatile storage array

[0233] VIR_LBA Address LBA address in storage array VIR_LBA0 LBA0 VIR_LBA1 LBA1 … … VIR_LBAi BnB

[0234] The virtual logical address space is divided according to the number of namespaces to obtain virtual logical address subspaces corresponding to each namespace. Thus, each virtual logical address subspace is obtained. The virtual logical address subspace includes multiple virtual logical addresses, as shown in Table 2-3.

[0235] Table 2-3 Correspondence between namespace and virtual logical address subspace

[0236] Namespace Virtual logical address subspace NS1 VIR_LBA0-VIR_LBA99 NS2 VIR_LBA100-VIR_LBA249 … … NSi VIR_LBAm-VIR_LBAn

[0237] Further, allocating a cache area for the access command in a static cache subspace according to the namespace to be accessed by the access command includes:

[0238] S3211, obtain a virtual logical address subspace according to the namespace matching.

[0239] S3212: Allocate a target virtual logical address for the access command from the virtual logical address subspace.

[0240] S3213: Allocate the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace.

[0241] In order to improve performance and facilitate management, the allocation granularity of the virtual logical address subspace corresponding to the NS is set according to the redundancy mode of the SSD hard disk (non-volatile storage array 200), and the virtual logical address subspace is divided into multiple stripes according to the number of members of the redundant group in the SSD hard disk. Specifically, according to the redundancy mode of the non-volatile storage array 200, the virtual logical address subspace is divided into a namespace array, and a row of virtual logical addresses in the namespace array is regarded as a stripe, such as Fig.10 As shown (the namespace array corresponding to NS1).

[0242] Further, in step S3212, allocating a target virtual logical address for the access command from the virtual logical address subspace includes:

[0243] When the access command is to access any virtual logical address in the stripe, the stripe is assigned to the access command as the target virtual logical address. It can be understood that when an access command accesses any virtual logical address in a stripe, the entire stripe where the virtual logical address is located will be allocated to the access command, and a cache area of ​​the entire stripe size will be applied for from the corresponding static cache subspace. Therefore, the static cache subspace should be set to an integer multiple of the stripe length. If a read command for NS1 is received to read the data corresponding to VIR_LBA3, it is necessary to apply for the corresponding cache area from the static cache subspace in NS1 for the entire stripe where VIR_LBA3 is located.

[0244] In step S3213, allocating the cache area for the target virtual logical address from the static cache subspace uniquely corresponding to the namespace includes:

[0245] If the cache area is not matched according to the stripe, a cache area is allocated to the stripe from the static cache subspace corresponding to the namespace according to the capacity of the stripe.

[0246] In one embodiment, in order to improve the data processing speed, the method of the embodiment of the present application further includes: dividing each namespace in the hard disk group of the non-volatile storage array 200 into a namespace group. The allocating a cache area for the access command in the static cache subspace according to the namespace to be accessed by the access command includes:

[0247] Access commands in different namespace groups are executed in parallel, and cache areas are allocated to corresponding access commands in corresponding static cache subspaces according to the namespaces to be accessed. Fig.11As shown, it is a schematic diagram of NS Group, where NameSpace1, NameSpace2 and NameSpace3 belong to NS Group1, NameSpace4, NameSpace5 and NameSpace6 belong to NS Group2. Different namespace groups can be accessed in parallel without affecting each other because they store different hard disk groups. Therefore, limiting the dynamic space usage of a single namespace group is beneficial to improving the overall processing efficiency of the array system.

[0248] S3220: Receive target data for reading and writing the non-volatile storage array 200 based on the access command, and cache the data in the cache area. The static cache subspace is obtained by dividing the static cache space in the controller memory 140 according to the namespace.

[0249] In one embodiment, in order to increase the speed of reading data, the present application also supports pre-reading data. The method also includes:

[0250] S3310: If the access command is a read command for reading a first virtual logical address, determine the stripe in which the first virtual logical address is located according to the first virtual logical address.

[0251] S3320, read the read data corresponding to the stripe in the non-volatile storage array 200; map the logical address of the non-volatile storage array 200 according to the virtual logical addresses corresponding to the stripe, and read the read data in the non-volatile storage array 200 according to the logical address of the non-volatile storage array 200.

[0252] S3330: Cache the read data to a cache area corresponding to the stripe, so as to serve as pre-read data for subsequent reading of other addresses in the stripe except the first virtual logical address.

[0253] For example, when receiving a read command for NS1 to read data corresponding to VIR_LBA3, it is necessary to apply for a corresponding cache area in the static cache subspace in NS1 for the entire stripe where VIR_LBA3 is located. Only the data corresponding to VIR_LBA3 can be read, or a pre-read operation can be performed to read all the data corresponding to the entire stripe from the non-volatile storage array 200 to the corresponding cache area. When a subsequent command reads data of VIR_LBA4 in the stripe, it can be read directly from the cache area, thereby improving the efficiency of reading data.

[0254] In one embodiment, the controller memory 140 also includes a dynamic shared cache space, such as Fig.12 shown.

[0255] The method further comprises:

[0256] When the static cache subspace corresponding to the namespace is in a full state, a storage area of ​​a preset capacity is applied for the namespace from the dynamic shared cache space.

[0257] Furthermore, the method further comprises:

[0258] Determine whether to approve the application based on the current capacity of the space, the current capacity of the space group, and the preset space capacity threshold and space group capacity threshold. The current capacity of the space is the current capacity of the static cache subspace obtained by the namespace; the current capacity of the space group is the sum of the current capacities of the static cache subspaces obtained by each namespace included in the namespace group.

[0259] Exemplarily, if the current capacity of the space group corresponding to the namespace group does not reach the space group capacity threshold, and the current capacity of the space corresponding to the namespace does not reach the space capacity threshold, it is determined that the application is approved, that is, the storage area is allowed to be allocated from the dynamic shared cache space, otherwise the application is not approved.

[0260] That is to say, in order to prevent a certain NS from occupying a large amount of dynamic space and affecting the use of other NS, the watermark of the dynamic space that can be applied is set for each NS and the namespace group to which the NS belongs in the embodiment of the present application. The application of dynamic space for all namespaces belonging to the same namespace group is limited by the namespace itself and the watermark (i.e., threshold) of the namespace group to which it belongs. When a namespace applies for dynamic space and touches any of the above watermarks, dynamic space will no longer be allocated to it.

[0261] Furthermore, the method further comprises:

[0262] When the static cache subspace is full, if it is determined that the application is not approved, the write data and pre-read data in the static cache subspace corresponding to the namespace are cleared. In order to execute commands, the namespace needs to release the cache space occupied by some completed commands in the namespace. For the cache of write commands, the backend is triggered to write to the disk as soon as possible; for the cache space of read commands, the pre-read data is cleared.

[0263] The following describes the namespace-based cache management method of the embodiment of the present application in conjunction with an example of a write command, which specifically includes the following steps:

[0264] S3401, the redundancy module 120 receives a write command, and allocates an idle virtual logical address VIR_LBA according to the namespace accessed by the current write command and the length of the data to be written, and records it as the first address.

[0265] S3402, the redundancy module 120 determines whether the stripe to which the first address belongs has been allocated a cache area according to the cache status table. If the stripe has been allocated a cache area, step S3403 is executed, and if not, step S3404 is executed.

[0266] S3403, the redundancy module 120 sends an R2T (Ready to Transfer, indicating that the cache area is ready) to the remote host 300 to instruct the remote host 300 to send the data to be written.

[0267] S3404, the redundancy module 120 determines whether there is a free cache area in the static cache sub-area of ​​the namespace corresponding to the stripe. If there is a free cache area, step S3405 is executed, otherwise step S3406 is executed.

[0268] S3405 , the redundancy module 120 allocates an available fixed cache area to the stripe from the static cache sub-area corresponding to the namespace.

[0269] S3406, the redundant module 120 determines whether the dynamic shared cache space applied for by the currently accessed NS triggers the preset water level (including the space capacity threshold and the space group capacity threshold). If triggered, cache cleanup is performed and the released cache space is allocated to the stripe. If not triggered, the corresponding shared cache area is allocated from the dynamic shared cache space to the stripe.

[0270] S3407, sends R2T (Ready to Transfer, indicating that the cache area is ready) to the remote host 300 to instruct the remote host 300 to send the data to be written, and stores the received data to be written into the second address (physical address of the cache space) corresponding to the first address (VIR_LBA of NS) in the allocated cache area.

[0271] In order to improve the data read and write processing speed of the storage array, for example, to improve the speed of determining the first cache subspace and the second cache subspace in the controller memory, the present application also provides a storage array data read and write method. The redundancy module in the present application implements a storage array data read and write method of the present application.

[0272] The storage array data reading and writing method is described below in conjunction with some specific embodiments.

[0273] In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (referred to as cache) according to the current redundancy mode and the number of NS (NameSpace). Exemplarily, the storage array data reading and writing method includes the following steps:

[0274] S4210: Determine a corresponding cache address space in a cache space management table according to an index of a target address stripe in a command to access the storage array.

[0275] Furthermore, in the embodiment of the present application, the non-volatile storage array 200 is mapped to a virtual logical address space according to each of the namespaces. For each logical address of the non-volatile storage array 200, there is a unique virtual logical address (Vir_LBA for short) corresponding to it in the virtual logical address space. The logical address in the corresponding non-volatile storage array 200 is determined by the virtual logical address.

[0276] The virtual logical address space is divided according to the number of each namespace to obtain virtual logical address subspaces corresponding to each namespace one by one, thereby obtaining the virtual logical address subspaces as shown in Table 3-1.

[0277] Table 3-1 Correspondence between namespace and virtual logical address subspace

[0278] Namespace Virtual logical address subspace NameSpace 1 VIR_LBA0-VIR_LBA99 NameSpace 1 VIR_LBA100-VIR_LBA249 … … NameSpace x VIR_LBAm-VIR_LBAn

[0279] Furthermore, in order to improve performance and facilitate management, the virtual logical address subspace corresponding to the namespace is divided into a namespace array according to the redundancy mode of the non-volatile storage array 200, and a row of virtual logical addresses in the namespace array is used as a stripe, thereby obtaining the target address stripe. That is, the allocation granularity of VIR_LBA in NS is set according to the redundancy mode of the SSD hard disk (the SSD hard disk in the non-volatile storage array 200), and the VIR_LBA in NS is divided into LBA stripes according to the number of members in the redundancy group in the SSD hard disk, such as Fig.13 shown.

[0280] Further, determining the corresponding cache address space in the cache space management table according to the index of the target address stripe includes:

[0281] S4211, determining a target namespace and a target virtual logical address to be accessed according to an access command to the non-volatile storage array 200. The access command includes the target namespace and the target virtual logical address.

[0282] S4212: Determine the target address stripe according to the target namespace and the target virtual logical address.

[0283] In one embodiment, determining the corresponding cache address space in the cache space management table according to the index of the target address stripe includes:

[0284] Matching the cache address space in the cache space management table according to the index;

[0285] If the match fails, the cache address space is obtained by dividing the target address stripe from the controller memory 140;

[0286] If the match is successful, the index is obtained, and the corresponding cache address space in the cache space management table is obtained.

[0287] Furthermore, in order to facilitate the management of cache space, in an embodiment of the present application, a cache space management table is established according to the index of the stripe. It can be understood that the method also includes: according to the serial number of the target address stripe, the divided cache address space is stored in the cache space management table. After the cache space (cache address space) is allocated from the controller memory for a stripe, the address of the cache space is written into the cache space management table. As shown in Table 3-2, the cache space management table records the physical address (Physics Block Address, physical block address, referred to as physical address, PBA) of the controller memory corresponding to each stripe.

[0288] Table 3-2 Cache space management table

[0289]

[0290]

[0291] When the cache needs to be searched, first determine the index of the stripe to which the virtual logical address corresponding to the access command is mapped, and then query the cache space management table based on the stripe index to see whether the stripe is allocated cache space. This application uses NS as the management unit, the index of the stripe where the virtual logical address is located as KEY, and the Value of each physical address bit allocated to the stripe to construct a key-value pair. When read and write commands need to find data stored in the cache space, they can hit it quickly.

[0292] S4220 , cache the read and write data determined based on the access command to the non-volatile storage array 200 into the controller memory 140 according to the cache address space.

[0293] When any VIR_LBA in the stripe is used, the virtual logical address of the entire stripe where the VIR_LBA is located will also be allocated, and the cache space of the entire stripe size will be applied. For example, if a write data command for NS1 is received, the data length is 5, and the virtual logical address VIR_LBA0-VIR_LBA4 is allocated. Since VIR_LBA is allocated and managed in stripes, stripe 1 is allocated to the current write data command, and sufficient cache space is applied from the controller memory for the stripe to cache the write data to be received. The received write data is cached in the cache space corresponding to LBA0-LBA4.

[0294] S4230: If the access command is a read command, the target data and the pre-read data are read according to the target address stripe and cached into the controller memory.

[0295] In one implementation, in order to significantly reduce the latency of the read command, the embodiment of the present application supports pre-reading data. It can be understood that, according to the cache address space, the read and write data determined based on the access command to the non-volatile storage array 200 is cached to the controller memory 140, including:

[0296] If the access command is a read command, acquiring the virtual logical address segment of the target data and the continuous virtual logical address segments adjacent thereto according to the target address stripe;

[0297] The target data and the pre-read data are read from the non-volatile storage array 200 and cached in the controller memory according to the virtual logical address segment.

[0298] S4240, sending the target data.

[0299] The target data requested by the read command is sent to the host, and then the target data and the pre-read data are retained in the controller memory 140 so as to be directly read from the controller memory 140 by subsequent access commands related to the virtual logical address segment.

[0300] For example, when a read command is received, a command for reading related continuous addresses is generated according to the target access address of the read command and is passed to the redundancy module 120 (EC / RAID). The redundancy module 120 reads data from the non-volatile storage array 200 according to the related continuous addresses and caches the read data in the controller memory 140. After the IOQ processor 113 subsequently receives a command to access the related continuous addresses, the above data can be quickly taken out from the controller memory 140, thereby significantly reducing the latency of the read command.

[0301] In one embodiment, the method further comprises:

[0302] If the access command is a read command, determining the target address stripe to which the virtual logical address segment to be accessed by the read command belongs according to the virtual logical address segment to be accessed;

[0303] Matching a target cache address space in the cache space management table according to the index of the target address stripe;

[0304] If the match is successful, the pre-read data is read from the target cache address space according to the cache address to be accessed by the read command.

[0305] In one embodiment, the embodiment of the present application not only supports write termination and significantly reduces write latency, but also can identify the activity level of data in the controller memory 140 to reduce wear on the SSD hard disk. It can be understood that the method also includes: writing the write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the present application enables the redundant module 120 to identify the activity level of data in the controller memory 140, temporarily store active data in the cache space, and not write to the disk. When there is a subsequent related write command to update the data, it can be completed directly in the cache space, reducing wear on the SSD hard disk.

[0306] In one implementation, the embodiment of the present application supports a write summary function. When the redundancy module 120 writes the data corresponding to the write command into the controller memory 140 managed by the redundancy module 120, the command completion information CQ can be sent to the remote host 300 without waiting for the data to be actually written to the SSD disk, thereby significantly reducing the write latency. It can be understood that in step S4220, the read and write data determined based on the access command to the non-volatile storage array 200 is cached to the controller memory 140 according to the cache address space, including:

[0307] If the read / write data is write data, after the write data is cached in the controller memory 140 , command completion information is sent to the remote host 300 .

[0308] Furthermore, if the read / write data is write data, after caching the write data in the controller memory 140, sending command completion information to the remote host 300 includes:

[0309] An integrity check is performed on the write data.

[0310] If the verification fails, a prompt message indicating a data write error is sent to the remote host 300;

[0311] If the verification passes, a command completion message is sent to the remote host 300.

[0312] In one embodiment, the embodiment of the present application not only supports write termination and significantly reduces write latency, but also can identify the activity level of data in the controller memory 140 to reduce wear on the SSD hard disk. It can be understood that the method also includes: writing the write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the present application enables the redundant module 120 to identify the activity level of data in the controller memory 140, temporarily store active data in the cache space, and not write to the disk. When there is a subsequent related write command to update the data, it can be completed directly in the cache space, reducing wear on the SSD hard disk.

[0313] The following describes the storage array data reading and writing method according to an embodiment of the present application in conjunction with an example of a write command, which specifically includes the following steps:

[0314] S4301, the redundancy module 120 receives a write command, and determines the stripe to which it is mapped according to the namespace and target virtual logical address accessed by the current write command.

[0315] S4302, query whether the stripe is in the cache in the established cache space management table according to the index of the stripe. If the stripe is in the cache, it means that the stripe cache address space (for example, PBAx-PBAy) has been allocated for the stripe, and then execute step S4304; if not, it means that the stripe cache address space has not been allocated, and then execute step S4303.

[0316] S4303: Apply for a cache address space in the controller memory 140 for the stripe, for example, PBAx-PBAy.

[0317] S4304, sending R2T (Ready to Transfer, indicating that the cache address space is ready) to the host to instruct the remote host 300 to send the data to be written.

[0318] S4305, the redundancy module 120 performs integrity check on the data to be written. If the check fails, a CQ with an error prompt is sent to the remote host 300; if the check passes, a CQ with a completion status (corresponding to command completion information) is sent and step S4306 is executed.

[0319] S4306, storing the data to be written after integrity verification into the allocated cache address space.

[0320] The following is an introduction to the storage array data reading and writing method of the present application embodiment with reference to an example of a read command, which specifically includes the following steps:

[0321] S4401, the redundancy module 120 receives a read command, and determines the stripe to which it is mapped according to the namespace and target virtual logical address accessed by the current read command.

[0322] S4402: query the cache space management table according to the index of the stripe whether the stripe is in the cache. If the stripe is in the cache, execute step S4404; if not, execute step S4403.

[0323] S4403, apply for a cache address space, such as PBAm-PBAn, in the controller memory 140 for the stripe.

[0324] S4404, determine whether the physical address corresponding to the virtual logical address of the stripe is used; if it is used, it means that pre-read data already exists, and then directly read the pre-read data cached at the physical address and use the pre-read data as the read data.

[0325] If it is not in use, a pre-read command is initiated to the SSD hard disk to read the data corresponding to the entire stripe, and the pre-read data read is stored in the allocated cache address space.

[0326] S4405, returning the read data in the physical address corresponding to the target virtual logical address to the remote host 300.

[0327] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the functions of each module in the cache management method of the storage array or the cache management device of the storage array.

[0328] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0329] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0330] The present application also provides a computer-readable storage medium for storing the computer program used in the above-mentioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0331] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0332] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0333] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0334] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A cache management method for a storage array, characterized in that: Applicable to storage array controllers, including: Mapping the storage array into a virtual logical address space according to the namespace, and dividing the virtual logical address space into virtual logical address groups; Determining the activity level of cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group; A target virtual logical address group that needs to be stored in the storage array is determined according to the activity level.

2. The cache management method of the storage array according to claim 1, characterized in that: Dividing the virtual logical address space into virtual logical address groups comprises: Dividing the virtual logical address space according to a preset number of namespaces to obtain a number of virtual logical address subspaces equal to the preset number; The continuous logical address blocks in the virtual logical address subspace are divided into a namespace array according to the redundancy mode of the storage array; a row of the logical address blocks in the namespace array is used as a stripe, and the namespace array is divided into multiple virtual logical address groups, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the storage array, and the virtual logical address group includes one to more stripes.

3. The cache management method of the storage array according to claim 2, characterized in that: The step of determining the target virtual logical address group to be stored in the storage array according to the activity level includes: The target cache data in the target virtual logical address group that needs to be stored in the storage array is determined according to the storage status.

4. The cache management method of the storage array according to claim 3, characterized in that: The storage status includes a read / write status flag bit corresponding to each logical address block in the virtual logical address group; The step of determining target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state includes: The cache data of the logical address block corresponding to the read-write status flag bit in the target virtual logical address group is in the write state is determined as the target cache data.

5. The cache management method of the storage array according to claim 4, characterized in that: The method further comprises: When writing the target cache data into the storage array, redundancy calculation is performed on the cache data in each logical address block in the stripe to obtain verification data and write it into the verification block in the stripe; and the read-write status flag corresponding to the verification block is set to the write status.

6. The cache management method of the storage array according to claim 4, characterized in that: The method further includes: updating the corresponding storage states respectively according to the read and write operations of the virtual logical address groups corresponding to each namespace in the cache, specifically including: If the data stored in the cache of the logical address block is first data, setting the read / write status flag corresponding to the logical address block to a write state, wherein the first data is write data sent by the remote host; If the data stored in the cache of the logical address block is second data, the read / write status flag corresponding to the logical address block is set to a read state; the second data is empty data or read data read from the storage array.

7. The cache management method of a storage array according to claim 4, characterized in that: The storage status includes a full flag bit corresponding to each virtual logical address group; The method further comprises: Determine whether each read / write status flag bit corresponding to each logical address block in the virtual logical address group is in the write state, and obtain the number of logical address blocks whose read / write status flag bit is in the write state; If the number of blocks is greater than a preset threshold, determining that the full flag corresponding to the virtual logical address group is in a full state; The method further includes: using the virtual logical address group corresponding to the full state of the full flag as the target virtual logical address group.

8. The cache management method of a storage array according to claim 1, characterized in that: The step of determining the target virtual logical address group to be stored in the storage array according to the activity level includes: Determining the virtual logical address group with a low activity level as the target virtual logical address group; And / or, when the cache space is full, the virtual logical address group at the middle activity level is determined as the target virtual logical address group.

9. The cache management method of a storage array according to claim 1, characterized in that: The storage state includes a number of activity factor flag bits corresponding to each virtual logical address group; The method further includes: updating the corresponding storage states respectively according to the read and write operation commands of the virtual logical address groups corresponding to each namespace in the cache, specifically including: According to the frequency of receiving the read and write operation commands for the virtual logical address group, the corresponding activity factor flag value is set.

10. The cache management method of the storage array according to claim 9, characterized in that: The step of setting the activity factor flag value corresponding to the virtual logical address group according to the frequency of receiving the read and write operation commands comprises: Counting objects according to the virtual logical address group according to a preset frequency and counting period; In the counting cycle, the activity factor flag value is updated according to a preset update rule based on whether the virtual logical address group receives a read or write operation command.

11. The cache management method of a storage array according to claim 10, characterized in that: The updating of the activity factor flag value according to a preset updating rule within the counting period and according to whether the virtual logical address group receives a read / write operation command includes: If the read / write operation command is not received within the counting period, the respective digits of the activity factor flag value are retrieved according to the set digit sequence, and the second state value is updated and written to the digit corresponding to the first state value; wherein, in the initial state, the values ​​of the respective digits of the activity factor flag value are all the first state values; If the read / write operation command is received within the counting cycle, the respective digits of the activity factor flag value are retrieved in the reverse order of the set digits, and the first state value is updated and written to the digit corresponding to the first second state value.

12. The cache management method of a storage array according to claim 11, characterized in that: The determining the activity level of cache data in the virtual logical address group according to the storage state corresponding to the virtual logical address group includes: If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the second state values, the activity level of the cache data in the virtual logical address group is determined to be a low activity level; If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the first state values, the activity level of the cache data in the virtual logical address group is determined to be a high activity level; Counting the number of digits of each digit of the activity factor flag value that are the number of digits of the first state value; If the number of digits is greater than a preset number, the activity level of the cache data in the virtual logical address group is determined to be an intermediate activity level.

13. The cache management method of a storage array according to any one of claims 1 to 12, characterized in that: The virtual logical address group is the granularity of the read and write operation commands; The storage state includes a number of lock flag bits equal to the number of groups of each virtual logical address group; The method further comprises: When operating the current virtual logical address group according to the read / write operation command, setting the lock flag bit corresponding to the current virtual logical address group to a lock state; Delaying the read and write operation commands accessing the virtual logical address group in the locked state.

14. The cache management method of a storage array according to claim 3, characterized in that: The step of determining the target virtual logical address group to be stored in the storage array according to the activity level includes: Determining a target logical address for storing the target cache data in the storage array according to the virtual logical address group and a preset logical address mapping relationship; The target cache data is written into the storage array according to the target logical address.

15. A cache management device for a storage array, characterized in that: include: Address group division module, activity level determination module and disk placement module; An address group division module, used for mapping the storage array into a virtual logical address space according to the namespace, and dividing the virtual logical address space into virtual logical address groups; An activity level determination module, configured to determine the activity level of cached data in the virtual logical address group according to a storage state corresponding to the virtual logical address group; The disk placement module is used to determine a target virtual logical address group that needs to be stored in the storage array according to the activity level.

16. A storage array controller, characterized in that: include: Redundancy module, storage interface control module, controller memory and non-volatile storage control module; The redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module and the controller memory; The storage interface control module is connected to the remote host for receiving and parsing the message data sent by the remote host to obtain the operation command, and transmits the operation command to the redundancy module after scheduling and managing the operation command based on the namespace; the non-volatile storage control module is connected to the storage array for mapping the controller memory to realize data interaction with the storage array in response to the data transmission request of the redundancy module; The redundancy module implements the cache management method of the storage array according to any one of claims 1-14.

17. A computer-readable storage medium, characterized in that: The computer program is stored therein, and when the computer program is executed on a processor, the cache management method of the storage array according to any one of claims 1 to 14 is implemented.

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