Memory access violation prediction method and system, terminal and storage medium

Abstract

The invention discloses a memory access violation prediction method and system, a terminal and a storage medium, and the method comprises the steps: obtaining a loading instruction, and decoding the loading instruction to obtain a target loading instruction; generating a target physical address according to the target loading instruction, obtaining a full connection entry, obtaining a violation distance of the target physical address in the full connection entry according to the target physical address, and obtaining a prediction storage instruction according to the target loading instruction and the violation distance; searching a storage instruction in a storage instruction queue according to the target physical address, taking the predicted storage instruction as a conflict storage instruction when the storage instruction which is not transmitted exists before the target loading instruction is searched, and storing the target loading instruction in a retransmission list; and after a target storage instruction corresponding to the conflict storage instruction is transmitted, writing back the target loading instruction in the retransmission list. According to the method, the memory access violation is predicted through the full-connection entry, so that the memory access violation is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of memory access violation prediction, and in particular to a memory access violation prediction method, system, terminal and storage medium. Background Art

[0002] In a superscalar processor, load instructions and store instructions can be executed out of order, but when the addresses of load and store instructions overlap, the load instruction should get the data of the store instruction first. If the load instruction is executed before the store instruction, an error will occur. This situation is called a memory access violation. At this time, the load instruction should get the result of the store instruction, but the store instruction has not been executed yet, so the instruction obtained by the load instruction is wrong; specifically, the load instruction needs to be executed first and then stored in a queue. When the store instruction is executed, it is found that there is a load instruction with the same address after the store instruction, but it has been written back, so the load instruction and the subsequent instructions need to be flushed.

[0003] At present, in order to prevent the occurrence of memory access violations, the out-of-order execution of storage and load instructions is usually prohibited directly, which will cause the storage instructions and load instructions to be executed completely sequentially, thereby reducing processor performance; or by recording multiple storage instructions that the load instruction depends on at one time, and suspending the issuance of these load instructions before issuing the storage instruction, but this method uses a direct mapping method, the table entry utilization rate is low, and multiple storage instructions are recorded at one time, resulting in a large area overhead.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] The main purpose of the present invention is to provide a memory access violation prediction method, system, terminal and computer-readable storage medium, aiming to solve the problem that in order to prevent the occurrence of memory access violations in the prior art, the method of directly prohibiting the out-of-order execution of storage and load instructions and the method of recording multiple storage instructions that the load instruction depends on at one time and suspending the issuance of these load instructions before issuing the storage instruction will lead to reduced processor performance or high resource consumption, thereby having certain limitations in practical applications.

[0006] To achieve the above object, the present invention provides a memory access violation prediction method, the memory access violation prediction method comprising the following steps: Obtaining a load instruction, and decoding the load instruction to obtain a target load instruction; Generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted store instruction according to the target load instruction and the violation distance; searching for a storage instruction in a storage instruction queue according to the target physical address, and when it is found that there is a storage instruction that has not been issued before the target load instruction, taking the predicted storage instruction as a conflicting storage instruction, and storing the target load instruction in a reissue list; After the target storage instruction corresponding to the conflicting storage instruction is issued, the target load instruction in the resend list is written back.

[0007] Optionally, before obtaining the fully connected entry, the step further includes: Acquire multiple pieces of historical memory access violation training information, wherein the historical memory access violation training information includes the physical address of the load instruction in each memory access violation, the position of the storage instruction carried in the load instruction, and the position of the storage instruction in the previous memory access violation corresponding to the load instruction; Obtaining a violation distance corresponding to each physical address according to all of the historical memory access violation training information; A fully connected structure is adopted to summarize all the physical addresses and corresponding violation distances, and the fully connected entry is obtained according to the number of memory access violation transmissions of each physical address, and the counter of each information in the fully connected entry is initialized.

[0008] Optionally, the acquiring the load instruction and decoding the load instruction to obtain the target load instruction specifically includes: Obtaining a load instruction, and decoding the load instruction according to a decoding unit; The decoded instructions are input into the reservation station for buffering, and when the preset requirements are met, the corresponding target load instructions are output from the reservation station.

[0009] Optionally, generating a target physical address according to the target load instruction specifically includes: Generate a virtual address according to the target load instruction; According to the virtual address, a conversion module is accessed, and a target physical address is returned according to the conversion module.

[0010] Optionally, searching for a storage instruction in a storage instruction queue according to the target physical address further includes: When the address and data of the storage instruction are found, the target load instruction is written back, and the number of the counter of the corresponding information in the fully connected entry is adjusted to be reduced by 1; When the address of the storage instruction found is transmitted but the data of the storage instruction is not found, the target load instruction is stored in the retransmission list. When the data of the storage instruction found is stored in the storage instruction queue, the target load instruction is written back and the number of the counter of the corresponding information in the fully connected entry is adjusted by 1.

[0011] Optionally, when it is found that there is a storage instruction that has not been issued before the target load instruction, the predicted storage instruction is used as a conflicting storage instruction, and the target load instruction is stored in a reissue list, and then the method further includes: Obtain a counter of corresponding information in the fully connected entry; The number of the counter of the corresponding information in the fully connected entry is increased by 1.

[0012] Optionally, the memory access violation prediction method further includes: At predetermined intervals, a counter of each piece of information in the full connection entry is obtained, and when the number of the counter is 0, the corresponding information is marked as invalid; The fully connected entry is updated according to the tag of each piece of information and the target algorithm.

[0013] In addition, to achieve the above-mentioned purpose, the present invention further provides a memory access violation prediction system, wherein the memory access violation prediction system comprises: An instruction acquisition module, used for acquiring a load instruction, and decoding the load instruction to obtain a target load instruction; A prediction module, configured to generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted storage instruction according to the target load instruction and the violation distance; A prediction and determination module, configured to search for a storage instruction in a storage instruction queue according to the target physical address, and when a storage instruction is found to be not issued before the target load instruction, use the predicted storage instruction as a conflicting storage instruction, and store the target load instruction in a retransmission list; The processing module is used for writing back the target load instruction in the resending list after the target storage instruction corresponding to the conflicting storage instruction is issued.

[0014] In addition, to achieve the above-mentioned purpose, the present invention also provides a terminal, wherein the terminal includes: a memory, a processor, and a memory access violation prediction program stored on the memory and executable on the processor, and when the memory access violation prediction program is executed by the processor, the steps of the memory access violation prediction method as described above are implemented.

[0015] In addition, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a memory access violation prediction program, and when the memory access violation prediction program is executed by a processor, the steps of the memory access violation prediction method as described above are implemented.

[0016] In the present invention, a load instruction is obtained, and the load instruction is decoded to obtain a target load instruction; a target physical address is generated according to the target load instruction, a fully connected entry is obtained, and a violation distance of the target physical address is obtained in the fully connected entry according to the target physical address, and a predicted storage instruction is obtained according to the target load instruction and the violation distance; a storage instruction is searched in a storage instruction queue according to the target physical address, and when a storage instruction is found before the target load instruction and is not issued, the predicted storage instruction is used as a conflicting storage instruction, and the target load instruction is stored in a retransmission list; after the target storage instruction corresponding to the conflicting storage instruction is issued, the target load instruction in the retransmission list is written back. The present invention does not need to prohibit all out-of-order executions, but generates a corresponding fully connected entry by recording a storage instruction and its corresponding violation distance, thereby avoiding redundant information of table entries, and adopts a fully connected method to improve the utilization rate of table entries, and uses a corresponding algorithm to replace infrequently used table entries, that is, it ensures that the area overhead of the fully connected entry is not too large, and enables it to accurately predict the existence of memory access violations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of a preferred embodiment of the memory access violation prediction method of the present invention; Figure 2 It is a schematic diagram of the processing flow of a load instruction in the memory access violation prediction method of the present invention; Figure 3 It is a schematic diagram of violation distance in the memory access violation prediction method of the present invention; Figure 4 is a structural diagram of a preferred embodiment of the memory access violation prediction system of the present invention; Figure 5 It is a structural diagram of a preferred embodiment of the terminal of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] In a superscalar processor, load instructions and store instructions can be executed out of order. However, when the addresses of load and store instructions overlap, the load instruction should first obtain the data of the store instruction. If the load instruction is executed before the store instruction, an error will occur. This situation is called a memory access violation. At this time, the load instruction should obtain the result of the store instruction, but the store instruction has not been executed yet, so the instruction obtained by the load instruction is wrong. Specifically, the load instruction needs to be executed first and then stored in a queue. When the store instruction is executed, it is found that there is a load instruction with the same address after the store instruction, but it has been written back. Then, the load instruction and the subsequent instructions need to be flushed. At present, in order to prevent the occurrence of memory access violations, the out-of-order execution of store and load instructions is usually directly prohibited, which will cause the store instruction and load instruction to be executed completely in sequence, thereby reducing the processor performance; or by recording multiple store instructions that the load instruction depends on at one time, and suspending the issuance of these load instructions before issuing the store instruction, but this method uses a direct mapping method, the table entry utilization rate is low, and multiple store instructions are recorded at one time, which has a large area overhead.

[0020] In response to one or more of the above problems, the present invention obtains a load instruction, decodes the load instruction to obtain a target load instruction; generates a target physical address according to the target load instruction, obtains a fully connected entry, obtains a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtains a predicted storage instruction according to the target load instruction and the violation distance; searches for a storage instruction in a storage instruction queue according to the target physical address, and when a storage instruction is found that has not been issued before the target load instruction, uses the predicted storage instruction as a conflicting storage instruction and stores the target load instruction in a retransmission list; and when the target storage instruction corresponding to the conflicting storage instruction is issued, writes back the target load instruction in the retransmission list.

[0021] The memory access violation prediction method described in the preferred embodiment of the present invention is as follows: Figure 1 As shown, the memory access violation prediction method includes the following steps: Step S10: Obtain a load instruction, and decode the load instruction to obtain a target load instruction.

[0022] Specifically, in the present invention, for a load instruction, the processing process is as follows: Figure 2As shown in the figure, Rename, i.e. instruction renaming module (Instruction Renaming), also known as register renaming (Register Renaming), is an important optimization technology in modern high-performance processors, which is used to solve the data dependency problem caused by instruction-level parallel execution, especially read-after-write (RAW) dependency; Dispatch, a decoding module, is used to send decoded instructions to different execution units or reservation stations, and the following Issue is the reservation station; Issue, i.e. reservation station (ReservationStation, RS), is a key component for optimizing instruction execution in modern superscalar and out-of-order execution processors, which acts as a buffer between instruction dispatch (dispatch) and execution, allowing instructions to be flexibly executed according to resource availability and data dependencies, rather than strictly following the original order in the program; the execution of load instructions is divided into 4 pipeline stages, namely loadUnit S0, loadUnit S1, loadUnit S2 and loadUnit S3. S3, its corresponding functions are described as follows: the initial stage (loadUnitS0), referred to as loadS0, generates a virtual address (vaddr), sends a virtual address request to DCache (data cache), and accesses TLB (a virtual address and physical address conversion module, which will return the physical address in the next shot); the first stage (loadUnitS1), referred to as loadS1, receives the physical address returned by TLB, which is sent to DCache and sent to storeQueue (storage instruction queue) to find data; the second stage (loadUnitS2), referred to as loadS2, obtains the data returned by DCache and the previous data returned by storeQueue. If the data is returned at the same time, the previous data returned by storeQueue will be used first; the third stage (loadUnitS3), referred to as loadS3, writes back the data of the load instruction.

[0023] It should be further explained that, in the present invention, a load instruction, that is, a load instruction, is used to place the value of a specified memory address in a specified register. A store instruction, that is, a store instruction, is used to place the data of a specified register at a specified memory address. storeQueue (storage instruction queue) is a circular queue that stores all store instructions in the processor in program order, including the addresses and data of committed and uncommitted store instructions; when a load instruction sends a request to storeQueue to obtain the forward data, the load instruction will carry the physical address and search the storeQueue for the data of the store instruction with the same address that is before the load instruction in program order and returned. RAWQueue (Read After Write Queue), that is, read-after-write queue, is used to store the load instructions that have been written back. The load instructions in RAWQueue have the following characteristics: when writing back, the physical address of the store instructions before the load instruction is unknown, because if the store instructions before the load instruction have the same address as the load instruction, then the load instruction should get the data of the store instruction corresponding to the same address; but at this time, the load instruction has already obtained the physical address requested by Dcache and is ready to write back, so all these load instructions with Raw (Read after write) risks are put into RAWQueue, and when the store instruction comes, this queue can be queried. At the same time, the store instruction will query RAWQueue, which stores the write-back load instructions. The store instruction checks whether there are load instructions in RAWQueue with the same address and the program order after the store. If so, it means that the execution result of this load instruction is wrong, so a flush is needed. The flush object is this wrong load instruction and all instructions after this load instruction. When a flush is about to be initiated, a memory access violation occurs, called a store-load violation.

[0024] Further, the acquiring of the load instruction and decoding the load instruction to obtain the target load instruction specifically includes: Obtaining a load instruction, and decoding the load instruction according to a decoding unit; The decoded instructions are input into the reservation station for buffering, and when the preset requirements are met, the corresponding target load instructions are output from the reservation station.

[0025] Specifically, Figure 2As shown, in the present invention, for each load instruction, the load instruction is decoded according to the decoding unit; the instruction obtained after decoding is input into the reservation station for buffering, and when the preset requirements are met, that is, when the cache station determines that it can be output, the corresponding target load instruction is output from the reservation station.

[0026] Step S20, generating a target physical address according to the target load instruction, obtaining a fully connected entry, obtaining a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtaining a predicted store instruction according to the target load instruction and the violation distance.

[0027] Furthermore, the target load instruction generates a target physical address, specifically including: Generate a virtual address according to the target load instruction; According to the virtual address, a conversion module is accessed, and a target physical address is returned according to the conversion module.

[0028] Specifically, Figure 2 As shown, after obtaining the target load instruction through the reservation station, a virtual address is generated, and the target physical address is obtained in the first stage, and then it can be predicted through the prediction module (new MDP) to obtain the predicted storage instruction.

[0029] Furthermore, in the present invention, before predicting the corresponding memory access violation through the fully connected entry, the fully connected entry is trained accordingly.

[0030] Furthermore, before obtaining the fully connected entry, the step further includes: Acquire multiple pieces of historical memory access violation training information, wherein the historical memory access violation training information includes the physical address of the load instruction in each memory access violation, the position of the storage instruction carried in the load instruction, and the position of the storage instruction in the previous memory access violation corresponding to the load instruction; Obtaining a violation distance corresponding to each physical address according to all of the historical memory access violation training information; A fully connected structure is adopted to summarize all the physical addresses and corresponding violation distances, and the fully connected entry is obtained according to the number of memory access violation transmissions of each physical address, and the counter of each information in the fully connected entry is initialized.

[0031] Specifically, in the training process of the fully connected entry, when the RAWQueue initiates a flush, it indicates that a memory access violation has occurred. This is the training information required for the fully connected entry, that is, training through multiple historical memory access violation training information. The training information includes: loadPc, loadPc is the PC of the load instruction, that is, the physical address of the load instruction; ld_stPtr, the StorePtr of the store instruction next to the load instruction, that is, the location of the storage instruction carried in the load instruction; stPtr, the StorePtr of the store instruction, that is, the location of the storage instruction in the previous memory access violation corresponding to the load instruction.

[0032] After obtaining these training information, they will be processed to obtain the following information: distance, that is, the violation distance, represented by ld_stPtr-stPtr; loadPc, that is, the physical address of the load instruction, and loadPc will be hashed and folded to 10 bits. There are many folding methods in the present invention. In one embodiment, loadPc (no matter how many bits) is grouped into groups of 10 bits from back to front. For example, for a 45-bit pc, it will be divided into 5 groups, the last group is 5 bits, and then the xth (x belongs to 0 to 9) bit of each group is XORed.

[0033] Among them, Figure 3 The figure shows how to obtain the violation distance. The distance between the load instruction that causes the violation and the store instruction that causes the violation is expressed as the number of store instructions between the previous store instruction of the load instruction and the violation store distance, that is, the number of store instructions that include the load instruction itself. Figure 3 In the embodiment shown in , the distance between the previous store instruction of the load instruction in which the violation occurs and the store instruction in which the violation occurs is 3, so the distance is 3.

[0034] After that, foldPc and distance will be updated to the fully connected entry, and cnt (counter) will be set to all 1s, the total is 3. When the storeQueue sends information about violation prediction failure, the cnt of the corresponding information in the fully connected entry will be reduced by 1. When the storeQueue sends information about violation prediction success, the cnt of the corresponding information in the fully connected entry will be increased by 1. When the cnt corresponding to a piece of information is 0, this item is invalid.

[0035] In addition, in the present invention, the fully connected entries are constructed using a fully connected structure, with a total of 32 pieces of information. When the table is full or reaches a predetermined time, the plru algorithm, i.e., the target algorithm, is used to replace the information that is not frequently used. The tag corresponding to each piece of information is 10 bits, and the tag can be obtained by hash mapping using loadPc. The distance depends on the size of the processor. Assuming that the size of the processor storeQueue is 64, the distance requires log 2 (64) = 6 bits.

[0036] Furthermore, after the full connection entry is obtained through training, the violation distance of the target physical address can be obtained in the full connection entry according to the target physical address, and the predicted storage instruction can be obtained according to the target load instruction and the violation distance.

[0037] Step S30, searching for a storage instruction in a storage instruction queue according to the target physical address, and when it is found that there is a storage instruction that has not been issued before the target load instruction, treating the predicted storage instruction as a conflicting storage instruction, and storing the target load instruction in a retransmission list.

[0038] Specifically, in the present invention, searching for a storage instruction in the storage instruction queue according to the target physical address does not only include the case where the address of the found storage instruction has not been completely transmitted.

[0039] Correspondingly, searching for a storage instruction in a storage instruction queue according to the target physical address, and then further comprising: When the address and data of the storage instruction are found, the target load instruction is written back, and the number of the counter of the corresponding information in the fully connected entry is adjusted to be reduced by 1; When the address of the storage instruction found is transmitted but the data of the storage instruction is not found, the target load instruction is stored in the retransmission list. When the data of the storage instruction found is stored in the storage instruction queue, the target load instruction is written back and the number of the counter of the corresponding information in the fully connected entry is adjusted by 1.

[0040] Specifically, from the instruction execution process, after the instruction obtains the target physical address in the loadS0 stage, it uses the fully connected entry to obtain the predicted store instruction and returns to the loadS1 stage in the next beat. The target load instruction obtains the virtual address in the loadS0 stage, and then obtains the corresponding physical address, and initiates a forward query request to the storeQueue, that is, searches for the store instruction in the store instruction queue according to the target physical address. The store instruction is divided into two parts: address (store addr, sta) and data (store data, std); if the data of the store instruction with the same address as the load instruction is obtained in the storeQueue at this time, this load instruction can be written back; if the same sta is found in the storeQueue at this time, but the corresponding std has not arrived, the load instruction cannot be written back, and the load instruction will enter the replayQueue (replay list) to wait for this store instruction; if the storeQueue finds that there is a store instruction in front of the load instruction whose sta has not been completed, since the address of the store instruction is unknown, the store instruction that the load instruction needs to wait for at this time is the predicted store instruction as the store instruction that the load instruction needs to wait for. This load instruction will wait for the predicted store instruction to be issued and then be reissued from the replayQueue for execution. If the predicted conflicting store instruction is correct, the load instruction should be able to be written back normally after the second reissue. If the predicted conflicting store instruction is incorrect, then the issuance of this load instruction wastes pipeline bandwidth.

[0041] When it is found that there is a storage instruction that has not been issued before the target load instruction, the predicted storage instruction is used as a conflicting storage instruction, and the target load instruction is stored in a reissue list, and then the method further includes: Obtain a counter of corresponding information in the fully connected entry; The number of the counter of the corresponding information in the fully connected entry is increased by 1.

[0042] The full connection entry is updated in the above manner, that is, the counter of each piece of information in the full connection entry is obtained at predetermined intervals, and when the number of the counter is 0, the corresponding information is marked as invalid; The fully connected entry is updated according to the tag of each piece of information and the target algorithm.

[0043] Step S40: After the target storage instruction corresponding to the conflicting storage instruction is issued, the target load instruction in the resend list is written back.

[0044] Specifically, Figure 2As shown, when it is found that there is a corresponding storage instruction that will cause a memory access violation after the corresponding target load instruction, it is necessary to wait until the corresponding storage instruction is issued before writing back the corresponding target load instruction.

[0045] The present invention obtains a load instruction, decodes the load instruction to obtain a target load instruction; generates a target physical address according to the target load instruction, obtains a fully connected entry, obtains the violation distance of the target physical address in the fully connected entry according to the target physical address, and obtains a predicted storage instruction according to the target load instruction and the violation distance; searches for a storage instruction in a storage instruction queue according to the target physical address, and when a storage instruction is found to be not issued before the target load instruction, uses the predicted storage instruction as a conflicting storage instruction, and stores the target load instruction in a retransmission list; when the target storage instruction corresponding to the conflicting storage instruction is issued, writes back the target load instruction in the retransmission list. The present invention does not need to prohibit all out-of-order executions, but generates a corresponding fully connected entry by recording a storage instruction and its corresponding violation distance, thereby avoiding redundant information of table entries, and adopts a fully connected method to improve the utilization rate of table entries, and uses a corresponding algorithm to replace infrequently used table entries, which ensures that the area overhead of the fully connected entry is not too large, and enables it to accurately predict the existence of memory access violations.

[0046] Furthermore, if Figure 4 As shown, based on the above memory access violation prediction method, the present invention also provides a memory access violation prediction system accordingly, wherein the memory access violation prediction system includes: The instruction acquisition module 41 is used to acquire a load instruction and decode the load instruction to obtain a target load instruction; A prediction module 42, configured to generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted store instruction according to the target load instruction and the violation distance; A prediction and determination module 43, configured to search for a storage instruction in a storage instruction queue according to the target physical address, and when a storage instruction is found to be not issued before the target load instruction, use the predicted storage instruction as a conflicting storage instruction, and store the target load instruction in a retransmission list; The processing module 44 is configured to write back the target load instruction in the resend list after the target store instruction corresponding to the conflicting store instruction is issued.

[0047] Furthermore, if Figure 5As shown, based on the above-mentioned memory access violation prediction method and system, the present invention also provides a terminal accordingly, and the terminal includes a processor 10, a memory 20 and a display 30. Figure 5 Only some components of the terminal are shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0048] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal. In other embodiments, the memory 20 may also be an external storage device of the terminal, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal. Further, the memory 20 may also include both an internal storage unit of the terminal and an external storage device. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In one embodiment, a memory access violation prediction program 40 is stored on the memory 20, and the memory access violation prediction program 40 can be executed by the processor 10, thereby realizing the memory access violation prediction method of the present invention.

[0049] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run the program code stored in the memory 20 or process data, such as executing the memory access violation prediction method.

[0050] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 30 is used to display information on the terminal and to display a visual user interface.

[0051] In one embodiment, when the processor 10 executes the memory access violation prediction program 40 in the memory 20 , the steps of the above memory access violation prediction method are implemented.

[0052] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a memory access violation prediction program, and when the memory access violation prediction program is executed by a processor, the following steps are implemented: Obtaining a load instruction, and decoding the load instruction to obtain a target load instruction; Generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted store instruction according to the target load instruction and the violation distance; searching for a storage instruction in a storage instruction queue according to the target physical address, and when it is found that there is a storage instruction that has not been issued before the target load instruction, taking the predicted storage instruction as a conflicting storage instruction, and storing the target load instruction in a reissue list; After the target storage instruction corresponding to the conflicting storage instruction is issued, the target load instruction in the resend list is written back.

[0053] Wherein, before obtaining the full connection entry, the method further includes: Acquire multiple pieces of historical memory access violation training information, wherein the historical memory access violation training information includes the physical address of the load instruction in each memory access violation, the position of the storage instruction carried in the load instruction, and the position of the storage instruction in the previous memory access violation corresponding to the load instruction; Obtaining a violation distance corresponding to each physical address according to all of the historical memory access violation training information; A fully connected structure is adopted to summarize all the physical addresses and corresponding violation distances, and the fully connected entry is obtained according to the number of memory access violation transmissions of each physical address, and the counter of each information in the fully connected entry is initialized.

[0054] The step of acquiring the load instruction and decoding the load instruction to obtain the target load instruction specifically includes: Obtaining a load instruction, and decoding the load instruction according to a decoding unit; The decoded instructions are input into the reservation station for buffering, and when the preset requirements are met, the corresponding target load instructions are output from the reservation station.

[0055] The step of generating a target physical address according to the target load instruction specifically includes: Generate a virtual address according to the target load instruction; According to the virtual address, a conversion module is accessed, and a target physical address is returned according to the conversion module.

[0056] The step of searching for a storage instruction in a storage instruction queue according to the target physical address further includes: When the address and data of the storage instruction are found, the target load instruction is written back, and the number of the counter of the corresponding information in the fully connected entry is adjusted to be reduced by 1; When the address of the storage instruction found is transmitted but the data of the storage instruction is not found, the target load instruction is stored in the retransmission list. When the data of the storage instruction found is stored in the storage instruction queue, the target load instruction is written back and the number of the counter of the corresponding information in the fully connected entry is adjusted by 1.

[0057] When it is found that there is a storage instruction that has not been issued before the target load instruction, the predicted storage instruction is used as a conflicting storage instruction, and the target load instruction is stored in a retransmission list, and then the method further includes: Obtain a counter of corresponding information in the fully connected entry; The number of the counter of the corresponding information in the fully connected entry is increased by 1.

[0058] Wherein, the memory access violation prediction method further includes: At predetermined intervals, a counter of each piece of information in the full connection entry is obtained, and when the number of the counter is 0, the corresponding information is marked as invalid; The fully connected entry is updated according to the tag of each piece of information and the target algorithm.

[0059] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or terminal including the element.

[0060] Of course, those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware (such as a processor, a controller, etc.) through a computer program, and the program can be stored in a computer-readable storage medium that can be read by a computer, and the program can include the processes of the above-mentioned method embodiments when executed. The computer-readable storage medium can be a memory, a disk, an optical disk, etc.

[0061] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A memory access violation prediction method, characterized in that: The memory access violation prediction method comprises: Obtaining a load instruction, and decoding the load instruction to obtain a target load instruction; Generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted store instruction according to the target load instruction and the violation distance; searching for a storage instruction in a storage instruction queue according to the target physical address, and when it is found that there is a storage instruction that has not been issued before the target load instruction, taking the predicted storage instruction as a conflicting storage instruction, and storing the target load instruction in a reissue list; After the target storage instruction corresponding to the conflicting storage instruction is issued, the target load instruction in the resend list is written back.

2. The memory access violation prediction method according to claim 1, characterized in that: Before obtaining the fully connected entry, the following step is also included: Acquire multiple pieces of historical memory access violation training information, wherein the historical memory access violation training information includes the physical address of the load instruction in each memory access violation, the position of the storage instruction carried in the load instruction, and the position of the storage instruction in the previous memory access violation corresponding to the load instruction; Obtaining a violation distance corresponding to each physical address according to all of the historical memory access violation training information; A fully connected structure is adopted to summarize all the physical addresses and corresponding violation distances, and the fully connected entry is obtained according to the number of memory access violation transmissions of each physical address, and the counter of each information in the fully connected entry is initialized.

3. The memory access violation prediction method according to claim 1, characterized in that: The acquiring of the load instruction and decoding the load instruction to obtain the target load instruction specifically includes: Obtaining a load instruction, and decoding the load instruction according to a decoding unit; The decoded instructions are input into the reservation station for buffering, and when the preset requirements are met, the corresponding target load instructions are output from the reservation station.

4. The memory access violation prediction method according to claim 1, characterized in that: Generating a target physical address according to the target load instruction specifically includes: Generate a virtual address according to the target load instruction; According to the virtual address, a conversion module is accessed, and a target physical address is returned according to the conversion module.

5. The memory access violation prediction method according to claim 2, characterized in that: The step of searching for a storage instruction in a storage instruction queue according to the target physical address further comprises: When the address and data of the storage instruction are found, the target load instruction is written back, and the number of the counter of the corresponding information in the fully connected entry is adjusted to be reduced by 1; When the address of the storage instruction found is transmitted but the data of the storage instruction is not found, the target load instruction is stored in the retransmission list. When the data of the storage instruction found is stored in the storage instruction queue, the target load instruction is written back and the number of the counter of the corresponding information in the fully connected entry is adjusted by 1.

6. The memory access violation prediction method according to claim 2, characterized in that: When it is found that there is a storage instruction that has not been issued before the target load instruction, the predicted storage instruction is used as a conflicting storage instruction, and the target load instruction is stored in a reissue list, and then the method further includes: Obtain a counter of corresponding information in the fully connected entry; The number of the counter of the corresponding information in the fully connected entry is increased by 1.

7. The memory access violation prediction method according to claim 2, characterized in that: The memory access violation prediction method further includes: At predetermined intervals, a counter of each piece of information in the full connection entry is obtained, and when the number of the counter is 0, the corresponding information is marked as invalid; The fully connected entry is updated according to the tag of each piece of information and the target algorithm.

8. A memory access violation prediction system, characterized in that: The memory access violation prediction system comprises: An instruction acquisition module, used for acquiring a load instruction, and decoding the load instruction to obtain a target load instruction; A prediction module, configured to generate a target physical address according to the target load instruction, obtain a fully connected entry, obtain a violation distance of the target physical address in the fully connected entry according to the target physical address, and obtain a predicted storage instruction according to the target load instruction and the violation distance; A prediction and determination module, configured to search for a storage instruction in a storage instruction queue according to the target physical address, and when a storage instruction is found to be not issued before the target load instruction, use the predicted storage instruction as a conflicting storage instruction, and store the target load instruction in a retransmission list; The processing module is used for writing back the target load instruction in the resending list after the target storage instruction corresponding to the conflicting storage instruction is issued.

9. A terminal, characterized in that: The terminal includes: a memory, a processor, and a memory access violation prediction program stored in the memory and executable on the processor. When the memory access violation prediction program is executed by the processor, the steps of the memory access violation prediction method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a memory access violation prediction program, and when the memory access violation prediction program is executed by a processor, the steps of the memory access violation prediction method according to any one of claims 1 to 7 are implemented.

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