Data processing method and device under ARM architecture and electronic equipment
By dynamically creating multiple data processing threads and assigning sub-computing tasks under the ARM architecture, the problem of difficulty in achieving parallel computing in multifunctional data testing systems is solved, and efficient data processing and simplified processing are achieved.
Patent Information
- Application Number
- CN202411650152.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-28
AI Technical Summary
The multifunctional data testing system in the prior art is difficult to achieve the same ability to perform parallel computing on data as DSP, while meeting the requirements of improving processing efficiency and simplifying processing processes.
By dynamically creating multiple data processing threads under the ARM architecture, each thread includes an external system communication thread, a monitoring thread and a data processing thread, a corresponding thread is created based on the number of registers and the number of external systems, and sub-operation tasks are assigned to each thread, and processed through a preset thread operation algorithm, and finally summarize the final target processing results of the pending data elements.
It realizes the parallel processing of data through multiple data processing threads under the ARM architecture, so that the ARM architecture can achieve the same parallel computing capabilities as DSP, while improving processing efficiency and simplifying processing processes.
Smart Images
Figure CN119536944A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital circuit processing technology, and in particular to a data processing method, device and electronic equipment under an ARM architecture. Background Art
[0002] With the development of data acquisition technology and microprocessor technology, in order to meet the growing market demand, the development of multifunctional data testing systems will gradually move towards miniaturization and intelligence. In order to meet the needs of different industries or different production environments, the multifunctional data testing system needs to meet the requirements of being easy to carry and more convenient to use, which also makes the multifunctional data testing system more miniaturized. In addition, the functions of the multifunctional data testing system are also constantly improving. It is not only for data collection, but also for data analysis and processing, intelligent generation of data reports, and real-time monitoring of data accuracy. All functions do not require manual data processing. The intelligence of the multifunctional data testing system makes data collection more efficient. However, the multifunctional data testing system in the prior art has the problem that it is difficult to achieve the same ability to perform parallel operations on data as DSP while meeting the requirements of improving processing efficiency and simplifying the processing process. Summary of the invention
[0003] The present invention provides a data processing device under ARM architecture to solve the problem that the multifunctional data test system in the prior art is difficult to realize the same ability of parallel computing on data as DSP while meeting the requirements of improving processing efficiency and simplifying processing process.
[0004] In order to achieve the above object, the present invention is implemented by the following technical solutions:
[0005] In a first aspect, the present invention provides a data processing method under an ARM architecture, which is applied to the ARM architecture, wherein the ARM architecture includes a plurality of registers, and the method includes:
[0006] S1: Determine the number of the registers, and then dynamically create a one-to-one external system communication thread for each external system according to the number of registers and the number of external systems that currently need to be collected, and each data processing thread includes an external system communication thread, a monitoring thread and a data processing thread;
[0007] S2: Assign a corresponding sub-computation task to each data processing thread;
[0008] S3: Performing computation on each sub-computing task according to the corresponding preset thread computing algorithm to obtain a sub-processing result corresponding to each data processing thread;
[0009] S4: Determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
[0010] Optionally, the S1 includes:
[0011] According to the second digit of the register in the ARM architecture, the threshold number is determined; the number of registers is determined to be greater than or equal to the threshold number; then according to the number of external systems that currently need to be collected, a one-to-one external system communication thread and a data processing monitoring thread are dynamically created for each external system, and the data processing monitoring thread dynamically adjusts the number of data processing threads according to the detected data accumulation status. The external system communication thread is responsible for receiving external system data and sending internal system data, and the data processing thread is responsible for identifying and parsing external system data and framing internal system data; when the data processing monitoring thread polls, it detects whether there is a data processing thread with an empty data cache area, and destroys it if it exists.
[0012] Optionally, allocating a corresponding sub-computing task to each data processing thread includes: obtaining the sub-computing task corresponding to each data processing thread according to the number of data elements to be processed and a preset thread computing algorithm.
[0013] Optionally, obtaining the sub-computation task corresponding to each data processing thread according to the number of data elements to be processed and a preset thread operation algorithm includes:
[0014] The external system communication thread is responsible for receiving external system data and sending internal system data, and the data processing thread is responsible for identifying and parsing external system data and framing internal system data; when the external system has data input, the external system communication thread automatically receives and processes the data; when the internal system data needs to be sent outward, a data sending buffer is established, and the external system communication thread sends it when polling;
[0015] The data processing monitoring thread corresponds to the external system communication thread one by one. The number of data processing threads under the data processing monitoring thread changes dynamically according to the communication commands received from the external system. When the thread is polled, it is detected whether there is a data processing thread with an empty data cache area, and if so, it is destroyed;
[0016] The data processing thread pre-processes the data transmitted by the data processing scheduling thread according to a predetermined protocol, discards unqualified data, and stores data that meets the protocol in a data buffer area waiting for thread polling processing.
[0017] Optionally, determining the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads includes:
[0018] The sub-processing results corresponding to each of the data processing threads are aggregated according to a preset sub-thread aggregation algorithm to determine the final target processing result corresponding to the data element to be processed.
[0019] Optionally, the registers in the ARM architecture are NEON units storing the same data type.
[0020] In a second aspect, the present application provides a data processing device under an ARM architecture, which is applied to the ARM architecture. The ARM architecture includes a plurality of registers. The device includes:
[0021] A first determining module, used to determine the number of the registers;
[0022] A second determination module, used to create an operation algorithm according to the number of registers and preset threads, and determine a plurality of data processing threads for the data elements to be processed;
[0023] An allocation module is used to allocate a corresponding sub-computation task to each data processing thread;
[0024] The first processing module is used to perform operation processing on each sub-operation task according to the corresponding preset thread operation algorithm to obtain a sub-processing result corresponding to each data processing thread;
[0025] The second processing module is used to determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
[0026] In a third aspect, the present application provides an electronic device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the data processing method under the ARM architecture as described in the first aspect.
[0027] Beneficial effects:
[0028] The present application provides a data processing method under the ARM architecture, which determines multiple data processing threads according to the number of registers and the preset thread creation algorithm, and assigns a corresponding sub-operation task to each data processing thread; performs operation processing on the sub-operation task according to the preset thread operation algorithm to obtain the sub-processing result corresponding to the data processing thread; and determines the final target processing result corresponding to the data element to be processed. In this way, it is possible to process the data elements to be processed in parallel through multiple data processing threads under the ARM architecture, so that the ARM architecture can achieve the same ability of parallel operation on data as DSP, while also improving processing efficiency and simplifying the processing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A flowchart of a data processing method under an ARM architecture according to a preferred embodiment of the present invention;
[0030] Figure 2 It is a block diagram of a multifunctional data testing system based on ARM according to a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0031] The technical solution of the present invention is described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0032] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate quantity restrictions, but indicate the existence of at least one. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship also changes accordingly.
[0033] See also Figure 1 The present application provides a data processing method under an ARM architecture, which is applied to the ARM architecture. The ARM architecture includes a plurality of registers. The method includes:
[0034] S1: Determine the number of the registers, and then dynamically create a one-to-one external system communication thread for each external system according to the number of registers and the number of external systems that currently need to be collected, and each data processing thread includes an external system communication thread, a monitoring thread and a data processing thread;
[0035] S2: Assign a corresponding sub-computation task to each data processing thread;
[0036] S3: Performing computation on each sub-computing task according to the corresponding preset thread computing algorithm to obtain a sub-processing result corresponding to each data processing thread;
[0037] S4: Determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
[0038] The above-mentioned data processing method under the ARM architecture realizes the ability to process the data elements to be processed in parallel through multiple data processing threads under the ARM architecture, so that the ARM architecture can not only realize the same ability of parallel data calculation as DSP, but also improve the processing efficiency and simplify the processing process.
[0039] Optionally, the S1 includes:
[0040] According to the second digit of the register in the ARM architecture, the threshold number is determined; the number of registers is determined to be greater than or equal to the threshold number; then according to the number of external systems that currently need to be collected, a one-to-one external system communication thread and a data processing monitoring thread are dynamically created for each external system, and the data processing monitoring thread dynamically adjusts the number of data processing threads according to the detected data accumulation status. The external system communication thread is responsible for receiving external system data and sending internal system data, and the data processing thread is responsible for identifying and parsing external system data and framing internal system data; when the data processing monitoring thread polls, it detects whether there is a data processing thread with an empty data cache area, and destroys it if it exists.
[0041] Determining the number of the registers to be a value greater than or equal to the threshold number ensures the compatibility of the acquisition objects and the data acquisition speed, and on the other hand also saves computer resources and ensures the stability of the system.
[0042] Optionally, allocating a corresponding sub-computing task to each data processing thread includes:
[0043] The sub-computation tasks corresponding to each data processing thread are obtained according to the number of data elements to be processed and the preset thread operation algorithm. When data is input to the external system, the external system communication thread automatically receives and processes the data; when the internal system data needs to be sent outward, a data sending buffer is established, and the external system communication thread sends it when polling. The number of data processing threads under the data processing monitoring thread changes dynamically according to the communication data received from the external system. When the thread polls, it detects whether there is a data processing thread with an empty data buffer, and destroys it if it exists. The data processing thread pre-processes the data transmitted by the data processing scheduling thread according to the predetermined protocol, discards unqualified data, and stores data that meets the protocol in the data buffer waiting for thread polling processing.
[0044] Optionally, determining the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads includes:
[0045] The sub-processing results corresponding to each of the data processing threads are aggregated according to a preset sub-thread aggregation algorithm to determine the final target processing result corresponding to the data element to be processed.
[0046] The present invention can dynamically create a one-to-one external system communication thread for each external system according to the number of external systems currently requiring data collection, and can automatically add a data processing thread according to the data accumulation in the data cache area to help improve data processing efficiency; on the one hand, it ensures the compatibility of the collection objects and the data collection speed, and on the other hand, it also saves computer resources and ensures the stability of the system.
[0047] In one example, the data processing method under the ARM architecture can be applied to Figure 2 The multifunctional data test system based on ARM is shown. The multifunctional data test system designs the hardware circuit of the data acquisition and monitoring system around the selected ARM chip. The design of the hardware circuit needs to be combined with the modules actually required by the data acquisition and monitoring system.
[0048] Reference Figure 2 ,The data acquisition monitoring system is designed around the selected ARM chip and RS422 communication chip, and the hardware circuit of the data acquisition monitoring system is designed. The design of the hardware circuit needs to be combined with the modules actually needed by the data acquisition monitoring system. According to the design requirements of this article, in terms of the hardware circuit, the entire system has the following four parts: ARM-based processor peripheral circuit, RS422-based communication circuit, storage module circuit and output module circuit.
[0049] The present application also provides a data processing device under an ARM architecture, which is applied to the ARM architecture. The ARM architecture includes a plurality of registers. The device includes:
[0050] A first determining module, used to determine the number of the data processing threads;
[0051] A second determination module, used to create an operation algorithm according to the number of registers and preset threads, and determine a plurality of data processing threads for the data elements to be processed;
[0052] An allocation module is used to allocate a corresponding sub-computation task to each data processing thread;
[0053] The first processing module is used to perform operation processing on each sub-operation task according to the corresponding preset thread operation algorithm to obtain a sub-processing result corresponding to each data processing thread;
[0054] The second processing module is used to determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
[0055] The data processing device under the ARM architecture can implement various embodiments of the data processing method under the above-mentioned ARM architecture and achieve the same beneficial effects, which will not be described in detail here.
[0056] The present application also provides an electronic device, including: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the data processing method under the ARM architecture as described above.
[0057] The electronic device can implement various embodiments of the data processing method under the above-mentioned ARM architecture and can achieve the same beneficial effects, which will not be described in detail here.
[0058] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.
Claims
1. A data processing method under an ARM architecture, applied to the ARM architecture, wherein the ARM architecture includes a plurality of registers, characterized in that: The method comprises: S1: Determine the number of the registers, and then dynamically create a one-to-one external system communication thread for each external system according to the number of registers and the number of external systems that currently need to be collected, and each data processing thread includes an external system communication thread, a monitoring thread and a data processing thread; S2: Assign a corresponding sub-computation task to each data processing thread; S3: Performing computation on each sub-computing task according to the corresponding preset thread computing algorithm to obtain a sub-processing result corresponding to each data processing thread; S4: Determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
2. The data processing method under the ARM architecture according to claim 1, characterized in that: The S1 includes: According to the second digit of the register in the ARM architecture, the threshold number is determined; the number of registers is determined to be greater than or equal to the threshold number; then according to the number of external systems that currently need to be collected, a one-to-one external system communication thread and a data processing monitoring thread are dynamically created for each external system, and the data processing monitoring thread dynamically adjusts the number of data processing threads according to the detected data accumulation status. The external system communication thread is responsible for receiving external system data and sending internal system data, and the data processing thread is responsible for identifying and parsing external system data and framing internal system data; when the data processing monitoring thread polls, it detects whether there is a data processing thread with an empty data cache area, and destroys it if it exists.
3. The data processing method under the ARM architecture according to claim 1, characterized in that: The allocating a corresponding sub-operation task to each data processing thread includes: obtaining the sub-operation task corresponding to each data processing thread according to the number of data elements to be processed and a preset thread operation algorithm.
4. The data processing method under ARM architecture according to claim 3, characterized in that: The obtaining of the sub-computation tasks corresponding to each data processing thread according to the number of data elements to be processed and the preset thread operation algorithm includes: The external system communication thread is responsible for receiving external system data and sending internal system data, and the data processing thread is responsible for identifying and parsing external system data and framing internal system data; when the external system has data input, the external system communication thread automatically receives and processes the data; when the internal system data needs to be sent outward, a data sending buffer is established, and the external system communication thread sends it when polling; The data processing monitoring thread corresponds to the external system communication thread one by one. The number of data processing threads under the data processing monitoring thread changes dynamically according to the communication commands received from the external system. When the thread is polled, it is detected whether there is a data processing thread with an empty data cache area, and if so, it is destroyed; The data processing thread pre-processes the data transmitted by the data processing scheduling thread according to a predetermined protocol, discards unqualified data, and stores data that meets the protocol in a data buffer area waiting for thread polling processing.
5. The data processing method under the ARM architecture according to claim 1, characterized in that: The determining the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads includes: The sub-processing results corresponding to each of the data processing threads are aggregated according to a preset sub-thread aggregation algorithm to determine the final target processing result corresponding to the data element to be processed.
6. The data processing method under the ARM architecture according to claim 1, characterized in that: The registers in the ARM architecture are NEON units storing the same data type.
7. A data processing device under ARM architecture, applied to ARM architecture, wherein the ARM architecture includes a plurality of registers, characterized in that: The device comprises: A first determining module, used to determine the number of the registers; The second determination module creates multiple data processing threads for determining the data elements to be processed according to the number of registers and the number of external systems currently to be collected, and the number of data processing threads changes dynamically with the communication commands received from the external systems. The working process is as follows: (1) Initializing and starting the data processing monitoring thread according to the number of the registers and the number of external systems currently to be collected; (2) establishing a data buffer area in the data processing monitoring thread for caching communication data from the external system communication thread and corresponding external system communication parameters; (3) Determine whether the data buffer area in the current data processing monitoring thread is empty. If it is empty, the current monitoring thread sleeps for 5ms and goes to step (3). If it is not empty, go to step (4); (4) judging whether there is a corresponding data processing thread according to the communication address and command of the external system currently received, if so, proceeding to step (6); if not, proceeding to step (5); (5) Create and start the data processing thread corresponding to the newly received external system command, and pass the currently received parameters and commands to the corresponding data processing thread, set the data processing monitoring thread to sleep for 5ms, and go to step (3); (6) Determine whether the data accumulation of the currently running data processing thread exceeds the limit value. If so, go to step (7); if not, go to step (8); (7) Dynamically create and start a new data processing thread, and go to step (8); (8) The currently received external system communication data and the corresponding external system communication parameters are transmitted to the corresponding data processing thread; An allocation module is used to allocate a corresponding sub-computation task to each data processing thread; The first processing module is used to perform operation processing on each sub-operation task according to the corresponding preset thread operation algorithm to obtain a sub-processing result corresponding to each data processing thread; The second processing module is used to determine the final target processing result corresponding to the data element to be processed based on the sub-processing results corresponding to each of the data processing threads.
8. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the data processing method under the ARM architecture as described in any one of claims 1-6.