Sensing, storing and computing integrated macro-cell circuit, sensing, storing and computing integrated macro-cell system and digital-to-analog conversion method

Abstract

The invention discloses a sensing, storing and computing integrated macro-cell circuit, a sensing, storing and computing integrated macro-cell system and a digital-to-analog conversion method. The digital-to-analog conversion method comprises the following steps: setting a weight coefficient; writing weight signals into the analog storage and calculation unit through an iSC bus according to the weight coefficient, wherein each bit of the digital signal corresponds to one weight signal; the tag module reads the digital signal from the iSC bus and sequentially obtains each bit of the digital signal; carrying out digital-to-analog conversion calculation according to a formula of DREGn * weight signals; and after all bits of the digital signal are converted and calculated, the conversion result corresponding to each bit of digital signal is accumulated to obtain an analog signal, so that the analog domain signal and the digital domain signal are efficiently and parallelly converted.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits and signal processing, and in particular to a sensing-storage-computing integrated macro unit circuit, system and digital-to-analog conversion method. Background Art

[0002] With the development of the industrial Internet, higher requirements are placed on video acquisition and processing technology. In traditional visual application systems, image sensors collect image information, convert optical signals into electrical signals, and convert them into digital signals after digital-to-analog conversion. The image data is then processed by the image signal processing unit, and finally output to the processor in the system through a special video interface, which then performs data analysis and makes corresponding controls and operations. In the field of laser ranging, distance measurement sensors also use the principle of image sensors to collect image information. Laser sensors emit laser beams and receive reflected signals, measure reflection time to calculate distance, and convert the measurement results into digital signals.

[0003] In applications such as image processing and laser ranging, Figure 1 As shown, the sensing, storage and computing integrated chip realizes efficient and low-power data processing by integrating sensing, storage and computing functions. Among them, in the middle is the processing macro unit (PE) 1 array, which is closely arranged together in the form of an array of PEs, such as a 1024*1024 scale. Because each PE includes a sensing, storage and computing basic unit, all PEs in the PE array can process the data in each unit in parallel at the same time. This method is also often called single instruction multiple data mode, namely SIMD, which is more common in GPUs. Row control modules 5 and column control modules 6 are designed in the horizontal and vertical directions of the PE array respectively. The row control module 5 is used to select rows and related controls for the PE array, and the corresponding column mode control module is used to select columns and related controls for the PE array, as well as data readout selection. The periphery of the PE array also includes a peripheral digital module 4, an INS bus 41, a peripheral analog module 3, and an interface module 7.

[0004] like Figure 2 As shown, the PE unit includes a sensing unit (SU), an analog signal operator operation unit (AOP), an analog storage unit (AREG BANK), a digital storage unit (DREG BANK), a tag module (TAG), and an adjacent PE communication unit (adjacentIF). The analog storage unit includes several analog registers AREG0, AREG1..., and the analog register itself is also an operation unit. Similarly, the digital storage unit includes several digital registers DREG0, DREG1..., and the digital registers can perform logical operations in addition to storing digital signals. The output of the tag unit is used as a judgment signal to control whether the current PE executes the current SIMD instruction.

[0005] To convert conventional digital signals to analog signals, a special DAC chip or DAC circuit is needed to realize the conversion. For image data in vision chips, the serial transmission through DAC chips or circuits brings extremely low efficiency problems, high latency and high power consumption problems caused by data handling. Especially for sensing and storage chips, there are analog signal operation and storage units and digital signal operation and storage units in PE. When the signals interact or flow in the analog domain and the digital domain, they face great problems. Either a DAC circuit is designed in PE, but it brings problems of circuit area and power consumption. Or a special DAC circuit is designed in the chip, and the data in PE is converted serially through this DAC, which brings efficiency problems, data flow delays, and power consumption problems. Summary of the invention

[0006] The present invention proposes a sensing-storage-computing integrated macro unit circuit, system and digital-to-analog conversion method, which can utilize existing PE resources and realize the principle of digital-to-analog conversion through a control method, thereby realizing a method of parallelizing digital domain to analog domain signal conversion, which is in line with the characteristics of the SIMD sensing-storage-computing chip, and can perform parallel digital-to-analog signal conversion at the entire pixel level or single PE level, so that analog domain signals and digital domain signals can be efficiently converted in parallel.

[0007] The present invention provides a digital-to-analog conversion method for a sensing-storage-computing integrated macro unit circuit, comprising the steps of: Set weight coefficient; The weight signal is written to the analog storage unit according to the weight coefficient through the iSC bus, and each bit of the digital signal corresponds to a weight signal; The tag module reads the digital signal from the iSC bus, obtains each bit of the digital signal in turn and performs digital-to-analog conversion calculations. The formula is: DREGn*weight signal; After all bit conversion calculations of the digital signal are completed, the calculation results corresponding to each bit of the digital signal are accumulated to obtain an analog signal.

[0008] A sensing, storage and computing integrated macro unit circuit, comprising: iSC bus is used to connect various modules and transmit perception signals and operation signals between modules; INS bus, used to connect various modules; The first control module is used to set the weight coefficient corresponding to each bit of the digital signal, and write the weight signal to the analog storage unit according to the weight coefficient through the iSC bus; A digital storage and calculation unit includes a plurality of digital registers for simultaneously performing digital data storage and data calculation, each digital register storing one bit of digital signal; The analog storage and calculation unit includes a plurality of analog registers for simultaneously performing analog data storage and data calculation, wherein the analog storage and calculation unit includes a read register and a result register. The read register is used to store a weight signal, and the result register is used to store a digital-to-analog conversion result. The tag module is used to read the digital signal from the iSC bus, and judge each bit of the digital signal in turn. When it is not 0, the weight signal is retained or read out, otherwise the weight signal is rewritten or not read; The second control module is used to accumulate the weight signals read from the analog storage unit read register and store them in the result register of the analog storage unit after all the bits of a digital signal are judged.

[0009] The present invention also provides a circuit system, comprising: a sensing-storage-computing integrated macro unit circuit, wherein the plurality of sensing-storage-computing integrated macro unit circuits are arranged in an array structure.

[0010] The present invention utilizes existing PE resources and implements the principle of DAC through a control method, thereby realizing a method for parallelizing digital domain to analog domain signal conversion, which conforms to the characteristics of the SIMD system chip of sensing, storage and computing, and realizes DAC conversion for the entire PE array at the same time.

[0011] The present invention utilizes existing components to convert digital signals into current signals and stores them in AREG in PE. It realizes a method of parallelizing digital domain to analog domain signal conversion without adding special conversion circuits. This method does not require a dedicated DAC circuit and utilizes the existing circuit of PE to realize the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, has high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a schematic diagram of the architecture of a sensing, storage and computing integrated circuit system; Figure 2 It is a schematic diagram of the architecture of a sensing, storage and computing integrated macro unit circuit; Figure 3 It is a schematic diagram of AREG BANK operation of a sensing, storage and computing integrated macro unit circuit; Figure 4 This is another AREG BANK operation diagram of the integrated sensing, storage and computing macro unit circuit; Figure 5 This is another AREG BANK operation diagram of the integrated sensing, storage and computing macro unit circuit; Figure 6 It is a schematic diagram of the DREG BANK structure of a sensing, storage and computing integrated macro unit circuit; Figure 7 It is a schematic diagram of an SRAM circuit of a sensing, storage and computing integrated macro unit circuit; Figure 8 It is a TAG circuit schematic diagram of a sensing, storage and computing integrated macro unit circuit; Fig. 9 It is a schematic diagram of a digital-to-analog conversion method of a sensing-storage-computing integrated macro unit circuit according to an embodiment of the present application; Fig.10 This is a flow chart of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro unit circuit according to the first embodiment of the present application; Fig.11 yes Fig.10 Schematic diagram of a digital-to-analog conversion method for a sensing-storage-computing-in-one macro-unit circuit according to an embodiment; Fig.12 This is a flow chart of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro unit circuit according to a second embodiment of the present application; Fig.13 yes Fig.12 Schematic diagram of a digital-to-analog conversion method for a sensing-storage-computing-in-one macro-unit circuit according to an embodiment; Fig.14 is a flow chart of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro unit circuit according to a third embodiment of the present application; Fig.15 yes Fig.14 Schematic diagram of a digital-to-analog conversion method for a sensing-storage-computing-in-one macro-unit circuit according to an embodiment; Fig.16 It is a coding schematic diagram of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro unit circuit of the first embodiment of the present application; Fig.17 It is a schematic diagram of the correspondence between binary digital signals and analog signals of a sensing-storage-computing integrated macro unit circuit according to another embodiment of the present application; Fig.18 A coding diagram of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro-unit circuit according to a fourth embodiment of the present application; Fig.19 is a flow chart of a digital-to-analog conversion method of a sensing-storage-computing-in-one macro unit circuit according to a fourth embodiment of the present application; Fig. 20 yes Fig.19 Schematic diagram of a digital-to-analog conversion method for a sensing-storage-computing-in-one macro-unit circuit of an embodiment. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more explicit definition of the protection scope of the present invention. Obviously, the embodiments described in the present invention are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0015] In this application, the use of "or" means "and / or" unless otherwise stated. Furthermore, the use of the term "comprising" and other forms such as "including" and "comprising" are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0016] The present invention provides a sensing-storage-computing integrated macro unit system, comprising a plurality of sensing-storage-computing integrated macro unit circuits arranged in an array. Figure 1 As shown, in this embodiment, the sensing-storage-computing integrated macro unit system is specifically designed in a sensing-storage integrated chip, with a processing macro unit (PE) array in the middle, which is closely arranged together in the form of an array by PE1, for example, a scale of 1024*1024. The internal structure of PE is described in detail with reference to the specific sensing-storage-computing integrated macro unit circuit and the embodiments of the sensing-storage-computing integrated macro unit circuit later. Here, only the overall architecture of the sensing-storage integrated macro unit system is described.

[0017] Because each PE includes a basic sensing, storage and computing unit, all PEs in the PE array can process the data in each unit in parallel at the same time. This method is also often called single instruction multiple data mode, or SIMD, which is more common in GPUs. Row control modules and column control modules are designed in the horizontal and vertical directions of the PE array respectively. The row control module is used to perform row selection and related control on the PE array, and the corresponding column mode control module is used to perform column selection and related control on the PE array, as well as data readout selection. Therefore, in addition to the PE array, the sensing and storage integrated circuit system also includes a digital-to-analog conversion unit (DAC) 2, a peripheral analog module 3, a peripheral digital module 4, a row control module 5, a column control module 6, an interface module 7, etc., and an INS bus 41 arranged on the periphery of the PE array.

[0018] In one embodiment, the sensing-storage-computing integrated macro unit system includes a plurality of sensing-storage-computing integrated macro unit circuits arranged in an array structure, and specifically may be a sensing-storage-computing integrated macro unit circuit of a distance measurement sensor, such as Figure 2As shown, the PE unit includes a perception unit SU, an analog signal operator operation unit AOP, an analog storage and calculation unit AREG BANK, a digital storage and calculation unit DREGBANK, a tag module TAG, an adjacent PE communication unit adjacent IF, an iSC bus, and an INS bus. The above units and modules are all connected to the iSC bus and the INS bus. The iSC bus is used to transmit perception signals and operation signals, and the perception unit and the storage and calculation unit are both connected to the iSC bus; the INS bus is used to transmit instructions.

[0019] The analog storage and calculation unit is equipped with AREG BANK, which contains multiple analog registers AREG, which is the basic unit for storing and calculating analog signals in the PE analog domain. A group of AREG0, AREG1, AREG2...composes AREGBANK to achieve more powerful signal processing capabilities. Figure 3 , AREG0 read operation, reads out I0, AREG1 write operation, writes the current read out by AREG0 to this register, but AREG1 flows into I0, because the current has a direction, it is defined as -I0.

[0020] like Figure 4 As shown, AREG0 is read and I0 is read out. AREG1 is also read and I1 is read out to iSC BUS. AREG2 is in write state, so the write current should be I0+I1, which means addition operation is realized. If the current directions of I0 and I1 are different, subtraction operation is realized. If the same current is repeatedly added, integer multiplication operation is realized. Of course, a special multiplication circuit can also be designed.

[0021] like Figure 5 , AREG0 is read operation, I0 is read out, AREG1 and AREG2 are write operations at the same time, the current size written to each register AREG1 / 2 is I0 / 2, thus realizing integer division operation.

[0022] Several AREGs form an AREG BANK, such as 5 or 10. The number of AREGs is designed according to the application. Such a group of AREGs can realize a large amount of signal storage and addition, subtraction, multiplication and division operations, providing basic computing power for applying complex algorithms.

[0023] The present invention utilizes the above-mentioned AREG operation to realize the conversion from the PE digital domain to the analog domain, that is, converting the digital signal in the PE into the corresponding analog signal.

[0024] Specifically, the label module is used to read the digital signal from the iSC bus and judge each bit of the digital signal in turn. In one embodiment, the label module sets the label value according to each bit of the digital signal, and determines whether the current sense storage and calculation integrated macro unit circuit executes the instruction sent by the INS bus based on the stored label value. The first control module is used to set the weight signal corresponding to each bit of the digital signal, and write the weight signal to the analog storage and calculation unit according to the weight coefficient through the iSC bus, and each bit of the digital signal corresponds to a weight signal; the digital storage and calculation unit includes a plurality of digital registers for simultaneous digital data storage and data calculation, and each digital register stores a digital signal; the analog storage and calculation unit includes a plurality of analog registers for simultaneous analog data storage and data calculation, including a read register and a result register, the read register is used to store the weight signal, and the result register is used to store the digital-to-analog conversion result; the label module is used to read the digital signal from the iSC bus, judge each bit of the digital signal in turn, and when it is not 0, retain or read the weight signal, otherwise rewrite or do not read the weight signal; the second control module is used to accumulate the weight signal read from the analog storage and calculation unit read register after all bits of a digital signal are judged, and store it in the result register of the analog storage and calculation unit.

[0025] In one embodiment, the weight coefficient corresponding to each bit of the digital signal changes according to a linear function, increasing or decreasing by multiples.

[0026] In one embodiment, it further includes an encoding module for encoding the digital signal according to standard binary code.

[0027] In one embodiment, the weight signal and the analog signal are current values.

[0028] In one embodiment, the analog storage and calculation unit includes three read registers, one result register, and one cache register; it also includes a processing unit, which judges each bit of the digital signal in turn. When it is not 0, the analog storage and calculation unit is turned on, and the weight signal is read out and the result signal stored in the result register is added and then written into the cache register; the result of the cache register is written into the result register.

[0029] In one embodiment, the analog storage and calculation unit includes three read registers and one result register; it also includes a processing unit, which judges each bit of the digital signal in turn, and when it is 0, rewrites the weight signal to 0, and adds the weight signals corresponding to each bit of the digital signal and stores them in the result register.

[0030] In one embodiment, the analog storage and calculation unit includes 1 cache register, 1 result register, and 1 weight signal register; the external DAC unit sends the weight signal to the weight signal register in sequence; each bit of the digital signal is judged in sequence, and when it is not 0, the analog storage and calculation unit is turned on, and the weight signal and the result signal of the result register are read out and added and written into the cache register; the result of the cache register is written into the result register.

[0031] In one embodiment, the analog storage unit includes three read registers and one result register; one of the read registers is used to store a sign bit.

[0032] In one embodiment, the sensing unit, analog storage and computing unit, digital storage and computing unit, iSC bus, INS bus and tag module are integrated on the same substrate.

[0033] In one embodiment, the analog storage and computing unit includes multiple analog registers, and the analog registers also serve as analog computing units. By connecting the multiple analog storage and computing units to the same iSC bus for read and write operations, analog signals are directly added, subtracted, multiplied, and divided in the analog registers.

[0034] In one embodiment, the digital storage and calculation unit includes a plurality of digital registers, and the digital registers have both storage and logic operation capabilities.

[0035] In one embodiment, a DREG BANK is provided in the digital storage and computing unit, and the DREG BANK includes multiple digital registers, a digital read bus iSC RD data bus and a digital write bus iSC WR data bus, and the digital register is a digital register DREG; multiple digital registers DREG are connected in parallel between the digital read bus iSC RD data bus (DBUS) and the digital write bus iSCWR data bus, wherein the input end IN of the digital register DREG is connected to the iSC WR data bus, and the output end OUT of the digital register DREG is connected to the iSC RD data bus, and a multiplexer MUX is also connected between the digital read bus iSC RD data bus and the digital write bus iSC WR data bus, and the digital read bus iSC RD data bus of the digital register DREG is also connected to the iSC bus through a switch.

[0036] In one embodiment, the digital register is implemented using Flash, which further includes: multiple FLASH memories, a read-write control circuit, a read data iSCRD data bus and a multiplexer MUX, wherein the input end IN of the FLASH memory is connected to the read-write control circuit, the output end of the FLASH is connected in parallel to the iSCRD data bus, and a multiplexer MUX is connected between the iSCRD data bus and the read-write control circuit.

[0037] In one embodiment, the tag module includes a comparator circuit (COMP) inside. Figure 8 , used to compare the size of two signals.

[0038] In one embodiment, the analog storage and calculation unit includes a plurality of analog registers AREG0, AREG1, etc. The analog registers themselves are also calculation units. Signals can be added, subtracted, multiplied, and divided through the analog registers. For example, five registers can be designed to meet basic calculation requirements. Similarly, the digital storage and calculation unit is provided with a DREG BANK, which includes a plurality of digital signal memories DREG, and each digital register can store one bit of data.

[0039] The digital register is implemented by 3T DRAM, or 6T DRAM, or SRAM. 6T SRAM is used as the circuit for storing digital signals DREG in PE. Compared with the previous DRAM, the storage is more stable, but the unit size of DREG will be increased. Data is written through the MWR tube, WR is valid, and IN inputs a valid signal to complete the write operation. Correspondingly, data is read out through the MRD tube, RD is valid, and OUT outputs a valid signal to complete the read operation. In this embodiment, the specific RAM reference Figure 7 .

[0040] In one embodiment, in addition to performing conventional operations through analog registers, the analog signal operator operation unit AOP can independently design efficient special operators to implement special operations, such as square operations, log operations, square root operations, etc., according to the particularity of the application scenario.

[0041] In one embodiment, the tag value of the tag unit TAG is used as a judgment signal to control whether the current PE executes the current SIMD instruction. For example, when the TAG tag value is 0, the current PE does not execute the current instruction, such as closing the read and write registers, that is, the read data is 0. On the contrary, when the TAG tag value is 1, the current PE executes the current instruction, such as reading the weight signal. The communication interface between adjacent PEs is also designed in the PE, such as Figure 2The adjacent PE communication unit (Adjacent IF) can provide the current PE with information about the eight PEs surrounding the current PE. The above module units are connected together through a specially designed sense-storage-computation bus iSC bus. The analog signal can be a voltage or a current signal. In addition to the iSC bus, a global instruction bus INS bus is also designed in the PE to perform overall operation control on each functional module in the PE. Because the INS bus of each PE is controlled by the same global signal, storage-computation integration (SIMD) is achieved in this way. The circuit structure of the tag unit TAG is shown in the figure. Figure 8 shown.

[0042] In a circuit system embodiment of the present invention, it includes multiple of the above-mentioned sensing-storage-computing integrated macro unit circuits, and the multiple sensing-storage-computing integrated macro unit circuits are arranged in an array structure; and also includes: a DAC unit arranged outside the array structure.

[0043] The present invention also provides a circuit system, comprising: a plurality of sensing-storage-computing-in-one macro-unit circuits are arranged in an array structure.

[0044] The following is further explained in conjunction with the sensing, storage and computing integrated macro unit circuit and its digital-to-analog conversion method.

[0045] refer to Fig. 9 The digital-to-analog conversion method of the sensing, storage and computing integrated macro unit circuit in this embodiment includes the following steps: setting a weight coefficient; writing a weight signal to the analog storage and computing unit through the iSC bus, and each bit of the digital signal corresponds to a weight signal; the label module reads the digital signal from the iSC bus, obtains each bit of the digital signal in turn, from MSB to LSB, or from LSB to MSB, and performs digital-to-analog conversion calculation, the formula is:; after the conversion calculation of all bits of the digital signal is completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain the analog signal.

[0046] The present invention realizes the conversion from PE digital domain to analog domain, that is, converting the digital signal in PE into the corresponding digital signal. The following example converts the digital signal of DREG in PE, for example, 3-bit precision, and in actual use, 5-bit precision or even higher 8-bit digital signal can be used, into an analog signal and stores it in the analog register AREG. The iSC bus transmission is adopted.

[0047] In one embodiment, a 3-bit digital signal is taken as an example. The digital signals of DREG0, DREG1, and DREG2 in DREG BANK are converted into analog current signals and stored in the result register AREG3 of AREG BANK. For example, in this embodiment, the current storage range of AREG is 0uA to 8uA, and the range of the current signal is 8uA, which is recorded as Ipp, which is the current range stored in the analog storage unit, that is, the difference between the maximum and the minimum. In this range, the digital value stored in DREG is mapped into the corresponding current signal and stored in AREG.

[0048] First, the analog signal of 1 / 2*Ipp needs to be stored in the read register AREG2, the analog signal of 1 / 4*Ipp needs to be stored in the read register AREG1, and the analog signal of 1 / 8*Ipp needs to be stored in the read register AREG0. The result register AREG3 is used to store the final analog signal result. In the initialization stage, the 0uA analog signal is stored in AREG3. Specifically, the current corresponding to the weight signal can be written to AREG by writing to the iSC bus, or AREG can read the weight signal of the iSC bus and calculate the analog signal of the corresponding current in the corresponding register.

[0049] Next, the binary digital signal to be converted is stored in DREG0, DREG1, and DREG2, where DREG2 stores the highest bit [2] of the 3-bit binary value, DREG1 stores the lowest bit [0] of the 3-bit binary value, and DREG0 stores the lowest bit [0] of the 3-bit binary value. Specifically, the digital signal to be converted can be written into DREG by writing via the iSC bus.

[0050] refer to Fig.11 By using the iSC bus, AREG0, AREG1, and AREG2 read the output current, and AREG3 writes the input current, the analog signal (Value) is calculated according to the binary weight relationship of the following formula DAC ):

[0051] k is the conversion precision. In this embodiment, it is 3 bits, k=3, which is specifically related to the converted digital signal encoding rule. n is the corresponding number of bits, and n takes values ​​of 0, 1, and 2. In other embodiments, the precision of the digital signal can also be adjusted. For example, k can take values ​​of 4 or 5, corresponding to the precision of 4 bits and 5 bits, and the corresponding n value range is from 0 to k-1.

[0052] Specifically in this embodiment: Value DAC = DREG2 * 2 2*(1 / 8*Ipp) + DREG1 * 2 1 * (1 / 8* Ipp) + DREG0 * 2 0 * (1 / 8* Ipp) =》Value DAC = DREG2 * (1 / 2*Ipp) + DREG1 * (1 / 4* Ipp) + DREG0 * (1 / 8*Ipp) =》Value DAC = DREG2 * I AREG2 + DREG1 * I AREG1 + DREG0 * I AREG0 The highest binary bit [2] represents 1 / 2*Ipp, the binary value [1] represents 1 / 4*Ipp, and the lowest binary bit [0] represents 1 / 8*Ipp. Add the analog signal current with the corresponding weight of 1 in the 3 bits to Value DAC (AREG3). I AREG Indicates the current of the corresponding register. Of course, in other embodiments, the current can also be converted into a voltage value.

[0053] Therefore, it is only necessary to operate according to the values ​​stored in DREG0, DREG1, and DREG2. In this embodiment, the values ​​in DREG0, DREG1, and DREG2 are read out in sequence. If DREG stores 1, then TAG = 1, perform the addition operation, and store the result in Value. DAC If DREG stores 0, then TAG = 0, and the PE does not perform the current global addition operation, that is, the AREG does not perform the read operation, Value DAC Keep the last calculation result. Specifically, in one embodiment, the reference signal input 1 / 2*VDD positive input terminal of TAG can be used to input the values ​​of DREG0, DREG1, and DREG2 in sequence through, for example, strobing. If DREG0 is 1, AREG0 performs a read operation, otherwise the PE does not perform the operation; similarly, if DREG1 is 1, AREG1 performs a read operation, otherwise the PE does not perform the operation; similarly, if DREG2 is 1, AREG2 performs a read operation, otherwise the PE does not perform the operation. In this way, a 3-bit digital signal requires three judgments and analog signal additions to complete the conversion, and so on, 5 bits require 5 times.

[0054] refer to Fig.16In one embodiment, the conversion is based on the binary system principle, proportional conversion, that is, linear conversion, and the weight coefficients are: 1 / 2, 1 / 4, 1 / 8. Specifically, the storage current range of AREG is 0uA to 8uA. The corresponding relationship between binary digital signals and analog signals is as follows: Fig.17 , which also shows the encoding of the digital-to-analog conversion method of the integrated sensing, storage and computing macro unit circuit.

[0055] In the first embodiment, reference Fig.10 and 8 , you can set the cache register Cache, add the conversion results of each AREGn to the Cache, and then store them in the result register AREG3. The conversion result of each digital signal is added to the result signal stored in the result register example and stored in the Cache, and then written from the Cache to the result register, and finally output by reading the value of the result register. Specifically, AREG4 can be used as a Cache.

[0056] In the second embodiment, reference Fig.12 and 10 , you do not need to set the Cache, and directly add the conversion results of each AREGn to AREG3 for output.

[0057] In the third embodiment, referring to Fig.14 and Fig.15 The weight coefficient can be written globally through the DAC outside the PE in the chip. The DAC can be 5-bit or higher precision to achieve more precise analog signal input. AREG1 is used to store weight data, AREG1 is used for write operation, and AREG0 is used as Cache, so that each digital signal passes through 1 AREG, such as AREG1 to convert the analog signal, and the converted signal is added and stored in Cache, that is, AREG0, and then stored in the result register AREG1. The conversion result of each digital signal is added to the result stored in the result register and stored in the Cache, and then written from the Cache to the result register, and finally output by reading the value of the result register AREG1.

[0058] In one embodiment, the DAC outside the PE may also directly write the current analog signal corresponding to the weight coefficient.

[0059] In one embodiment, the original signal can come from the SU unit, or be written into the PE from the outside of the chip, or from the digital storage unit DREG BANK, or the AOP unit, and then sent to the iSC bus. The TAG unit receives the digital signal from the iSC bus, and then compares it according to the size of the DREG digital signal to obtain the TAG value, and then reads and writes the AREGBANK according to the TAG value, thereby realizing the conversion of digital signals to analog signals. The operation results can be stored in the AREG of the PE and then output through the iSC bus to realize certain application functions.

[0060] All of the above data transmission and signal collection require INS command control. The INS bus connects the components in each PE. The INS can come from the system outside the chip, or it can be issued by the MCU module inside the chip, or the chip can generate an INS for specific applications itself.

[0061] In one embodiment, the storage current range of AREG is -8uA to 8uA, and the voltage output to the iSC bus will also change accordingly, from 0.2V to 0.9V.

[0062] Because the main circuit of the TAG module is the comparator circuit, the characteristics of the TAG comparator are used to realize the DAC function in the PE, that is, to realize the mutual conversion of the digital domain signal to the analog domain signal in the PE. Specifically, the iSC bus is connected to the positive end of the comparator in the TAG. The negative end of the comparator in the TAG inputs the reference signal, which is 1 / 2*VDD in this embodiment.

[0063] Specifically, the DREG BANK can send a digital signal to the iSC bus. The TAG includes a comparator circuit inside to compare the magnitude of the digital signal obtained from the iSC and the reference signal. Figure 8 As shown, the gate input signal A of the MOS tube M171, the gate input signal B of the MOS tube M172, and the drain of the MOS tube M172 are used as the output terminal. The comparator circuit is used to compare the sizes of the two signals. When A is smaller than B, the output of TAG will become 0, or the output terminal of the digital register DREG is input to the B terminal, and the reference signal voltage is input to the A terminal to determine whether the value of DREG exceeds the given reference signal voltage. If it exceeds, it becomes 0, and if it is lower, it becomes 1.

[0064] The sensing-storage-computing integrated macro unit circuit and the digital-to-analog conversion method of the present invention are further explained below in conjunction with a specific digital-to-analog conversion process. Example

[0065] In this embodiment, reference Fig.10 and Fig.11, the encoding rule of digital signal is standard binary code. The weight coefficient increases or decreases according to the multiple of linear function. Fig.10 As shown in the figure, the control process is controlled by instructions. The chip performs operations according to the instructions, and the entire PE array operates in SIMD mode. The specific operation process and steps of converting analog signals into digital signals are as follows: S10: Write weight signal to AREG; Each read register corresponds to a weight signal. In this embodiment, AREG0, AREG1, and AREG2 are used to store weight signals, so in this step, AREG0, AREG1, and AREG2 store a weight signal corresponding to a digital signal.

[0066] S20: Initialize the AREG result register to 0; In this embodiment, AREG3 is set as a result register to store the result RESULT after the digital-to-analog conversion.

[0067] S30: Set the tag value of TAG to 1; S40: read the digital signal of DREGn; Among them, the initial value of n is 2; k is the conversion precision, in this embodiment, it is 3 bits, k=3, n is the corresponding number of bits, n takes values ​​of 0, 1, and 2. In other embodiments, the precision of the digital signal can also be adjusted, for example, k can take values ​​of 4 or 5 corresponding to precision bits of 4 bits and 5 bits, and the corresponding value range of n is from 0 to k-1.

[0068] S50: The TAG unit compares the digital signal of DREG (n) currently read with the reference signal; S60: setting a tag value according to the comparison result, and determining whether the tag value is 1; If the TAG tag value = 1, continue to execute step S70, if the TAG tag value = 0, execute step S90; Specifically, the reference signal is 1 / 2*VDD, and if the comparison digital signal is greater than the reference signal, the TAG tag value is 1, otherwise it is 0. If the TAG tag value = 1, continue to execute step S70, and if the TAG tag value = 0, execute step S90.

[0069] S70: Cache=AREGn+RESULT; Specifically, the PE executes a global instruction and performs an AREG read operation, that is, reads the weight signal and adds (writes) it to the Cache. In this embodiment, AREG4 is set as the Cache.

[0070] Read the weight signal corresponding to the bit and perform digital-to-analog conversion:

[0071] Additive digital-to-analog conversion: Cache(AREG4) = + RESULT(AREG3) S80:AREG3=Cache; Specifically, the result of Cache (AREG4) is written into AREG3.

[0072] S90: determine n=0; Specifically, n is then determined. If n is not equal to 0, n=n-1 is executed and the process returns to step S30. Otherwise, the conversion ends.

[0073] Second embodiment In this embodiment, reference Fig.12 and Fig.13 The specific operation process and steps are as follows: S10: Write weight signal to AREG; Specifically, each bit of the digital signal corresponds to a weight signal. In this embodiment, AREG0, AREG1, and AREG2 are used to store the weight signal, so in this step, AREG0, AREG1, and AREG2 store a weight signal corresponding to one bit of the digital signal respectively.

[0074] S20: Initialize the AREG result register to 0; In this embodiment, AREG3 is a result register, AREG3=0.

[0075] S30: Set the tag value of TAG to 1; S40: read the digital signal of DREGn; Among them, the initial value of n is 2; S50: TAG unit compares the digital signal with the reference signal; Specifically, the TAG unit compares the digital signal of DREGn currently read with the reference signal.

[0076] S60: setting a tag value according to the comparison result, and determining whether the tag value is 1; Specifically, if the TAG tag value = 1, continue to execute step S80, if the TAG tag value = 0, execute step S70; The reference signal is 1 / 2*VDD, and if the comparison digital signal is greater than the reference signal, the TAG tag value is 1, otherwise it is 0. If the TAG tag value = 1, continue to execute step S80, and if the TAG tag value = 0, execute step S70.

[0077] S70:AREGn=RESULT=0; Specifically, the PE executes the global instruction and performs the AREGn read and write operation, that is, the weight signal is read and analog converted and then saved to AREGn; the weight signal corresponding to the bit is read and digital-to-analog converted:

[0078] S80: Then determine whether n is 0; Specifically, if n is not equal to 0, execute n=n-1 and return to step S30.

[0079] S90:; Specifically, if n=0, end the conversion and output Value DAC .

[0080] Third embodiment In this embodiment, reference Fig.14 and Fig.15 The present invention also provides another implementation method, which occupies fewer AREGs and uses only one AREG register to store the current conversion weight (Weight), such as Fig.14 As shown, IO_REG is used. This REG is a type of AREG and can be considered as an AREG register, but the input source is the chip I / O. That is, the conversion of each bit requires the chip IO to provide a corresponding analog signal, which can be a voltage or a current signal.

[0081] Includes steps: S10: Initialize AREG result register to 0; In this embodiment, AREG3 is used as the result register.

[0082] S20: Set the tag value of TAG to 1; S30: The external DAC unit sends a weight signal to iSC and writes IO_REG; Specifically, the external DAC unit sends a weight signal to the iSC. Every time a digital signal is read, the iSC sends a weight signal corresponding to the digital signal and writes IO_REG S40: read the digital signal of DREGn; Specifically, the initial value of n is 2; S50: TAG unit compares the digital signal with the reference signal; Specifically, the TAG unit compares the digital signal of DREGn currently read with the reference signal. If DREGn=1, the TAG tag value is 1, otherwise it is 0.

[0083] S60: setting a tag value according to the comparison result, and determining whether the tag value is 1; Specifically, if the TAG tag value = 1, continue to execute step S70, if the TAG tag value = 0, execute step S90; S70: Cache = IO_REG + RESULT; Specifically, the PE executes a global instruction and performs an AREG read operation, that is, reads the weight coefficient and adds the RESULT in the result register, and writes it into the Cache. In this embodiment, AREG0 is used as the Cache.

[0084] Read the weight signal corresponding to the bit and perform digital-to-analog conversion:

[0085] Additive digital-to-analog conversion: Cache(AREG0) = DREGn*IO_REG + RESULT(AREG3) S80:AREG3=Cache; Specifically, the addition result of the cache is written to AREG3 S90: Determine whether n is 0; Specifically, if n is not equal to 0, n=n-1 is executed and the process returns to step S20; if n=0, the conversion is terminated.

[0086] The former method will occupy more AREG registers, but since the weight value has been written into the corresponding AREG during the initialization phase, the execution efficiency will be relatively high.

[0087] The converted analog signal is stored in Value DAC AREG can be used to perform calculations in the analog domain, or output as the final calculation result to the chip's subsequent system to provide relevant analog signals for the subsequent system.

[0088] Fourth embodiment The similarities between this embodiment and the first embodiment are not repeated here, but the differences are as follows: The conversion range of the above embodiment is 0uA to 8uA. If there is a negative value in the conversion range, such as from -4uA to 4uA, a method is provided as follows: Fig.18 As shown, if you still use 3-bit precision, refer to Fig. 20, the high bit (3rd bit) is used as the sign bit, and the low 2 bits are used for the conversion principle described above. At this time, the Ipp is 4uA, not 8uA as described above. Fig.19 and Fig. 20 AREG2 stores -1*Ipp, i.e. -4uA. The operation of the lower two bits is exactly the same as that in the first embodiment. When it comes to the sign bit, when Sign bit=0, AREG2 participates in the operation, i.e. Cache = AREG2+RESULT, and then AREG3= Cache; when Sign bit=1, AREG2 does not participate in the operation, completing the current conversion, and n in the flowchart is 0 and 1.

[0089] The present invention provides a method for parallelizing digital domain to analog domain signal conversion in PE. This method does not require a dedicated DAC circuit and utilizes the existing circuit of PE to realize the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, has high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. To convert conventional digital signals to analog signals, a special DAC chip or DAC circuit is needed to realize the conversion. For traditional image sensors, the early single DAC has developed to column-level DAC, and then to the latest pixel-level DAC design, but this requires advanced process requirements. Because of the DAC design size limitation and DAC frequency characteristic requirements, the traditional data handling process results in high processing delay and high power consumption.

[0090] Especially for the sensing storage chip, there are analog signal operation and storage units and digital signal operation and storage units in the PE. When the signal interacts or flows in the analog domain and the digital domain, it faces great problems. Either a DAC circuit is designed in the PE, but it brings problems of circuit area and power consumption. Or a single DAC circuit is used for serial conversion, which brings efficiency problems, data flow delay, and power consumption problems.

[0091] The present invention does not require a dedicated DAC circuit, but utilizes the existing PE circuit to realize the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, has high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

[0092] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system including volatile and non-volatile memory and / or storage elements, at least one input device and at least one output device.

[0093] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner.

[0094] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0095] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including, but not limited to, floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0096] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0097] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0098] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0099] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A digital-to-analog conversion method for a sensing-storage-computing integrated macro unit circuit, characterized in that: Includes steps: Set weight coefficient; The weight signal is written to the analog storage unit according to the weight coefficient through the iSC bus, and each bit of the digital signal corresponds to a weight signal; The tag module reads the digital signal from the iSC bus, obtains each bit of the digital signal in turn and performs digital-to-analog conversion calculations. The formula is: DREGn*weight signal; After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal.

2. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The weight coefficient corresponding to each bit of the digital signal changes in sequence according to a linear function, increasing or decreasing in multiples.

3. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The encoding rule of digital signals is standard binary code.

4. The digital-to-analog conversion method of a sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The calculation formula of the weight signal is: Weight signal = weight coefficient * Ipp, Wherein Ipp represents the current range stored in the analog storage unit.

5. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 4, characterized in that: The calculation formula for the analog signal is: , k represents the conversion precision, which is an integer greater than 0, and n is the corresponding number of conversion bits, ranging from 0 to k-1.

6. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The method also includes the steps of setting a label value of the label module according to each bit of the digital signal, and determining whether the current sensing, storage and computing integrated macro unit circuit executes the instruction sent by the INS bus based on the stored label value.

7. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 6, characterized in that: After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal, including the steps of: Read each bit of the digital signal in sequence; Compare the reference signal with the current bit of the read digital signal; Set the label value according to the comparison result, and determine whether the label value is 1. If the label value is 1, read the corresponding weight signal and the current result signal in the result register, add them and write them into the cache register; write the result of the cache register into the result register; If the tag value is 0, no reading or writing is performed.

8. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 6, characterized in that: After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal, including the steps of: Read each bit of the digital signal in sequence; Compare the reference signal with the current bit of the read digital signal; Set the label value according to the comparison result, and determine whether the label value is 1. If the label value is 1, retain the weight signal of the corresponding bit; If the label value is 0, rewrite the weight signal of the corresponding bit to 0; After all bits of the digital signal are converted, the conversion results corresponding to each bit are added and stored in the result register.

9. A sensing-storage-computing integrated macro unit circuit using the digital-to-analog conversion method according to any one of claims 1 to 8, characterized in that: include: iSC bus is used to connect various modules and transmit perception signals and operation signals between modules; INS bus, used to connect various modules; The first control module is used to set the weight coefficient corresponding to each bit of the digital signal, and write the weight signal to the analog storage unit according to the weight coefficient through the iSC bus; A digital storage and calculation unit includes a plurality of digital registers for simultaneously performing digital data storage and data calculation, each digital register storing one bit of digital signal; The analog storage and calculation unit includes a plurality of analog registers for simultaneously performing analog data storage and data calculation, wherein the analog storage and calculation unit includes a read register and a result register. The read register is used to store a weight signal, and the result register is used to store a digital-to-analog conversion result. The tag module is used to read the digital signal from the iSC bus, and judge each bit of the digital signal in turn. When it is not 0, the weight signal is retained or read out, otherwise the weight signal is rewritten or not read; The second control module is used to accumulate the weight signals read from the analog storage unit read register and store them in the result register of the analog storage unit after all the bits of a digital signal are judged.

10. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The weight coefficient corresponding to each bit of the digital signal changes according to a linear function, increasing or decreasing by multiples.

11. The sensing-storage-computing-in-one macro-unit circuit according to claim 9 is characterized in that: The encoding module is used to encode the digital signal according to the standard binary code.

12. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The label module sets the label value according to each bit of the digital signal, and determines whether the current integrated sensing, storage and computing macro unit circuit executes the instructions sent by the INS bus based on the stored label value. If the instructions sent by the INS bus are executed, the analog storage and computing unit performs read and write operations.

13. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The analog storage and calculation unit includes 3 read registers, 1 result register, and 2 cache registers; It also includes a processing unit, which obtains each bit of the digital signal in turn. When it is not 0, the analog storage unit is turned on, the weight signal and the result signal stored in the result register are read out, and the weight signal and the result signal stored in the result register are added and written into the cache register; the result of the cache register is written into the result register.

14. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The analog storage and calculation unit includes 3 read registers and 2 result registers; It also includes a processing unit, which judges each bit of the digital signal in turn, and when it is 0, rewrites the weight signal to 0, and adds the weight signals corresponding to each bit of the digital signal and stores them in the result register.

15. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The analog storage and calculation unit includes 1 cache register, 1 result register, and 1 weight signal register; The external DAC unit sends the weight signal to the weight signal register in turn; Each bit of the digital signal is judged in turn. When it is not 0, the analog storage unit is turned on, the weight signal and the result signal of the result register are read out, and the result is written into the cache register after adding them; the result of the cache register is written into the result register.

16. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The analog storage and calculation unit includes 3 read registers and 1 result register; one of the read registers is used to store the sign bit.

17. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The analog storage and calculation unit, the digital storage and calculation unit, the iSC bus, the INS bus and the tag module are integrated on the same substrate.

18. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The digital register is implemented by using 3T DRAM, or 6T DRAM, or SRAM.

19. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The tag module includes a comparator circuit inside, which is used to compare the magnitudes of two signals.

20. The sensing-storage-computing-in-one macro-unit circuit according to claim 9, characterized in that: The weight signal and the analog signal are current values.

21. A circuit system, characterized in that: include: The sensing-storage-computing-in-one macro-unit circuit described in any one of claims 9-20, wherein the plurality of sensing-storage-computing-in-one macro-unit circuits are arranged in an array structure.

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