Verification method, verification device and storage medium

Abstract

The invention discloses a test vector verification method and device and a storage medium. The verification method comprises the steps of obtaining a simulation environment for verifying a to-be-tested chip; in the simulation environment, adding a multiplexer to a top layer port of the chip model to be tested; during the invalid level period of the enable signal of the multiplexer, providing a drive signal of a register transfer stage for the to-be-tested chip model through the multiplexer to obtain a test vector; providing a test vector for the to-be-tested chip model through the multiplexer in an effective level period of the enable signal of the multiplexer so as to obtain a simulation waveform; and comparing the simulation waveform with the expected waveform, judging whether the test vector is correct or not according to a comparison result, and judging that the test vector is correct under the condition that the simulation waveform is consistent with the expected waveform. By multiplexing the simulation environment, the consumption of time cost and labor cost for establishing the simulation environment is reduced, and the test efficiency of the wafer is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testing, and in particular to a test vector verification method, a verification device and a storage medium. Background Art

[0002] Wafer probing is an important part of the chip manufacturing process. After the wafer is manufactured, the voltage, current, timing and function of each die on the entire wafer are verified, so that defective dies can be found and eliminated before the chip is packaged, which helps to improve the quality and reliability of the final product.

[0003] The most direct and effective wafer testing method is to test the bare die through pre-designed test vectors. Test vectors are a preset signal sequence that can not only carry test instructions, but also serve as a carrier of test data to simulate various working conditions and states that chips encounter in actual applications. The specific operation of wafer testing through test vectors is to connect the pins of each bare die to the test machine through probes to input the test vector into the bare die and then observe the output of the bare die. If the output is consistent with expectations, then the bare die is judged to be normal.

[0004] Test vectors are usually designed and generated based on specific test requirements. However, due to the difficulty in unifying the configuration parameters of the test machine and the format of the test vectors, the test vectors must be verified in the early stages of wafer testing to ensure that the working state of the chip can be correctly simulated during the test, thereby improving the reliability of wafer testing.

[0005] In the prior art, to verify the test vector, the test machine needs to capture the output waveform of the bare chip and analyze the output waveform. If the output waveform is consistent with the expectation, the test vector can be determined to be correct; if the output waveform is inconsistent with the expectation, it is necessary to debug the test vector generation environment and / or the configuration parameters of the test machine according to the analysis results until the new test vector passes the verification. The round-trip debugging process takes a lot of time and energy; due to limited storage capacity, the test machine is often unable to capture and analyze all output waveforms, and cannot be intuitively traced back to a specific time node, which is very unfavorable to improve the efficiency of wafer testing. Summary of the invention

[0006] In view of the above problems, the purpose of the present application is to provide a test vector verification method, a verification device and a storage medium, which can shorten the verification time and improve the wafer testing efficiency.

[0007] According to one aspect of the present application, a method for verifying a test vector is provided, wherein the verification method comprises: obtaining a simulation environment for verifying a chip to be tested; in the simulation environment, adding a multiplexer to the top-level port of the chip model to be tested; during an invalid level of an enable signal of the multiplexer, providing a drive signal of a register transfer level to the chip model to be tested via the multiplexer to obtain a test vector; during an effective level of an enable signal of the multiplexer, providing the test vector to the chip model to be tested via the multiplexer to obtain a simulation waveform; comparing the simulation waveform with an expected waveform, and judging whether the test vector is correct based on the comparison result, wherein the test vector is judged to be correct if the simulation waveform is consistent with the expected waveform.

[0008] Optionally, after obtaining the test vector, the verification method also includes: defining an input drive component and an output monitoring component, the input drive component is used to drive the chip model to be tested, and the output monitoring component is used to monitor the simulation waveform output by the chip model to be tested; and defining a structure, which is used to store simulation data.

[0009] Optionally, the simulation data includes pin signals of the chip, test machine configuration parameters and a queue, the queue is used to store test data corresponding to the test vector, and the verification method also includes defining the queue in the structure.

[0010] Optionally, the method of providing the test vector to the chip model under test via the multiplexer includes: storing the test data in the queue; and driving the test data to the chip model under test in sequence according to a preset driving timing and flip type.

[0011] Optionally, the method for storing the test data includes: preprocessing the test vectors to obtain a text file of the test data; and reading and storing the text file in the queue.

[0012] Optionally, before preprocessing the test vector, the method for storing the test data further includes: writing a script file, wherein the script file is used to extract the test data from the test vector.

[0013] Optionally, the method for obtaining the test vector includes: monitoring the drive signal and the output signal of the chip model to be tested according to a first clock frequency; and obtaining the test vector based on the monitoring result, wherein the clock frequency of the output signal is a second clock frequency, and the first clock frequency is greater than the second clock frequency.

[0014] Optionally, the verification method also includes: determining that the test vector is wrong when the simulation waveform is different from the expected waveform; adjusting the first clock frequency according to the analysis result of the simulation waveform; generating a new test vector at the adjusted first clock frequency; and verifying the new test vector.

[0015] Optionally, the verification method also includes: determining that the test vector is wrong when the simulation waveform is different from the expected waveform; adjusting the clock frequency of the drive timing according to the analysis result of the simulation waveform, the first clock frequency is greater than the clock frequency of the drive timing; and verifying the test vector under the new drive timing.

[0016] Optionally, the chip includes a display driver chip, and the test data includes a level signal of the chip pin, an interface type, a read / write flag, a row delay, a row cycle number, etc.

[0017] Optionally, the configuration parameters of the test machine include a clock frequency of the driving timing.

[0018] According to another aspect of the present application, a verification device for a test vector is provided, wherein the verification device comprises: a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions stored in the memory to implement the verification method provided in any one of the above items.

[0019] According to a third aspect of the present application, a storage medium is provided, wherein a computer program is stored on the storage medium, and when the computer program is executed by a processor, the verification method as described in any one of the above items is implemented.

[0020] According to the verification method, verification device and storage medium of the test vector provided in the present application, by adding a multiplexer to the top-level port of the chip to be tested in the simulation environment to select the input signal of the chip model to be tested, the simulation verification of the register transfer level of the chip to be tested, the generation of test vectors and the simulation verification of test vectors can be realized through the same simulation environment. By reusing the simulation environment, the time cost and labor cost of setting up the simulation environment are reduced, which is conducive to improving the test efficiency of the wafer. At the same time, because the simulation environment has been used and verified many times in the verification stage of the chip, it has higher stability, the waveform it outputs is closer to the waveform of the real application scenario, and the reliability of the test results is higher.

[0021] Furthermore, by defining a structure in the simulation environment to store simulation data, when matching different test vector verification projects, only the simulation data in the structure needs to be adjusted without making other modifications to the simulation environment, which makes it more iterative.

[0022] Furthermore, by preprocessing the test data extracted from the test vector and converting it into a text file, the verification method provided by the present application can be compatible with test vector files of different formats and has better versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A schematic flow chart showing the test vector verification method of the present application is shown;

[0025] Figure 2A A schematic structural block diagram of a simulation environment for verifying a chip under test is shown;

[0026] Figure 2B Show Figure 2A The schematic structural block diagram after adding a multiplexer in the simulation environment;

[0027] Figure 3 A schematic flow chart showing the process of providing a test vector to a chip model to be tested;

[0028] Figure 4 A schematic structural block diagram of a test vector verification device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the following description of the present application, some specific details are described in detail. At the same time, in order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail, and those skilled in the art can fully understand the present application without the description of these known parts. For the sake of clarity, the various parts in the drawings are not necessarily drawn to scale.

[0030] In addition, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0031] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0032] In the following, a driver chip is shown as an example of a chip, but it should be understood that the verification method provided in the present application is applicable to various types of chips.

[0033] Figure 1 FIG. 1 is a schematic flow chart of the test vector verification method of the present application. Figure 1 As shown, the test vector verification method provided by the present application includes the following steps:

[0034] Step S11, obtaining a simulation environment for verifying the chip to be tested;

[0035] During the design and production process, in order to ensure that the chip can achieve the expected functions and performance and avoid possible design errors, the chip must be simulated and verified.

[0036] Figure 2A FIG. 1 shows a schematic structural diagram of a simulation environment for verifying a chip under test. Figure 2A As shown, when the chip under test is simulated and verified, the chip under test model is used as the device under test DUT10 (DUT, Device Under Test), the digital signal DS and the analog signal AS are driven to DUT10 and the output signal Output of DUT10 is monitored to realize the verification of the chip under test. Wherein, in the simulation environment 100, the digital signal DS is a register transfer level drive signal (i.e., RTL drive signal, RTL: Register Transfer Level, register transfer level), for example, including the valid level and invalid level of the reset port or MIPI interface, SPI interface and other interfaces on DUT10 (usually, the valid level represents the binary number 1, and the invalid level represents the binary number 0, but it should be understood that the present application is not limited to this). The analog signal AS is the power supply signal of DUT10. For example, for a display driver chip, the analog signal AS includes a gate turn-on voltage VGH and a gate turn-off voltage VGL.

[0037] Step S12, in the simulation environment, adding a multiplexer to the top-level port of the chip to be tested;

[0038] In this step, Figure 2AIn the simulation environment shown, a multiplexer 210 is added to the top-level port of the chip under test that receives the digital signal to obtain the simulation environment 200. The first input port of the multiplexer 210 is coupled to the test vector (pattern) generated in the subsequent step; the second input port is coupled to the RTL drive signal. The multiplexer provides the pattern or the RTL drive signal as a digital signal to the DUT10 according to the enable signal. For example, in some embodiments, during the valid level of the enable signal EN, the multiplexer drives the test vector to the chip under test model, and the simulation environment is used to simulate and verify the test vector; during the invalid level of the enable signal EN, the multiplexer drives the RTL drive signal to the chip under test model, and the simulation environment can be used to generate test vectors or simulate and verify the chip under test.

[0039] By reusing the simulation verification environment of the chip to be tested, the generation environment and verification environment of the test vector can be quickly built, and in the subsequent debugging process of the test vector, the simulation environment can be reused to generate test vectors or verify test vectors, which greatly shortens the time for building and modifying the simulation environment in the debugging process, is conducive to improving the verification efficiency of the test vector and reducing the verification cost. At the same time, since the simulation environment has been used and verified many times in the verification stage of the chip, the stability is higher, the waveform of its output is closer to the waveform of the real application scene, and the reliability of the test result is higher. In some embodiments, a simulation environment written in SystemVerilog is selected to facilitate modification. However, it should be understood that the present application is not limited to this, for example, a simulation environment written in other hardware description languages ​​such as Verilog can also be selected.

[0040] Step S13, during the invalid level period of the multiplexer enable signal, providing a drive signal of the register transfer level to the chip model to be tested via the multiplexer to obtain a test vector;

[0041] In this step, the RTL driving signal is provided to the DUT 10 as the digital signal DS via the multiplexer, and a test vector is obtained according to the monitoring result of the digital signal DS and the output signal Output of the DUT 10.

[0042] In some embodiments, the test vector is obtained by collecting the slow clock with the fast clock. Specifically, the monitoring frequency of the RTL drive signal and the output signal Output is the first clock frequency, the output frequency of DUT10 (the output frequency of Output) is the second clock frequency, and the first clock frequency is greater than the second clock frequency. The test vector obtained by collecting the slow clock with the fast clock can provide adjustment space for the driving timing of the test vector in the subsequent verification process, which is more conducive to the test vector passing the verification, thereby saving debugging time and improving wafer verification efficiency.

[0043] Step S14, providing a test vector to the chip model to be tested via the multiplexer during the period when the multiplexer enable signal is at an effective level;

[0044] An input driver component (driver) is defined in the simulation environment 200 to drive the DUT 10. Specifically, the test vector is used as an input stimulus of the DUT 10 in the simulation environment (the specific steps will be described below) to trigger the DUT 10 to execute a specific instruction.

[0045] Step S15, determining whether the test vector is correct;

[0046] In this step, the simulation waveform output by DUT10 is compared with the expected waveform to determine whether the test vector is correct. If the simulation waveform is consistent with the expected waveform, the test vector is determined to be correct and the verification ends; if the simulation waveform is different from the expected waveform, the test vector is determined to be wrong and step S16 and subsequent steps are continued.

[0047] Specifically, an output monitoring component (monitor) is defined in the simulation environment 200 for observing and recording the behavior of the DUT 10. The output of the DUT 10 is monitored by the output monitoring component, and the information is recorded to obtain a simulation waveform, so as to facilitate subsequent verification and analysis of the test vector.

[0048] By replacing the chip operation process of the test machine with a simulation environment, it is easier to obtain the simulation waveform corresponding to the test vector, which is helpful to shorten the time required for verification and debugging of the test vector in the early stage of wafer testing and improve the efficiency of wafer testing. The simulation waveform obtained by simulation can more conveniently and intuitively locate and debug the problems existing in the test vector, which is helpful to reduce the labor cost in the debugging process. In some embodiments, a label is added at a specific position during the generation of the test vector, so it is only necessary to compare the simulation waveform with the expected waveform at the corresponding time of the label to determine whether the verification is passed, avoiding the comparison of all simulation waveforms with the expected waveform, which can effectively improve the simulation efficiency.

[0049] Step S16, updating the test vector generation environment;

[0050] In this step, the error cause is determined in combination with the simulation waveform, and the test vector generation environment is adjusted according to the error cause. After step S16, the above steps S13 to S15 are repeated to generate and verify a new test vector.

[0051] In some embodiments, adjusting the test vector generation environment includes adjusting the first clock frequency (ie, adjusting the monitoring frequency of the RTL drive signal and the Output signal).

[0052] It should be noted that in this application, a structure is also defined in the simulation environment to store simulation data for simulating test vectors. These simulation data include chip pin signals (including reset signals, MIPI interface signals, MCU interface signals, and SPI interface signals, etc.), test machine configuration parameters (including interface configuration, test type, test vector drive timing, etc.) and queues (used to store test data corresponding to each test vector).

[0053] For example, the schematic syntax structure of the structure is as follows: typedef struct { logic RESX; logic MIPI1_CLKP_LP; logic MIPI1_CLKN_LP; logic MIPI2_CLKP_LP; logic MIPI2_CLKN_LP; … logic CSX ; logic DCX ; logic WRX; logic RDX ; logic [7:0] D ; … logic T_DELAY ; logic P_MODE ; ... } struct_inft;

[0054] However, it should be understood that the structures described in this application should not be limited thereto.

[0055] By storing simulation data in a structure, when verifying test vectors for different projects, it is only necessary to add / delete / modify the corresponding parameters in the structure without adjusting other settings in the simulation environment, so that the verification method provided by this application has better versatility and stronger iterativeness. At the same time, since simulation parameters can be modified easily, it is also more conducive to functional debugging and analysis and optimization of existing test vectors.

[0056] Figure 3 FIG. 4 is a schematic flow chart showing a method of providing a test vector to a chip model to be tested. Figure 3 The method for providing a test vector to a chip model to be tested includes the following steps:

[0057] In step S22, the test vector is preprocessed to obtain a text file of test data;

[0058] In this step, test data is extracted from the test vector file, and the extracted test data is stored as a text file in a preset format. Taking the display driver chip as an example, these test data include the level signal of the chip pin, interface type, read / write representation, line delay, line cycle number, etc. Through preprocessing, test vectors of different formats can be converted into text files of the same format, which improves the compatibility of the verification method of this application.

[0059] In some embodiments, the preprocessing of the test vector is performed by a pre-written script file, so before step S22, step S21 is further included: writing a script file, wherein the script file is written in a language including Python.

[0060] In step S23, the text file is read to store the test data in the test vector queue;

[0061] In this step, the text file is read using the read function and the test data is stored in the queue of the structure. The read function includes $fopen, $fscanf, etc.

[0062] In step S25, the test data in the queue are sequentially driven to the chip according to the preset driving timing and flip type. The flip type refers to the flip of 1 and 0 in the digital signal, and 1 and 0 are usually represented by the high and low levels.

[0063] It should be noted that, in some embodiments, the failure of the test vector to pass the verification may be due to an error in the test machine configuration parameters. Therefore, the test machine configuration parameters can be adjusted in combination with the simulation waveform, and the generated test vectors can be re-verified in the update of the test machine parameters (i.e., there is no need to execute step S16 and repeat step S13).

[0064] Specifically, the adjustment of the test machine configuration parameters usually includes adjusting the clock frequency of the test vector driving timing. Therefore, before step S25, step S24 is also included to adjust the driving timing of the test data. It should be noted that the first clock frequency is greater than the clock frequency of the driving timing.

[0065] Figure 4 FIG. 2 is a schematic structural block diagram of a test vector verification device according to an embodiment of the present application. Figure 4 As shown, the test vector verification device 300 provided in the present application includes a processor 310 and a memory 320 .

[0066] The memory 320 is used to store computer readable instructions.

[0067] The processor 310 provides a simulation environment for building and operating the environment. The processor 310 is also used to execute computer-readable instructions stored in the memory 320 to implement the various processes of the various embodiments of the test vector verification method provided in this application, and can achieve the same technical effect, which will not be repeated here.

[0068] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, the present application embodiment also provides a storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by the processor, each process of each embodiment of the above update method can be implemented.

[0069] Since the instructions stored in the storage medium can execute the steps in the update method provided in the embodiment of the present application, the beneficial effects that can be achieved by the verification method provided in the embodiment of the present application can be achieved, which will not be repeated here.

[0070] In summary, according to the test vector verification method, verification device and storage medium provided by the present application, by adding a multiplexer to the top-level port of the chip to be tested in the simulation environment to select the input signal of the chip model to be tested, the simulation verification of the register transfer level of the chip to be tested, the generation of test vectors and the simulation verification of test vectors can be realized through the same simulation environment. By reusing the simulation environment, the time cost and labor cost of setting up the simulation environment are reduced, which is conducive to improving the test efficiency of the wafer. At the same time, since the simulation environment has been used and verified many times in the verification stage of the chip, it has higher stability, the waveform it outputs is closer to the waveform of the real application scenario, and the reliability of the test results is higher.

[0071] Furthermore, by defining a structure in the simulation environment to store simulation data, when matching different test vector verification projects, only the simulation data in the structure needs to be adjusted without making other modifications to the simulation environment, which makes it more iterative.

[0072] Furthermore, by preprocessing the test data extracted from the test vector and converting it into a text file, the verification method provided by the present application can be compatible with test vector files of different formats and has better versatility.

[0073] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. These embodiments are selected and specifically described herein in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A method for verifying a test vector, wherein: The verification method comprises: Obtain a simulation environment for verifying the chip under test; In the simulation environment, adding a multiplexer to the top-level port of the chip model to be tested; During the invalid level of the multiplexer enable signal, providing a register transfer level driving signal to the chip model to be tested via the multiplexer to obtain a test vector; During the period when the multiplexer enable signal is at an effective level, providing the test vector to the chip model under test via the multiplexer to obtain a simulation waveform; Compare the simulation waveform with the expected waveform, and determine whether the test vector is correct based on the comparison result, Wherein, the test vector is determined to be correct when the simulation waveform is consistent with the expected waveform.

2. The verification method according to claim 1, wherein: After obtaining the test vector, the verification method further includes: defining an input driving component and an output monitoring component, wherein the input driving component is used to drive the chip model to be tested, and the output monitoring component is used to monitor the simulation waveform output by the chip model to be tested; and Define a structure for storing simulation data.

3. The verification method according to claim 2, wherein: The simulation data includes the pin signal of the chip, test machine configuration parameters and a queue, and the queue is used to store the test data corresponding to the test vector. The verification method also includes defining the queue in the structure.

4. The verification method according to claim 3, wherein: The method of providing the test vector to the chip model to be tested via the multiplexer comprises: storing the test data in the queue; and The test data is sequentially driven to the chip model to be tested according to a preset driving timing and flip type.

5. The verification method according to claim 4, wherein: The method for storing the test data comprises: preprocessing the test vectors to obtain a text file of the test data; and The text file is read and stored in the queue.

6. The verification method according to claim 5, wherein: Before preprocessing the test vector, the method for storing the test data further includes: A script file is written, where the script file is used to extract the test data from the test vector.

7. The verification method according to claim 4, wherein: The method for obtaining the test vector includes: Monitoring the driving signal and the output signal of the chip model to be tested according to a first clock frequency; and Obtain the test vector according to the monitoring result, The clock frequency of the output signal is a second clock frequency, and the first clock frequency is greater than the second clock frequency.

8. The verification method according to claim 7, wherein: The verification method further comprises: When the simulation waveform is different from the expected waveform, determining that the test vector is wrong; adjusting the first clock frequency according to the analysis result of the simulation waveform; generating a new test vector at the adjusted first clock frequency; and The new test vector is verified.

9. The verification method according to claim 7, wherein: The verification method further comprises: When the simulation waveform is different from the expected waveform, determining that the test vector is wrong; adjusting the clock frequency of the driving timing according to the analysis result of the simulation waveform, wherein the first clock frequency is greater than the clock frequency of the driving timing; and The test vector is verified under the new driving timing.

10. The verification method according to claim 3, wherein: The chip includes a display driver chip, The test data includes the level signal of the chip pin, interface type, read / write flag, row delay, row cycle times, etc.

11. The verification method according to claim 4, wherein: The configuration parameters of the test machine include the clock frequency of the driving timing.

12. A test vector verification device, wherein: The verification device comprises: a memory for storing computer-readable instructions; and A processor executes the readable instructions stored in the memory to implement the verification method provided in any one of claims 1 to 11.

13. A storage medium, wherein: The storage medium stores a computer program, and when the computer program is executed by a processor, the verification method according to any one of claims 1 to 11 is implemented.

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