Chip design tool, method, equipment and computer medium

Abstract

The invention discloses a chip design tool, method and device and a computer medium, and the tool comprises a chip connection relation setting module, a chip layout display module and a wiring module. Wherein a user sets a connection relationship among a plurality of devices in a chip through the chip connection relationship setting module; the chip layout display module is used for displaying or editing chip layout results corresponding to the plurality of devices on a chip layout page based on the plurality of devices; and the wiring module is used for wiring the chip based on the connection relationship between the devices and the chip layout result to obtain a chip design result, and the effect of improving the flexibility of chip design can be achieved.

Description

Technical Field

[0001] The present application belongs to the field of chip design technology, and in particular, relates to a chip design tool, method, device and computer medium. Background Art

[0002] CAD (Computer Aided Design) software has gradually penetrated into various industries, bringing great convenience to designers in all walks of life. Among them, CAD software specifically used for electronic design can also be called EDA (electronic design automation) software, which can assist electronic design engineers in completing electronic design, simulation, verification and other processes. In addition, with the increasing integration of electronic circuits, the number of transistors contained in today's ultra-large-scale integrated circuits is tens of thousands, and manual design has become an unrealistic task. EDA software tools have become an indispensable part of modern electronic design.

[0003] Since the design of electronic circuits is a very professional and complex task, and EDA software needs to be highly coordinated with all aspects of electronic circuit design, the functions and types of EDA software are very diverse, such as system simulation design, printed circuit board design and verification, integrated circuit layout design, digital logic circuit design, analog circuit design, digital-analog hybrid design, system-on-chip design, etc. Although the current EDA tools are very rich, they still fail to meet the endless design requirements in the electronic design process. The relevant circuit design software cannot meet more flexible design requirements and has poor flexibility.

[0004] In 2.5D / 3D packaging design, the design of electronic circuits presents a new form and raises new issues for the industry, from the original connection between transistors to the connection between chiplets. Correspondingly, EDA design tools are also facing completely different problems and challenges from the past: from focusing on the circuit connection between transistors to focusing on the design of packaging structures and the layout and circuit connection of chiplets such as dies. At present, chiplet technology is in its infancy, and the EDA market does not have mature tools for this design technology. It can provide a full-process operation platform from chiplet device selection, layout placement to chiplet wiring and DRC, helping 2.5D / 3D packaging designers to carry out chip design work conveniently and quickly. Summary of the invention

[0005] The embodiment of the present application provides an implementation scheme different from the related art to solve the technical problem in the related art that the related circuit design software cannot meet more flexible design requirements and has poor flexibility.

[0006] In a first aspect, the present application provides a chip design tool, including: a first chip connection relationship setting module based on a schematic diagram, a second chip connection relationship setting module based on a netlist, a chip layout display module, and a wiring module;

[0007] The user sets the connection relationship between multiple devices in the chip through the first chip connection relationship setting module or the second chip connection relationship setting module;

[0008] The chip layout display module is used to display chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices;

[0009] The wiring module is used to wire the chip based on the connection relationship and the chip layout result to obtain a chip design result.

[0010] In a second aspect, the present application provides a chip design method, comprising:

[0011] Acquire the connection relationship between multiple devices in the chip set by the user through the first chip connection relationship setting module based on the schematic diagram or the second chip connection relationship setting module based on the netlist;

[0012] Displaying chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices through a chip layout display module;

[0013] The chip is wired based on the connection relationship and the chip layout result by a wiring module to obtain a chip design result;

[0014] Among them, the first chip connection relationship setting module, the second chip connection relationship setting module, the chip layout display module, and the wiring module are modules in a chip design tool.

[0015] In a third aspect, the present application provides an electronic device, including:

[0016] Processor; and

[0017] A memory, configured to store executable instructions of the processor;

[0018] The processor is configured to execute any method in the second aspect or any possible implementation manner of the second aspect by executing the executable instructions.

[0019] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements any method in the second aspect or any possible implementation manner of the second aspect.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the method described in the second aspect or any of the possible implementations of the second aspect.

[0021] The chip design tool provided by the present application includes: a first chip connection relationship setting module based on a schematic diagram, a second chip connection relationship setting module based on a netlist, a chip layout display module, and a wiring module; wherein the user sets the connection relationship between multiple devices in the chip through the first chip connection relationship setting module or the second chip connection relationship setting module; the chip layout display module is used to display the chip layout results corresponding to the multiple devices on the chip layout page based on the multiple devices; the wiring module is used to wire the chip based on the connection relationship and the chip layout result to obtain a chip design result. Through the solution of the present application, the user can choose one of the schematic design and the netlist design to perform chip design, and the chip design has greater flexibility and higher design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0023] Figure 1a A schematic diagram of the structure of a chip design tool provided in one embodiment of the present application;

[0024] Figure 1b A schematic diagram of a chip layout page provided in an embodiment of the present application;

[0025] Figure 1c An interface diagram of intermediary layer related settings when the intermediary layer is an embedded type provided in an embodiment of the present application;

[0026] Figure 1d An interface for intermediary layer related settings when the intermediary layer is a non-embedded type provided in an embodiment of the present application;

[0027] Figure 1e A schematic diagram of a stacking setting interface provided by an embodiment of the present application;

[0028] Figure 1f A schematic diagram of a schematic diagram editing page provided in an embodiment of the present application;

[0029] Figure 1gA schematic diagram showing content when a relevant person clicks the button of the device library on the schematic editing page provided in an embodiment of the present application;

[0030] Figure 1h A schematic diagram of a chip design process provided by an embodiment of the present application;

[0031] Figure 1i A schematic diagram of a chip design process provided by another embodiment of the present application;

[0032] Figure 1j A schematic diagram of a chip design process provided by another embodiment of the present application;

[0033] Figure 1k A schematic diagram of the architecture of a chip design tool provided in another embodiment of the present application;

[0034] Figure 2 A schematic diagram of a chip design method according to an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a chip design device provided in one embodiment of the present application;

[0036] Figure 4 It is the magnetic adsorption effect of the device pin;

[0037] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, but cannot be understood as limiting the present application.

[0039] The terms "first" and "second" etc. in this application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0040] First, some terms in the embodiments of the present application are explained below to facilitate understanding by those skilled in the art.

[0041] Bare chip (die): refers to the chip produced in a processing plant. The chip only has pads for packaging and cannot be directly used in actual circuits.

[0042] Chiplet refers to a pre-manufactured chip (die) with specific functions that can be combined and integrated. It can also be an integrated functional chip (that is, a chip after the die is packaged). Chiplet is narrowly called a core particle, but the industry sometimes refers to bare dies and small chips that are still small in size after packaging. Chiplet is also translated as "small chip".

[0043] DRC (Design rules checking): Through the use of checklists and reports, it focuses on avoiding major design defects such as bypassing and short circuits. While checking, it also follows the PCB (Printed Circuit Board) design quality control process and methods.

[0044] Jump wire, also known as jumper wire, refers to a method of directly connecting two nodes on a printed circuit board with wires due to design defects, testing purposes or other design considerations.

[0045] Interposer is an intermediary layer, commonly used in distributed systems, which can help nodes in the upper or lower layers exchange information (such as connecting two chips).

[0046] Substrate: refers to the substrate or base plate. The substrate refers to the board used for electronic product packaging, which provides support and electrical connections for electronic components. The material of the substrate can be silicon, ceramic or organic material, and the specific material to be selected depends on the specific requirements of the application.

[0047] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0048] Figure 1a A schematic diagram of a chip design tool provided for an exemplary embodiment of the present application, the chip design tool comprising: a chip connection relationship setting module, a chip layout display module 13, and a wiring module 14;

[0049] The user sets the connection relationship between multiple devices in the chip through the chip connection relationship setting module;

[0050] The chip layout display module is used to display or edit chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices;

[0051] The wiring module 14 is used to wire the chip based on the connection relationship between the devices and the chip layout result to obtain a chip design result.

[0052] The chip connection relationship setting module includes: a first chip connection relationship setting module 11 based on a schematic diagram, and a second chip connection relationship setting module 12 based on a netlist.

[0053] The user sets the connection relationship between multiple devices in the chip through the first chip connection relationship setting module 11 or the second chip connection relationship setting module 12;

[0054] In some optional embodiments, the first chip connection relationship setting module 11 may also include a first display module for displaying a schematic editing page, and a user may design a chip by drawing a schematic on the schematic editing page.

[0055] In some optional embodiments, the second chip connection relationship setting module 12 may further include a second display module for displaying a netlist editing page, and a user may set netlist information on the netlist editing page.

[0056] The netlist information may include the parameters of the netlist, some of which are editable (such as pin network names, etc.) and some of which are not editable (such as device names, pin numbers, etc.). Users define pin network names to set the connection relationship of device pins.

[0057] In some optional embodiments, it further includes: a device library;

[0058] The user sets the connection relationship between multiple devices in the chip through the device library and the first chip connection relationship setting module, or sets the connection relationship between multiple devices in the chip through the device library and the second chip connection relationship setting module.

[0059] In some optional embodiments, the devices in the device library include at least one of the following: chiplets, bare chips, interposers, and passive devices. For example, the devices in the device library include chiplets (chiplets, bare chips), interposers, or passive devices; interposers can be passive interposers or active interposers; chiplets or bare chips can be logic chips or memory chips; the device library displays the aforementioned devices in categories, and the categories include at least one of the following: sensors, power supplies, radio frequency circuits, memories, clocks, passive devices, and interposers.

[0060] The passive components may be resistors, capacitors, etc. In some embodiments, the passive components further include integrated passive components.

[0061] In some optional embodiments, the types of the aforementioned intermediary layer may include embedded type and non-embedded type. Figure 1b The schematic diagram of the chip layout page shown, Figure 1c When the interposer type is embedded, the interface diagram of the interposer related settings is shown, and Figure 1d The diagram shows an interface diagram of related settings of the interposer when the interposer is of non-embedded type.

[0062] Further, see Figure 1c The interface diagram of the interposer related settings when the interposer type is embedded is shown. In some embodiments, the embedding depth of the interposer in the Substrate can be 7 microns. As for the stacking settings, they can be set manually by relevant personnel or by importing tech files.

[0063] Further, see Figure 1d When the intermediary layer type is non-embedded, the intermediary layer related settings interface is shown. In some embodiments, the setting parameters for Ball can be referred to Figure 1d As shown, the setting parameters for Ball may include: rows, columns, spacing, and quantity, wherein the rows may be 10, the columns may be 20, the spacing may be 2 microns, and the quantity may be 200. As for the setting of the stack, it can be set manually by relevant personnel or by importing a tech file. Optionally, the setting interface of the stack or the content of the tech file can be found in Figure 1e As shown, no further description is given here.

[0064] In some optional embodiments, the parameters of the netlist include the name of the device selected by the user from the device library, the pin number of the device, etc., and the connection relationship between any devices, which is not limited in this application.

[0065] In some optional embodiments, the connection relationship between device pins is set by defining the pin network names of the pins, for example, pins with the same pin network name are connected to each other.

[0066] In some optional embodiments, the aforementioned netlist information is displayed on the netlist editing page after being set.

[0067] In some optional embodiments, the aforementioned netlist information may be determined based on a netlist uploaded by a user. Wherein, when the netlist information is determined by a netlist uploaded by a user, the aforementioned tool may further include a prompting module for prompting the user to upload the netlist.

[0068] In some optional embodiments, the user may also download the current netlist locally and use other professional netlist editing tools to edit it and input the netlist information.

[0069] In some optional embodiments of the present application, after the netlist information is partially or fully set, the user can search for part of the netlist information through filtering conditions, where the filtering conditions can be the name of the device, pin number, etc.

[0070] In some optional embodiments of the present application, the above-mentioned tool also includes a switching module, which is used to display the schematic editing page when it is detected that the user triggers the startup of the schematic editing page corresponding to the first chip connection relationship setting module; and is used to display the netlist editing page when it is detected that the user triggers the startup of the netlist editing page corresponding to the second chip connection relationship setting module; wherein the schematic editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

[0071] Furthermore, the user can select a device in the device library on the schematic editing page to enter the chip design, which can include designing the logical connection relationship between any devices. Specifically, the connection relationship between the devices can include the connection relationship between the device pins.

[0072] In some optional embodiments of the present application, Figure 1f For schematic diagrams of the schematic editing page, Figure 1f In the diagram, below the group is a list of selected devices, and the schematic editing area shows the pin numbers of the specific devices (i.e. Figure 1f ), and the user's settings for the network of each pin, where when the pins of two devices have the same network, the pins of the same network can interact. Furthermore, the schematic editing page can also include multiple icons for operating devices, such as edit, left and right mirror, top and bottom mirror, move, method, store, previous step, next step, and delete.

[0073] In an optional embodiment of the present application, the schematic editing page also includes a device library button. When the relevant personnel click the button, the displayed content can be seen in Figure 1g shown.

[0074] Optionally, users can see all available devices in the device library on the schematic editing page, and can import the devices they need by dragging and dropping, and then define the logical connection relationship between the pins of each device in the form of a circuit schematic, thereby realizing the logic design of the chip.

[0075] In some optional embodiments of the present application, the user uses the second chip connection relationship setting module 12, that is, the connection relationship between multiple devices in the chip edited by the netlist will be synchronized in real time to the first chip connection relationship setting module 11 and the chip layout display module, so that the connection relationship between the multiple devices set by the user through the second chip connection relationship setting module 12 can be displayed through the first display module, and the multiple devices used by the user through the second chip connection relationship setting module 12 can also be presented through the chip layout display module.

[0076] In some optional embodiments of the present application, the user uses the first chip connection relationship setting module 11, that is, the connection relationship between multiple devices in the chip edited by the schematic diagram will be synchronized in real time to the second chip connection relationship setting module 12 and the chip layout display module, so that the connection relationship between the multiple devices set by the user through the first chip connection relationship setting module 11 can be displayed through the second display module, and the multiple devices used by the user through the first chip connection relationship setting module 11 can also be presented through the chip layout display module.

[0077] In some optional embodiments, the user can select any one of the first chip connection relationship setting module 11 and the second chip connection relationship setting module 12 to set the connection relationship between multiple devices in the chip.

[0078] In some optional embodiments of the present application, the aforementioned tool may be a client, and the user may view the historical chip design results created by the user in the aforementioned tool, wherein a chip design result mentioned in the present application may be saved as a chip project.

[0079] In some optional embodiments of the present application, when opening a chip design tool and creating a new chip project, the user can select only one of the first chip connection relationship setting module 11 and the second chip connection relationship setting module 12 to set the connection relationship between multiple devices in the chip through corresponding selection, thereby avoiding data processing delays caused by synchronous updates between the first chip connection relationship setting module 11 and the second chip connection relationship setting module 12.

[0080] In some optional embodiments of the present application, an interposer that has completed circuit design and wiring design can be imported into a device library as a standard device and reused by multiple users. At this time, the interposer can directly select and edit the connection relationship between the pins of the interposer and the pins of the core particle on the schematic editing page or the netlist editing page.

[0081] Optionally, the interposer in the device library can be a silicon substrate without any wiring. When the interposer is needed to interconnect the core particles or dies (i.e. 2.5D packaging), after the connection relationship between the core particles or dies is determined, the layout relationship between the core particles and the interposer is designed on the chip layout page. After the design is completed, the wiring design is performed inside the interposer in the wiring module to interconnect the core particles. Each interposer designed is captured by the device library to generate a new interposer device so that the interposer can be reused in subsequent projects.

[0082] In some optional embodiments of the present application, the device library in the present application can be edited by the user.

[0083] In some optional embodiments of the present application, the device library in the present application may be a device library uploaded by the user.

[0084] In some optional embodiments of the present application, the device library in the present application supports users to import device data, export device data, view device data, and edit device data, wherein the device data refers to the device data of the devices included in the device library.

[0085] In some optional embodiments of the present application, the user may also select a device in the device library on the chip layout page, and may drag the selected device to the display area of ​​the chip layout, wherein the display area of ​​the chip layout is specifically a display area of ​​the chip layout results.

[0086] like Figure 4 As shown, in some optional embodiments of the present application, the user can also select a device in the device library on the chip layout page, and the above tool can also present a magnetic adsorption effect based on the position relationship of the pins under the device. When clicking or dragging the device, the corresponding pins are automatically adsorbed and connected. Specifically, this function can be implemented based on the aforementioned chip layout display module.

[0087] In some optional embodiments of the present application, the devices displayed in the display area of ​​the chip layout result are consistent with the devices set by the first chip connection relationship setting module 11 and the devices set by the second chip connection relationship setting module.

[0088] In some optional embodiments of the present application, when a user views multiple devices included in a device library, secondary filtering is supported, wherein the primary filtering and the secondary filtering may refer to the major category and the minor category to which the devices in the device library belong, respectively.

[0089] In some optional embodiments of the present application, the aforementioned sensors, power supplies, radio frequency circuits, memories, clocks, and passive devices are major categories in the device library classification.

[0090] In some optional embodiments of the present application, the user can expand or reduce the device library. For example, the user can add new device information to the device library.

[0091] In some optional embodiments, the tool further comprises an identification module, which can automatically identify new device information and classify it into a device library. The new device information that can be identified by the identification module can come from a netlist.

[0092] In some optional embodiments, the tool further includes a prompt module. When a device input by a user in a netlist does not exist in a device library, the prompt module will prompt the user to create a corresponding device.

[0093] Furthermore, the tools in this application may also support the design of redistribution layers (RDL) and bump maps for connecting functional core particles. The tools in this application may also support fine bumpmap position error evaluation and analysis, which is not limited in this application.

[0094] Furthermore, the tool of the present application can also be applied to 3D-SIP (system-level packaging) and ATE (automatic test equipment) test channel connection design and simulation.

[0095] In some optional embodiments of the present application, the aforementioned tool in the present application also includes a message log module, wherein the message log module is used to allow users to obtain log information generated by various operations in real time, so that users can understand various data of the operation process and automatically use alarms. Optionally, anomalies generated by the operation process can also be highlighted in yellow.

[0096] In some optional embodiments of the present application, the tool further includes: an interposer adding module, configured to: in response to a user's operation of adding an interposer, display the interposer on the chip layout page.

[0097] In some optional embodiments of the present application, the tool further includes: a substrate adding module, which is used to: in response to a user's operation of adding a substrate, display the substrate on the chip layout page.

[0098] In the present application, the chip layout display module 13 can be used for users to add interposer and other interposer devices on the chip layout page, and can be used for users to define the spatial position relationship of each unit, interposer and other devices on the chip layout page, including but not limited to the relative position of each device on the horizontal plane, the rotation angle of the device, the stacking relationship between some devices, the contact relationship between the device and the pin foot / the pin foot and the pin foot, etc. Among them, the chip layout page is a three-dimensional view interface. Furthermore, the user can also define the pin distribution of the interposer and other interposer devices and the corresponding network on the chip layout page through the chip layout display module 13.

[0099] In some optional embodiments of the present application, the parameters that users can define when adding an interposer include: coordinates, size, stacking, bump arrangement, network allocation, and pins (newly generated pins require manual network allocation). At the same time, it supports importing tech files and importing interposer definitions. In addition, users can also edit the coordinates, size, stacking, ball arrangement, and network allocation of the Substrate. It also supports users to import substrate files to add substrates.

[0100] After the bump in Interposer is edited, the bump pad on the substrate can be automatically generated to correspond to it one by one.

[0101] In some optional embodiments of the present application, in the chip layout display module 13, it is also stipulated that the stacking or movement of devices can be achieved by dragging the mouse, entering coordinates, etc.; at the same time, you can also choose: embedded, stacked above (directly find the upper surface); you can also choose the commonly used stacking methods: EMIB, 2.5D, 3D.

[0102] In some optional embodiments of the present application, the chip layout display module is further used to: obtain preset layout rules; and layout the multiple devices based on the preset layout rules.

[0103] In some optional embodiments of the present application, the wiring module 14 is used for the user to enable the automatic wiring operation in the three-dimensional view page, and present the result of the automatic wiring in the form of a three-dimensional model. The user can choose to display or hide the entire physical wiring result, or choose to display or hide the wiring corresponding to a specific network, and can also highlight the physical wiring line corresponding to a specific network. Among them, the wiring scheme of each layer in Interposer can be selected and displayed separately.

[0104] In some optional embodiments of the present application, in addition to defining the spatial position of the device, the user can also highlight the selected device through the physical layout module and switch between transparent and opaque modes. The physical layout module can be included in the chip layout display module.

[0105] In some optional embodiments of the present application, when a user is editing a netlist, when the user clicks on a border of the netlist, the border may be highlighted.

[0106] In some optional embodiments of the present application, the tool further includes: a chip detection module, which is used to:

[0107] In response to a user's detection operation on the chip design result, obtaining design rule information;

[0108] Checking the chip design result based on the design rule information to obtain a check result;

[0109] The inspection result is displayed.

[0110] In some optional embodiments of the present application, a button corresponding to the chip detection module may be set on the chip layout page. When a user operation on the button is detected, it is deemed that the user's detection operation on the chip design result has been received.

[0111] In some optional embodiments of the present application, the design rule information is mainly DRC rules. The specific rule content can be set by relevant packaging or chip designers and needs to be determined according to specific project requirements. Different projects have different packaging requirements and chip design requirements.

[0112] In some optional embodiments of the present application, the tool further includes: an import module for allowing a user to import the netlist.

[0113] In some optional embodiments of the present application, the tool further includes: a response module, configured to:

[0114] In response to a user's dragging operation on any device among the plurality of devices on the chip layout page, the arbitrary device is controlled to move accordingly.

[0115] In some optional embodiments of the present application, the tool further includes: an export module, which is used to:

[0116] In response to a user's operation of exporting the chip design result, the chip design result is exported.

[0117] The solution of the present application proposes a new type of chip design tool, which can use a bare die (DIE) or a small chip as an operating device, complete the logic design of the chip by defining the logical connection relationship between them, and then complete the physical layout and wiring of each bare die device in the chip in the form of a three-dimensional view, and finally perform a DRC check and complete the design of the entire chip. In addition, the tool provided by the embodiment of the present application allows the user to set the logical relationship between units in the form of a netlist or schematic diagram, and then present it in the form of flying lines in a three-dimensional view; afterwards, the user can complete the spatial layout of each unit by dragging and other operations, and can use custom DRC rules to check the layout results.

[0118] In addition, the tool in the present application also supports an automatic routing function, and the chip can be routed through the routing module 14 to obtain a chip design result. When the routing module 14 specifically routes, the real three-dimensional space lines between each chiplet can be calculated, and the space routing results can be checked using custom DRC rules.

[0119] In some optional embodiments of the present application, the aforementioned prompt module is also used to present the anomalies and errors generated in the chip design process in real time, and to display the intermediate data generated by each calculation link in real time.

[0120] The following combination Figure 1h To further explain this solution, specifically, when using the tool of this application, the user can select devices through the first chip connection relationship setting module or the second chip connection relationship setting module, and can edit the logical connection relationship between devices. After editing the logical connection relationship between devices, the user can further perform physical layout based on the chip layout display module, and perform physical layout DRC based on the chip detection module; further, the user can perform physical wiring based on the wiring module, and perform physical layout DRC based on the chip detection module, and export the design results based on the export module.

[0121] See also Figure 1i and Figure 1jAs shown, the user can set the connection relationship between multiple devices in the chip by importing a netlist or directly opening the netlist tool, and editing it on the netlist page to edit the logical connection relationship between the devices. Optionally, the user can also set the connection relationship between multiple devices in the chip by directly opening the schematic diagram and editing it on the schematic diagram page. Optionally, the user can also import the netlist before opening the netlist. Optionally, the timing of the user selecting a device from the device library is not limited in this application. For example, the user can select a device from the device library when opening the netlist, importing the netlist, opening the schematic diagram, or drawing the schematic diagram, or before. Optionally, after opening the schematic diagram tool, the user can also switch to importing the netlist.

[0122] Specifically, the user first selects the device and then sets the connection relationship between multiple devices in the chip. Figure 1h After selecting a device, the user can edit the netlist by importing it, or edit the schematic by opening it. For a schematic diagram of the connection relationship between multiple devices in the chip, see Figure 1i As shown; the corresponding schematic diagram of the user importing the netlist before opening the netlist tool can be seen in Figure 1j shown.

[0123] In some optional embodiments of the present application, the chip layout page can be found at Figure 1b As shown, the specific parameter settings can be found in the figure and will not be repeated here.

[0124] Furthermore, the present application also provides a schematic diagram of the software architecture of the tool in the present application, see Figure 1k As shown, specifically, the product framework of the tool proposed in this application includes: device selection, logical connection, spatial layout, wiring pre-inspection, export design, and offline production; the core business modules include: 3D model interaction, package architecture model, netlist logical connection, design sample library, automatic layout, device library, automatic wiring, Test Bench, DRC pre-inspection, assembly process animation, pin distribution design, real-time cost estimation, simulation effect presentation, and background management system; the technical basic modules include: external database docking, external service docking, external EDA file parsing, external EDA file generation, K 85 microservice framework, Kafka message queue, Java, micro front-end APP Shell, log system, JavaScript, React application framework, plug-in system, Python, Three 3D framework, message system, Postgre SQL, multi-tenant account system, background tasks, MongoDB, payment system, AI assistance, and Redis.

[0125] The chip design tool provided by the present application includes: a first chip connection relationship setting module based on a schematic diagram, a second chip connection relationship setting module based on a netlist, a chip layout display module, and a wiring module; wherein the user sets the connection relationship between multiple devices in the chip through the first chip connection relationship setting module or the second chip connection relationship setting module; the chip layout display module is used to display the chip layout results corresponding to the multiple devices on the chip layout page based on the multiple devices; the wiring module is used to wire the chip based on the connection relationship and the chip layout result to obtain a chip design result. Through the solution of the present application, the user can choose one of the schematic design and the netlist design to perform chip design, and the chip design has greater flexibility and higher design efficiency.

[0126] The present application also provides a chip design method. Figure 2 A schematic flow chart of a chip design method provided in an embodiment of the present application includes at least the following steps S201-S203:

[0127] S201, obtaining a connection relationship between multiple devices in a chip set by a user through a first chip connection relationship setting module based on a schematic diagram or a second chip connection relationship setting module based on a netlist;

[0128] In some optional embodiments, the first chip connection relationship setting module may also include a first display module for displaying a schematic editing page, and a user may perform chip design by drawing a schematic on the schematic editing page.

[0129] In some optional embodiments, the second chip connection relationship setting module may further include a second display module for displaying a netlist editing page, and a user may set netlist information on the netlist editing page.

[0130] The netlist information may include parameters of the netlist, wherein some parameters of the netlist are editable, for example, modifiable, and some parameters are not editable.

[0131] S202, displaying chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices through a chip layout display module;

[0132] In the present application, the chip layout display module can be used for users to add interposer and other interposer devices on the chip layout page, and can be used for users to define the spatial position relationship of each unit, interposer and other devices on the chip layout page, including but not limited to the relative position of each device in three-dimensional space, the rotation angle of the device, the stacking relationship between some devices, the contact relationship between the device and the pin / pin and pin, etc. Among them, the chip layout page is a three-dimensional view interface. Furthermore, users can also define the pin distribution of interposer and other interposer devices and the corresponding network on the chip layout page through the chip layout display module.

[0133] In some optional embodiments of the present application, the parameters that users can define when adding an interposer include: coordinates, size, stacking, ball arrangement, network allocation, and pins (newly generated pins require manual network allocation). At the same time, it supports importing tech files and importing interposer definitions. In addition, users can also edit the coordinates, size, stacking, ball arrangement, and network allocation of the Substrate. It also supports users to import substrate files to add substrates.

[0134] S203, routing the chip based on the connection relationship and the chip layout result through a routing module to obtain a chip design result;

[0135] In some optional embodiments of the present application, the wiring module is used for the user to enable automatic wiring operation in the three-dimensional view page, and present the results of automatic wiring in the form of a three-dimensional model. The user can choose to display or hide the entire physical wiring result, or choose to display or hide the wiring corresponding to a specific network, and can also highlight the physical wiring lines corresponding to a specific network. Among them, the wiring scheme of each layer in Interposer can be selected and displayed separately.

[0136] Among them, the first chip connection relationship setting module, the second chip connection relationship setting module, the chip layout display module, and the wiring module are modules in a chip design tool.

[0137] In some optional embodiments of the present application, the aforementioned tool may be a client, and the user may view the historical chip design results created by the user in the aforementioned tool, wherein a chip design result mentioned in the present application may be saved as a chip project.

[0138] In an optional embodiment of the present application, the method further includes:

[0139] Displaying a schematic diagram editing page through the first chip connection relationship setting module;

[0140] In response to an operation of selecting a first device from a device library on the schematic editing page triggered by a user, displaying device information of the first device on the schematic editing page;

[0141] or

[0142] Displaying a netlist editing page through the second chip connection relationship setting module;

[0143] In response to an operation of selecting a first device from the device library triggered by a user on the netlist editing page, displaying device information of the first device on the netlist editing page;

[0144] The schematic editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

[0145] In an optional embodiment of the present application, the method further includes the following S01-S03:

[0146] S01, in response to a user's detection operation on the chip design result, obtaining design rule information;

[0147] S02, checking the chip design result based on the design rule information to obtain a check result;

[0148] S03: display the inspection result.

[0149] In an optional embodiment of the present application, the method further includes: in response to a user's dragging operation on any device among the multiple devices on the chip layout page, controlling the arbitrary device to move accordingly.

[0150] The specific implementation method of this embodiment can be found in the above content and will not be repeated here.

[0151] Figure 3 A schematic diagram of a chip design device provided for an exemplary embodiment of the present application, wherein the device comprises:

[0152] An acquisition unit 31 is used to acquire a connection relationship between multiple devices in a chip set by a user through a first chip connection relationship setting module based on a schematic diagram or a second chip connection relationship setting module based on a netlist;

[0153] A display unit 32, configured to display chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices through a chip layout display module;

[0154] A wiring unit 33, configured to perform wiring on the chip based on the connection relationship and the chip layout result through a wiring module to obtain a chip design result;

[0155] Among them, the first chip connection relationship setting module, the second chip connection relationship setting module, the chip layout display module, and the wiring module are modules in a chip design tool.

[0156] Optionally, the aforementioned device can also be used for:

[0157] Displaying a schematic diagram editing page through the first chip connection relationship setting module;

[0158] In response to an operation of selecting a first device from a device library on the schematic editing page triggered by a user, displaying device information of the first device on the schematic editing page;

[0159] or

[0160] Displaying a netlist editing page through the second chip connection relationship setting module;

[0161] In response to an operation of selecting a first device from the device library triggered by a user on the netlist editing page, displaying device information of the first device on the netlist editing page;

[0162] The schematic editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

[0163] Optionally, the aforementioned device can also be used for:

[0164] In response to a user's detection operation on the chip design result, obtaining design rule information;

[0165] Checking the chip design result based on the design rule information to obtain a check result;

[0166] The inspection result is displayed.

[0167] Optionally, the aforementioned apparatus may also be used to: in response to a user's dragging operation on any device among the plurality of devices on the chip layout page, control the arbitrary device to move accordingly.

[0168] It should be understood that the device embodiment and the method embodiment may correspond to each other, and similar descriptions may refer to the method embodiment. To avoid repetition, no further description is given here. Specifically, the device may perform the above method embodiment, and the above and other operations and / or functions of each module in the device are the corresponding processes in each method in the above method embodiment, respectively, and no further description is given here for the sake of brevity.

[0169] The above describes the device of the embodiment of the present application from the perspective of the functional module in conjunction with the accompanying drawings. It should be understood that the functional module can be implemented in hardware form, can be implemented by instructions in software form, and can also be implemented by a combination of hardware and software modules. Specifically, the steps of the method embodiment in the embodiment of the present application can be completed by the hardware integrated logic circuit and / or software form instructions in the processor, and the steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or a combination of hardware and software modules in the decoding processor to perform. Optionally, the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory, and completes the steps in the above method embodiment in conjunction with its hardware.

[0170] Figure 5 is a schematic block diagram of an electronic device provided in an embodiment of the present application, and the electronic device may include:

[0171] The memory 401 and the processor 402, the memory 401 is used to store the computer program and transmit the program code to the processor 402. In other words, the processor 402 can call and run the computer program from the memory 401 to implement the method in the embodiment of the present application.

[0172] For example, the processor 402 may be configured to execute the above method embodiments according to instructions in the computer program.

[0173] In some embodiments of the present application, the processor 402 may include but is not limited to:

[0174] General-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.

[0175] In some embodiments of the present application, the memory 401 includes but is not limited to:

[0176] Volatile memory and / or non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0177] In some embodiments of the present application, the computer program may be divided into one or more modules, which are stored in the memory 401 and executed by the processor 402 to complete the method provided by the present application. The one or more modules may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0178] like Figure 5 As shown, the electronic device may also include:

[0179] The transceiver 403 may be connected to the processor 402 or the memory 401 .

[0180] The processor 402 may control the transceiver 403 to communicate with other devices, specifically, to send information or data to other devices, or to receive information or data sent by other devices. The transceiver 403 may include a transmitter and a receiver. The transceiver 403 may further include an antenna, and the number of antennas may be one or more.

[0181] It should be understood that the various components in the electronic device are connected via a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus and a status signal bus.

[0182] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a computer, the computer can perform the method of the above method embodiment. In other words, the present application embodiment also provides a computer program product containing instructions, and when the instructions are executed by a computer, the computer can perform the method of the above method embodiment.

[0183] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a solid state drive (solid state disk, SSD)), etc.

[0184] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0185] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0186] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. For example, each functional module in each embodiment of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0187] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip design tool, characterized in that: include: Chip connection relationship setting module, chip layout display module, and wiring module; The user sets the connection relationship between multiple devices in the chip through the chip connection relationship setting module; The chip layout display module is used to display or edit chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices; The wiring module is used to wire the chip based on the connection relationship between the devices and the chip layout result to obtain a chip design result.

2. The tool according to claim 1, characterized in that The chip connection relationship setting module includes: a first chip connection relationship setting module based on a schematic diagram, and a second chip connection relationship setting module based on a netlist.

3. The tool according to claim 2, characterized in that Also includes: Device library; The user sets the connection relationship between multiple devices in the chip through the device library and the first chip connection relationship setting module, or sets the connection relationship between multiple devices in the chip through the device library and the second chip connection relationship setting module.

4. The tool according to claim 3, characterized in that The parameters in the netlist include: device name, pin number, pin network name; the user sets the connection relationship of the device pins by defining the pin network name.

5. The tool according to claim 3, characterized in that The devices in the device library include at least one of the following: a die, a bare die, an interposer, and a passive device.

6. The tool according to claim 5, characterized in that The device library displays the devices by categories, and the categories include: sensor, power supply, radio frequency circuit, memory, clock, passive device, and intermediate layer.

7. The tool according to claim 1, characterized in that Also includes: Chip detection module for: In response to a user's detection operation on the chip design result, obtaining design rule information; Checking the chip design result based on the design rule information to obtain a check result; The inspection result is displayed.

8. The tool according to claim 2, characterized in that Also includes: The import module is used for allowing the user to import the netlist.

9. The tool according to claim 2, characterized in that It also includes a switching module, which is used to display the schematic diagram editing page when detecting that the schematic diagram editing page corresponding to the first chip connection relationship setting module is started by a user; and used to display the netlist editing page when detecting that the netlist editing page corresponding to the second chip connection relationship setting module is started by a user; The schematic editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

10. The tool according to claim 1, characterized in that Also includes response modules for: In response to a user's dragging operation on any device among the plurality of devices on the chip layout page, the arbitrary device is controlled to move accordingly.

11. The tool according to claim 1, characterized in that The chip layout display module is also used for: Get the preset layout rules; The plurality of devices are laid out based on the preset layout rule.

12. The tool according to claim 1, characterized in that Also includes: Export modules for: In response to a user's operation of exporting the chip design result, the chip design result is exported.

13. The tool according to claim 1, characterized in that Also includes: The interposer adding module is used to: in response to a user's operation of adding an interposer, display the interposer on the chip layout page.

14. The tool according to claim 1, characterized in that Also includes: The substrate adding module is used to: in response to a user's operation of adding a substrate, display the substrate on the chip layout page.

15. A chip design method, characterized in that: include: Acquire the connection relationship between multiple devices in the chip set by the user through the first chip connection relationship setting module based on the schematic diagram or the second chip connection relationship setting module based on the netlist; Displaying chip layout results corresponding to the multiple devices on a chip layout page based on the multiple devices through a chip layout display module; The chip is wired based on the connection relationship and the chip layout result by a wiring module to obtain a chip design result; Among them, the first chip connection relationship setting module, the second chip connection relationship setting module, the chip layout display module, and the wiring module are modules in a chip design tool.

16. The method according to claim 15, characterized in that The method further comprises: Displaying a schematic diagram editing page through the first chip connection relationship setting module; In response to an operation of selecting a first device from a device library on the schematic editing page triggered by a user, displaying device information of the first device on the schematic editing page; or Displaying a netlist editing page through the second chip connection relationship setting module; In response to an operation of selecting a first device from the device library triggered by a user on the netlist editing page, displaying device information of the first device on the netlist editing page; The schematic editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

17. The method according to claim 16, characterized in that The method further comprises: In response to a user's detection operation on the chip design result, obtaining design rule information; Checking the chip design result based on the design rule information to obtain a check result; The inspection result is displayed.

18. The method according to claim 15, characterized in that The method further comprises: In response to a user's dragging operation on any device among the plurality of devices on the chip layout page, the arbitrary device is controlled to move accordingly.

19. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to perform the method of any one of claims 15-18 by executing the executable instructions.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 15 to 18 is implemented.

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