Method for determining parallel execution quantum circuit and related device

Abstract

The invention discloses a method for determining quantum circuits executed in parallel and a related device, and belongs to the technical field of quantum computing, and the method comprises the steps: obtaining a circuit set composed of quantum circuits needing to be executed; for each quantum circuit in the circuit set, determining a layout set composed of the circuit layout of the quantum circuit by using the physical bit layout of target quantum hardware; the score of each line layout in the layout set of each quantum line is obtained, and the score is determined by the noise level of the target quantum hardware; and under a target condition, determining the quantum circuits which are executed in parallel and the corresponding circuit layouts from the circuit set by utilizing an equation constructed by the determined score and the use relationship between each quantum circuit and the corresponding circuit layout. By applying the embodiment of the invention, the service efficiency and throughput of the quantum computing platform can be improved.

Description

Technical Field

[0001] The present application belongs to the field of quantum computing technology, and in particular to a method and related device for determining quantum circuits for parallel execution. Background Art

[0002] Quantum computing is a new computing model that follows the laws of quantum mechanics to control quantum information units for computing. Unlike classical computing, quantum computing follows the laws of quantum mechanics and is a new computing model that can break through the bottleneck of classical computing power. Quantum computers, as devices that perform quantum computing tasks, use quantum bits (qubits) as basic computing units. In quantum computing, based on the principle of quantum superposition, different states of quantum bits can be stored and processed simultaneously.

[0003] Quantum computing has matured from a purely theoretical computing model to one that can outperform traditional computers on certain problems. Currently, several companies offer free or paid access to their quantum hardware devices. Most of this access is provided through quantum cloud platforms. As the demand for quantum computing continues to grow, users often have to wait in line for a long time, and their jobs must wait until all previously submitted jobs have been completed. Therefore, there is an urgent need to improve the service efficiency and throughput of quantum computing platforms to improve user experience. Summary of the invention

[0004] The purpose of this application is to provide a method and related device for determining quantum circuits for parallel execution, aiming to improve the service efficiency and throughput of a quantum computing platform.

[0005] An embodiment of the present application provides a method for determining quantum circuits executed in parallel, the method comprising:

[0006] Obtain a circuit set consisting of quantum circuits to be executed;

[0007] For each quantum circuit in the circuit set, using the physical bit layout of the target quantum hardware, determine a layout set consisting of the circuit layout of the quantum circuit, wherein the target quantum hardware is the quantum hardware in the quantum computing platform, and each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set;

[0008] Obtaining a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by a noise level of a target quantum hardware;

[0009] Under a target condition, quantum circuits executed in parallel and corresponding circuit layouts are determined from the circuit set using an equation constructed by the determined score and a usage relationship between each quantum circuit and each corresponding circuit layout, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

[0010] Optionally, for each quantum circuit in the circuit set, determining a layout set consisting of the circuit layout of the quantum circuit by using the physical bit layout of the target quantum hardware includes:

[0011] Determining the topological structure of each quantum circuit in the circuit set;

[0012] According to the matching relationship between the topological structure of each quantum circuit and the physical bit layout of the target quantum hardware, a layout set consisting of the circuit layout corresponding to each quantum circuit is determined.

[0013] Optionally, determining a layout set consisting of a circuit layout corresponding to each quantum circuit according to a matching relationship between the topological structure of each quantum circuit and the physical bit layout of the target quantum hardware includes:

[0014] Determine a set of topological structures corresponding to the target quantum hardware by using the physical bit layout of the target quantum hardware;

[0015] For each quantum circuit, a topological structure identical to the topological structure of the quantum circuit is determined from the set of topological structures corresponding to the target quantum hardware as the target topological structure;

[0016] The target topological structure of each quantum circuit is used to determine a layout set consisting of circuit layouts corresponding to the quantum circuit.

[0017] Optionally, the step of using the target topological structure of each quantum circuit to determine a layout set consisting of circuit layouts corresponding to the quantum circuit includes:

[0018] For each quantum circuit, the physical bit groups corresponding to the target topological structure are used as the circuit layouts in the layout set corresponding to the quantum circuit.

[0019] Optionally, under the target condition, determining the quantum circuits to be executed in parallel and the corresponding circuit layouts from the circuit set by using an equation constructed by the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, comprises:

[0020] Determine the area of ​​each quantum circuit, where the area of ​​the quantum circuit is the number of physical bits that the quantum circuit needs to occupy;

[0021] Under target conditions, with the goal of minimizing an equation consisting of decision variables and coefficients of the decision variables, the equation is solved to determine quantum circuits to be executed in parallel, wherein the decision variables are the usage relationship between each quantum circuit and each corresponding circuit layout, and the coefficients of the decision variables are constructed using the area of ​​each quantum circuit and the determined score.

[0022] Optionally, the equations are constructed using integer linear programming.

[0023] Optionally, the coefficient of the decision variable is:

[0024] c ij =q ej A i -1

[0025] Among them, c ij represents the coefficient of the decision variable corresponding to quantum circuit i using circuit layout j, q ij represents the score of quantum circuit i using circuit layout j, represents the area of ​​quantum circuit i normalized over all quantum circuits, and M is the sum of the areas of all quantum circuits.

[0026] Optionally, the method further includes:

[0027] When the number of quantum bits of the received quantum circuit requested to be executed exceeds the number of physical bits of the target quantum hardware, the received quantum circuit is discarded.

[0028] Optionally, the method further includes:

[0029] Deploying the determined quantum circuits to be executed in parallel onto the target quantum hardware according to the corresponding circuit layout, so that the target quantum hardware executes the determined quantum circuits in parallel;

[0030] After receiving the information of completion of the operation fed back by the target quantum hardware, if there are quantum circuits that have not been executed, the method returns to the step of obtaining a circuit set consisting of quantum circuits to be executed.

[0031] Another embodiment of the present application provides a device for determining quantum circuits executed in parallel, the device comprising:

[0032] A first acquisition module is used to obtain a circuit set consisting of quantum circuits to be executed;

[0033] A first determination module is used to determine, for each quantum circuit in the circuit set, a layout set consisting of the circuit layout of the quantum circuit using the physical bit layout of the target quantum hardware, wherein each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set;

[0034] A second obtaining module is used to obtain a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by the noise level of the target quantum hardware;

[0035] The second determination module is used to determine the quantum circuits executed in parallel and the corresponding circuit layouts from the circuit set under a target condition by using an equation constructed by the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

[0036] Another embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method for determining quantum circuits to be executed in parallel as described in any of the above embodiments is implemented.

[0037] Yet another embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the method for determining quantum circuits to be executed in parallel in any of the above embodiments.

[0038] Compared with the prior art, the present application provides a method for determining quantum circuits to be executed in parallel. The method first determines a set of circuits, and then determines a set of layouts corresponding to the quantum circuits based on the physical bit layout of the target quantum hardware. An equation is constructed according to the score of each circuit layout and the usage relationship between the quantum circuit and the circuit layout. The equation is solved under target conditions to determine the quantum circuits to be executed in parallel and the corresponding circuit layouts. A batch of quantum circuits to be executed at most simultaneously is reasonably determined based on the scores of the circuit layouts and the target conditions. This reduces the frequency of accessing the target quantum hardware, thereby improving the throughput and hardware utilization of the quantum computing platform, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A network block diagram of a quantum computing platform provided in an embodiment of the present application;

[0040] Figure 2 A flowchart of a method for determining a quantum circuit for parallel execution provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of a physical bit layout of a target quantum hardware provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of a set of topological structures corresponding to a target quantum hardware provided in an embodiment of the present application;

[0043] Figure 5 A structural diagram of a quantum circuit device for determining parallel execution provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0046] Figure 1 1 is a network block diagram of a quantum computing platform provided by an embodiment of the present application. The quantum computing platform system for implementing the method provided by the present application may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170 (including target quantum hardware), and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0047] Network 110 is a medium used to provide communication links between various devices and computers connected together in the quantum computing platform, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and their combinations. The connection method can be wired, wireless communication links or optical fiber cables, etc.

[0048] The server 120, the wireless device 130 and the client 140 are conventional data processing systems, which may contain data and applications or software tools for performing conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0049] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 163 (application 173). The application 163 (application 173) may be used to implement a quantum algorithm compiled according to the method for determining quantum circuits for parallel execution provided in an embodiment of the present application.

[0050] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0051] It should be noted that the real quantum computing platform is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical computing unit 160, which is responsible for performing classical computing and control; the quantum computing unit 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0052] The classical computing unit 160 and the quantum computing unit 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum programs through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum computing unit 170 through the network services thereon. The second device runs a quantum computer operating system, and the code of the quantum program is parsed and compiled into instructions that can be recognized and executed by the quantum processor 170 through the quantum computer operating system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0053] The computing unit of the classic processor 161 in the classic computing unit 160 is a CMOS tube based on a silicon chip. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and can be used at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor 161 is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, such as: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0054] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is the quantum bit. The input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the length of use and is not available at any time. Making full use of the quantum bit within the available length of use of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of the quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical function combinations to achieve the computing effect. Quantum computing

[0055] Based on these differences, the design of CMOS tubes by classical logic functions and the design of quantum bits by quantum logic functions are significantly and essentially different. The design of CMOS tubes by classical logic functions does not need to consider the individuality of CMOS tubes. For example, the representation of CMOS tubes in silicon chips is the individual identification, position, and usable life of each CMOS tube. Therefore, the classical algorithm composed of classical logic functions only expresses the operational relationship of the algorithm, but does not express the algorithm's dependence on individual CMOS tubes.

[0056] When quantum logic functions act on qubits, the individuality of qubits needs to be considered, such as the individual identification of the qubit in the quantum chip, its position, its relationship with surrounding qubits, and the usable time of each qubit. Therefore, the quantum algorithm composed of quantum logic functions not only expresses the computational relationship of the algorithm, but also expresses the algorithm's dependence on individual qubits.

[0057] Quantum chips can include quantum bits and channels for regulating quantum bits. Quantum logic gates are implemented through analog signals. Different combinations of analog signals are applied to quantum bits through channels for regulating quantum bits, thereby realizing quantum circuits with different functions and completing data processing. Therefore, the design of quantum logic functions acting on quantum bits (including the design of whether quantum bits are used or not and the design of the efficiency of each quantum bit) is the key to improving the computing performance of quantum computers, and special designs are required. This is also the uniqueness of quantum algorithms based on quantum logic functions, which is essentially and significantly different from classical algorithms based on classical logic functions. The above-mentioned design for quantum bits is a technical issue that ordinary computing devices do not need to consider or face.

[0058] See also Figure 2 , Figure 2 A method for determining a quantum circuit to be executed in parallel is provided in an embodiment of the present application, and the method comprises the following steps:

[0059] S201: Obtain a circuit set consisting of quantum circuits to be executed.

[0060] The circuit set is determined from the quantum circuits executed by the user request, and the circuit set can be expressed as: C = {C1, C2, ..., C N}. The quantum circuits of the circuit set satisfy the following constraints: ① The quantum circuit is the circuit that the user initiates an execution request to the quantum computing platform and hopes to be executed; ② The total number of quantum bits used by the quantum circuit does not exceed m, where m is the number of physical bits of the target quantum hardware, and the target quantum hardware is the quantum hardware that executes the quantum circuit in the quantum computing platform; ③ The quantum circuit has not been executed yet. During the specific implementation, a list is established to store the quantum circuits that need to be executed. When a task requesting the execution of a quantum circuit arrives, it is determined whether the number of quantum bits of the quantum circuit exceeds m. If not, the quantum circuit is added to the list; otherwise, the circuit is discarded and the relevant information is reported to the user. At the end of this step, a copy of the list is copied to a temporary list, and the original list is cleared at the same time. The quantum circuits in the temporary list constitute a circuit set. It should be noted that the quantum circuits mentioned in this application are all quantum logic circuits, that is, the quantum bits in the quantum circuits are logical bits.

[0061] S202: For each quantum circuit in the circuit set, using the physical bit layout of the target quantum hardware, determine a layout set consisting of the circuit layout of the quantum circuit, wherein the target quantum hardware is the quantum hardware in the quantum computing platform, and each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set.

[0062] The physical bit layout of the target quantum hardware is the way the physical qubits of the target quantum hardware are arranged in space. This layout is crucial to the realization of quantum circuits because it directly affects the interaction between qubits and the execution efficiency of quantum logic gates. Circuit layout refers to matching the quantum circuit with the physical qubits of the target quantum hardware and assigning the corresponding physical qubits to the quantum circuit. The structure of the quantum circuit is matched with the layout of the physical bits of the target quantum hardware, and the layout set can be obtained using the matching results. Specifically, the layout set can be determined based on the physical bit layout of the quantum circuit and the target quantum hardware using the Mapomatic method. The Mapomatic method is a technology used for quantum circuit layout optimization. It uses a heuristic method to search for structures that match the quantum circuit in the physical bit layout to generate a layout set.

[0063] The layout sets of different quantum circuits may be the same, or some of the circuit layouts in the layout set may be the same. The circuit layouts in the layout set of the same quantum circuit are isomorphic. i The layout set of can be expressed as L (i) Each element of L (i) An isomorphic layout of L. (i) Each element in is different, so L (i) Contains C i All different isomorphic layouts.

[0064] The topological structure of a quantum circuit can also be considered as the graph structure corresponding to the quantum circuit. The matching relationship between the topological structure of a quantum circuit and the layout of physical bits is crucial to the realization of quantum computing, which affects the execution efficiency of the quantum circuit and the performance of quantum computing. In some embodiments of the present application, the topological structure of each quantum circuit in the circuit set can be determined first, and then the layout set consisting of the circuit layout corresponding to each quantum circuit can be determined based on the matching relationship between the topological structure of each quantum circuit and the physical bit layout of the target quantum hardware. The topological structure of a quantum circuit can utilize existing methods. In this topological structure, nodes represent quantum bits, and the direction of edges represents the connection relationship between quantum bits. Specifically, the physical bit layout of the target quantum hardware is used to determine the topological structure set corresponding to the target quantum hardware; for each quantum circuit, from the topological structure set corresponding to the target quantum hardware, a topological structure identical to the topological structure of the quantum circuit is determined as the target topological structure; and the target topological structure of each quantum circuit is used to determine the layout set consisting of the circuit layout corresponding to the quantum circuit.

[0065] By splitting the physical bit layout of the target quantum hardware, we can get a corresponding topological structure set, which contains all the sub-topological structures corresponding to the target quantum hardware. For example, the physical bit layout of the target quantum hardware is as follows: Figure 3 As shown, the corresponding topological structure set is Figure 4 As shown, Figure 4 The physical bits are included from Figure 4 The topological structure set shown in FIG. 1 determines the topological structure that is the same as the topological structure of the quantum circuit as the target topological structure. When determining the target topological structure, the layout set can be determined based on the relationship between the determined target topological structure and the physical quantum bits. Specifically, for each quantum circuit, the physical bit group corresponding to the target topological structure is used as the circuit layout in the layout set corresponding to the quantum circuit. For example, if the target topological structure is Figure 4The third topology in , the determined physical bit groups are: (q1, q2), (q2, q3), (q2, q4), the physical bit group can include only one physical bit, if the target topology is Figure 4 The fourth topology in the example is: Figure 4 For the first topology structure, the determined physical bit group is (q1, q2, q3, q4).

[0066] S203: Obtaining a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by a noise level of the target quantum hardware.

[0067] The noise level is related to the physical environment. For the fixed quantum hardware, its internal physical environment is basically fixed. Therefore, the noise level of the target quantum hardware is basically fixed. The noise index of the circuit layout can be obtained in advance through hardware testing, and when the internal environment of the quantum hardware does not change significantly, the corresponding noise index remains valid. Therefore, the noise index can be used as the score of the circuit layout. The score of the circuit layout reflects the size of the noise generated by the quantum circuit corresponding to the execution of the circuit layout in the target quantum hardware. Therefore, the score of the circuit layout can be calculated by other methods. The score may not be the actual noise size generated by the circuit layout, but may be the relative size of the noise, or other values ​​that can reflect the noise size.

[0068] S204: Under a target condition, using an equation constructed by the determined score and a usage relationship between each quantum circuit and each corresponding circuit layout, determine the quantum circuits executed in parallel and the corresponding circuit layouts from the circuit set, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

[0069] The target condition is set as a constraint condition for determining the quantum circuits to be executed in parallel. Non-overlap between circuit layouts means that the physical bits occupied by the quantum circuits executed in parallel in the target quantum hardware do not overlap with each other, and the distance between the corresponding circuit layouts has an impact on the execution results of the quantum circuits within a preset range. The target condition is set so that there is a buffer distance between the circuit layouts of the two quantum circuits. The buffer distance is the distance of the circuit layout used to reduce the impact of crosstalk, specifically, it refers to the vacant physical quantum bits used to reduce the impact of crosstalk. The distance between the two quantum circuit layouts is the interval between the allocated physical quantum bit groups corresponding to the two quantum circuits, and the interval refers to the unused physical bits. Exemplarily, taking the physical bit layout of the target quantum hardware as Figure 3For example, the quantum circuit is a single-bit quantum circuit. There is serious noise between the two directly connected physical bits. The circuit layouts assigned to these two quantum circuits can only be q1 and q4, or q1 and q3, or q3 and q4. The common point of these circuit layouts is that there must be an unused physical quantum bit q2 in the middle. Compared with the physical bits connected in between, q2 blocks the two circuit layouts and acts as a gap, that is, q2 is a gap.

[0070] In the embodiment of the present application, it is not necessary to obtain the buffer distance of the two circuit layouts. When the target conditions are met, there is naturally a suitable buffer distance between the two circuit layouts. That is, the present application reduces the crosstalk phenomenon by constructing an appropriate buffer distance, but the method of constructing an appropriate buffer distance is not to calculate the buffer distance, but to always meet two constraints during the construction process: a. The two circuit layouts do not overlap; b. The distance between any quantum bit in one quantum circuit and any quantum bit in another quantum circuit satisfies that the crosstalk phenomenon will not seriously affect the execution results of the two quantum circuits. Exemplarily, the physical bits q1 and q2 constitute crosstalk, and the physical bits q1 and q3 do not constitute crosstalk. The distance between q1 and q2 will cause the crosstalk phenomenon to seriously affect the execution results of the two quantum circuits, that is, the crosstalk effect exceeds the acceptable range; the distance between q1 and q3 will not cause the crosstalk phenomenon to seriously affect the execution results of the two circuits, that is, the crosstalk effect exceeds the acceptable range. The arrangement and connection of the physical bits in the target quantum hardware are determined, and the corresponding physical environment is also fixed. Therefore, the crosstalk effect between any two physical bits on the target quantum hardware is certain and can be tested experimentally or calculated theoretically. Based on this, whether the crosstalk effect of the distance between the two circuit layouts on the execution results of the quantum circuit is within an acceptable range is also fixed and can be obtained without calculation.

[0071] The usage relationship between quantum circuits and circuit layouts can be divided into two types: use and non-use. The usage relationship can be defined as:

[0072]

[0073] x ij As the decision variable, the corresponding score is used to construct the coefficient of the decision variable. With the target condition as the constraint, the equation consisting of the solution variable and the coefficient of the decision variable is solved to determine the quantum circuit for parallel execution.

[0074] The embodiment of the present application first determines a circuit set, and then determines a layout set corresponding to the quantum circuit based on the physical bit layout of the target quantum hardware, constructs an equation according to the score of each circuit layout and the usage relationship between the quantum circuit and the circuit layout, solves the equation under the target condition, determines the quantum circuits to be executed in parallel and the corresponding circuit layout, and reasonably determines a batch of quantum circuits to be executed at most simultaneously through the scores of the circuit layout and the target condition, thereby reducing the frequency of accessing the target quantum hardware, thereby improving the throughput and hardware utilization of the quantum computing platform, and thus improving the user experience.

[0075] In some embodiments of the present application, under the target condition, using the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, determining the quantum circuits to be executed in parallel from the circuit set includes:

[0076] Determine the area of ​​each quantum circuit, where the area of ​​the quantum circuit is the number of physical bits that the quantum circuit needs to occupy;

[0077] Under target conditions, with the goal of minimizing an equation consisting of decision variables and coefficients of the decision variables, the equation is solved to determine quantum circuits to be executed in parallel, wherein the decision variables are the usage relationship between each quantum circuit and each corresponding circuit layout, and the coefficients of the decision variables are constructed using the area of ​​each quantum circuit and the determined score.

[0078] The equation can be obtained by integer linear programming modeling, and the equation obtained by modeling can be:

[0079]

[0080] Among them, c ij is the coefficient of the decision variable.

[0081] The target conditions can be:

[0082]

[0083] in, Indicates the line layout With circuit layout overlapping.

[0084] In some possible implementations of the present application, the coefficient of the decision variable constructed by the score and the area of ​​the quantum circuit may be:

[0085] c ij =q ij A i -1

[0086] Among them, c ijrepresents the variable coefficient corresponding to the circuit layout j used by quantum circuit i, q ij represents the score of quantum circuit i using circuit layout j, represents the area of ​​quantum circuit i normalized over all quantum circuits, and M is the sum of the areas of all quantum circuits.

[0087] By using the coefficients of the decision variables constructed in the above manner, the noise of the circuit layout of each quantum circuit executed in parallel can be distributed within the noise of the optimal layout of the quantum circuit.

[0088] In some possible implementations of the present application, after the quantum circuits to be executed in parallel and the corresponding circuit layouts are determined, the determined quantum circuits to be executed in parallel need to be deployed on the target quantum hardware according to the corresponding circuit layouts, so that the target quantum hardware executes the determined quantum circuits in parallel;

[0089] After receiving the information of the target quantum hardware indicating that the operation is completed, if there are quantum circuits that have not been executed, returning to the step of obtaining a circuit set consisting of quantum circuits to be executed until all quantum circuits are executed.

[0090] See also Figure 5 , Figure 5 An apparatus for determining a quantum circuit to be executed in parallel is provided in an embodiment of the present application, and the apparatus may include:

[0091] A first obtaining module 501 is used to obtain a circuit set consisting of quantum circuits to be executed;

[0092] A first determining module 502 is used to determine, for each quantum circuit in the circuit set, a layout set consisting of the circuit layout of the quantum circuit using the physical bit layout of the target quantum hardware, wherein each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set;

[0093] A second obtaining module 503 is used to obtain a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by the noise level of the target quantum hardware;

[0094] The second determination module 504 is used to determine the quantum circuits executed in parallel and the corresponding circuit layouts from the circuit set under a target condition by using an equation constructed by the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

[0095] Regarding the specific functions and effects achieved by the above-mentioned device for determining quantum circuits to be executed in parallel, reference can be made to other embodiments of the present application for comparative explanation, and no further description is given here. The various modules in the device for determining quantum circuits to be executed in parallel can be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to the above modules.

[0096] See also Figure 6 The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the method for determining parallel quantum circuits in any of the above embodiments when executing the computer program. Figure 6 , the computer device may be a classical computer. The computer device may also be a quantum computer.

[0097] The embodiments of the present application also provide a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the method for determining quantum circuits to be executed in parallel in any of the above embodiments.

[0098] The embodiments of the present application also provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to execute the method for determining quantum circuits to be executed in parallel in any of the above embodiments.

[0099] It can be understood that in the various implementations of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present application.

[0100] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0101] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0102] It can be understood that the processor of the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0103] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0104] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0105] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0108] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0109] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for determining quantum circuits executed in parallel, characterized in that: The method comprises: Obtain a circuit set consisting of quantum circuits to be executed; For each quantum circuit in the circuit set, using the physical bit layout of the target quantum hardware, determine a layout set consisting of the circuit layout of the quantum circuit, wherein the target quantum hardware is the quantum hardware in the quantum computing platform, and each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set; Obtaining a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by a noise level of a target quantum hardware; Under a target condition, quantum circuits executed in parallel and corresponding circuit layouts are determined from the circuit set using an equation constructed by the determined score and a usage relationship between each quantum circuit and each corresponding circuit layout, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

2. The method according to claim 1, characterized in that The step of determining, for each quantum circuit in the circuit set, a layout set consisting of the circuit layout of the quantum circuit using the physical bit layout of the target quantum hardware, comprises: Determining the topological structure of each quantum circuit in the circuit set; According to the matching relationship between the topological structure of each quantum circuit and the physical bit layout of the target quantum hardware, a layout set consisting of the circuit layout corresponding to each quantum circuit is determined.

3. The method according to claim 2, characterized in that The step of determining a layout set consisting of a circuit layout corresponding to each quantum circuit according to a matching relationship between the topological structure of each quantum circuit and the physical bit layout of the target quantum hardware comprises: Determine a set of topological structures corresponding to the target quantum hardware by using the physical bit layout of the target quantum hardware; For each quantum circuit, a topological structure identical to the topological structure of the quantum circuit is determined from the set of topological structures corresponding to the target quantum hardware as the target topological structure; The target topological structure of each quantum circuit is used to determine a layout set consisting of circuit layouts corresponding to the quantum circuit.

4. The method according to claim 3, characterized in that The step of using the target topological structure of each quantum circuit to determine a layout set consisting of circuit layouts corresponding to the quantum circuit comprises: For each quantum circuit, the physical bit groups corresponding to the target topological structure are used as the circuit layouts in the layout set corresponding to the quantum circuit.

5. The method according to claim 1, characterized in that The step of determining the quantum circuits to be executed in parallel and the corresponding circuit layouts from the circuit set under the target condition by using an equation constructed by the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, comprises: Determine the area of ​​each quantum circuit, where the area of ​​the quantum circuit is the number of physical bits that the quantum circuit needs to occupy; Under target conditions, with the goal of minimizing an equation consisting of decision variables and coefficients of the decision variables, the equation is solved to determine quantum circuits to be executed in parallel, wherein the decision variables are the usage relationship between each quantum circuit and each corresponding circuit layout, and the coefficients of the decision variables are constructed using the area of ​​each quantum circuit and the determined score.

6. The method according to claim 5, characterized in that The equations are constructed using integer linear programming.

7. The method according to claim 6, characterized in that The coefficients of the decision variables are: c ij =q ej A i -1 Among them, c ij represents the coefficient of the decision variable corresponding to quantum circuit i using circuit layout j, q ij represents the score of quantum circuit i using circuit layout j, represents the area of ​​quantum circuit i normalized over all quantum circuits, and M is the sum of the areas of all quantum circuits.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: When the number of quantum bits of the received quantum circuit requested to be executed exceeds the number of physical bits of the target quantum hardware, the received quantum circuit is discarded.

9. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: Deploying the determined quantum circuits to be executed in parallel onto the target quantum hardware according to the corresponding circuit layout, so that the target quantum hardware executes the determined quantum circuits in parallel; After receiving the information of completion of the operation fed back by the target quantum hardware, if there are quantum circuits that have not been executed, the method returns to the step of obtaining a circuit set consisting of quantum circuits to be executed.

10. A device for determining quantum circuits executed in parallel, characterized in that: The device comprises: A first acquisition module is used to obtain a circuit set consisting of quantum circuits to be executed; A first determination module is used to determine, for each quantum circuit in the circuit set, a layout set consisting of the circuit layout of the quantum circuit using the physical bit layout of the target quantum hardware, wherein each quantum circuit corresponds to the same topological structure as each circuit layout in its layout set; A second obtaining module is used to obtain a score of each circuit layout in the layout set of each quantum circuit, wherein the score is determined by the noise level of the target quantum hardware; The second determination module is used to determine the quantum circuits executed in parallel and the corresponding circuit layouts from the circuit set under a target condition by using an equation constructed by the determined score and the usage relationship between each quantum circuit and each corresponding circuit layout, wherein the target condition is that the circuit layouts corresponding to the quantum circuits executed in parallel do not overlap.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the method for determining quantum circuits to be executed in parallel as claimed in any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a computer, the computer executes the method for determining quantum circuits to be executed in parallel according to any one of claims 1 to 9.

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