Method, system and device for determining WCK-ON value of LPDDR chip and storage medium

Abstract

The invention discloses a method, a system and a device for determining a WCK-ON value of an LPDDR chip and a storage medium. The method comprises the following steps: acquiring a first MR value of the LPDDR chip; obtaining a second MR value of the LPDDR chip; comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; under the condition that the first comparison result represents that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode; and under the condition that the first comparison result represents that the second MR value is not updated, correcting the second MR value into the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode. The WCK-ON value determination method and device can be compatible with double-Rank and single-Rank LPDDR chips at the same time to determine the WCK-ON value, the test cost is low, the error probability caused by the scheme switching problem is reduced, and the accuracy of WCK-ON value determination is improved.

Description

Technical Field

[0001] The present invention relates to the field of memory testing technology, and in particular to a method, system, device and storage medium for determining a WCK-ON value of an LPDDR chip. Background Art

[0002] LPDDR (Low-Power Double Data Rate SDRAM) is a memory device used in electronic devices with strict power consumption requirements, such as mobile devices and IoT devices. While meeting the device's requirements for memory capacity and performance, it focuses on reducing power consumption and extending the device's battery life.

[0003] Existing LPDDR chips are usually designed with a dual-channel architecture or a single-channel architecture, that is, one LPDDR chip includes two channels (i.e., dual-rank) or one channel (i.e., single-rank). Before initialization, the LPDDR chip needs to obtain the WCK-ON (Write Clock-ON) value, so as to initialize the LPDDR chip according to the WCK-ON value. However, there is currently a lack of a universal solution to be compatible with both single-rank and dual-rank WCK-ON acquisition. When facing LPDDR chips with different rank configurations, different initialization schemes need to be formulated for single-rank and dual-rank to obtain WCK-ON values ​​and initialize, which not only increases the testing cost, but also easily increases the probability of error due to problems such as scheme switching, reducing the accuracy of WCK-ON value determination. Summary of the invention

[0004] In view of this, an embodiment of the present invention aims to provide a method, system, device and storage medium for determining the WCK-ON value of an LPDDR chip, which can be compatible with both single-rank and dual-rank LPDDR chips, accurately test the WCK-ON value of the LPDDR chip, and have low testing cost.

[0005] In a first aspect, an embodiment of the present invention provides a method for determining a WCK-ON value of an LPDDR chip, comprising: Acquire a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to the first Rank; Acquire a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; Comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; When the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, a first CHS mode is determined according to the first MR value and the second MR value, and a first WCK-ON value of the LPDDR chip is determined according to the first CHS mode, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between the ranks; When the first comparison result indicates that the second MR value has not been updated, the second MR value is corrected to the first MR value, a second CHS mode is determined according to the second MR value, and a second WCK-ON value of the LPDDR chip is determined according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

[0006] In some optional embodiments, when the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value includes: When the first comparison result indicates that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, configuring the LPDDR chip to a dual Rank mode; Obtain the first synchronization coordination table corresponding to the dual Rank mode; The first CHS mode is determined according to the first synchronization coordination table, the first MR value, and the second MR value.

[0007] In some optional embodiments, determining the first CHS mode according to the first synchronization coordination table, the first MR value, and the second MR value includes: Determine the first configuration information and the second configuration information according to the first MR value, the second MR value and a preset configuration table; Determine the first synchronization coordination information according to the first configuration information and the second configuration information; Searching the first synchronization coordination table for a first entry that matches the first synchronization coordination information; The CHS mode corresponding to the first entry is configured as the first CHS mode.

[0008] In some optional embodiments, the method further includes: When the first comparison result indicates that the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, the first CHS mode is configured as a first mode, and the first WCK-ON value is configured as a first value according to the first mode; When the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, the first CHS mode is configured as a second mode, and the first WCK-ON value is configured as a second value according to the second mode.

[0009] In some optional embodiments, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode includes: When the second MR value is equal to the preset MR value, configuring the second CHS mode to the second mode, and configuring the second WCK-ON value to a second value according to the second mode; When the second MR value is not equal to the preset MR value, the second CHS mode is configured as the first mode, and the second WCK-ON value is configured as a first value according to the first mode.

[0010] In some optional embodiments, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode includes: When the second MR value is equal to the preset MR value, configuring the second CHS mode to the second mode, and configuring the second WCK-ON value to a second value according to the second mode; When the second MR value is not equal to the preset MR value, the second CHS mode is configured as the first mode, and the second WCK-ON value is configured as a first value according to the first mode.

[0011] In some optional embodiments, determining the second CHS mode according to the second synchronization coordination table and the second MR value includes: Determine the second synchronization coordination information according to the second MR value and a preset configuration table; Searching the second synchronization coordination table for a second entry matching the second synchronization coordination information; The CHS mode corresponding to the second entry is configured as the second CHS mode.

[0012] In a second aspect, an embodiment of the present invention provides a system for determining a WCK-ON value of an LPDDR chip, including: The first module is used to obtain a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; The second module is used to obtain a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; A third module, configured to compare the first MR value and the second MR value with a preset MR value to obtain a first comparison result; a fourth module, configured to determine a first CHS mode according to the first MR value and the second MR value, and determine a first WCK-ON value of the LPDDR chip according to the first CHS mode, when the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between ranks; The fifth module is used to correct the second MR value to the first MR value when the first comparison result indicates that the second MR value is not updated, determine a second CHS mode according to the second MR value, and determine a second WCK-ON value of the LPDDR chip according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

[0013] In a third aspect, an embodiment of the present invention provides a memory testing device, which is applied to a smart card, and the device includes: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method as described above.

[0014] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to perform the method as described above.

[0015] Implementation of the embodiments of the present invention includes the following beneficial effects: The embodiments of the present invention provide a method for determining a WCK-ON value of an LPDDR chip, including: obtaining a first MR value of the LPDDR chip, the first MR value representing first configuration information corresponding to a first Rank; obtaining a second MR value of the LPDDR chip, the second MR value representing second configuration information corresponding to a second Rank; comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; when the first comparison result represents that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, the first CHS mode indicating that the LPDDR chip has dual Ranks and first synchronization coordination information between Ranks; when the first comparison result represents that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, the second CHS mode indicating that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks. After obtaining the first MR value and the second MR value of the first Rank and the second Rank, they are compared with the preset MR value to determine whether the LPDDR chip has dual Rank or single Rank, and determine the corresponding first WCK-ON value and second WCK-ON value, so that the WCK-ON value can be determined for LPDDR chips that are compatible with both dual Rank and single Rank. There is no need to formulate different initialization schemes for single Rank and dual Rank respectively, the testing cost is low, the error probability caused by problems such as scheme switching is reduced, and the accuracy of WCK-ON value determination is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic flow chart of the steps of a method for determining a WCK-ON value of an LPDDR chip provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a first Rank and a second Rank of an LPDDR chip provided by an embodiment of the present invention; Figure 3 It is a structural block diagram of a system for determining a WCK-ON value of an LPDDR chip provided by an embodiment of the present invention; Figure 4 It is a structural block diagram of a memory testing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] An embodiment of the present invention provides a method for determining a WCK-ON value of an LPDDR chip, comprising: obtaining a first MR value of the LPDDR chip, the first MR value representing first configuration information corresponding to a first Rank; obtaining a second MR value of the LPDDR chip, the second MR value representing second configuration information corresponding to a second Rank; comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; when the first comparison result represents that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, the first CHS mode indicating that the LPDDR chip has dual Ranks and first synchronization coordination information between Ranks; when the first comparison result represents that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, the second CHS mode indicating that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks. After obtaining the first MR value and the second MR value of the first Rank and the second Rank, they are compared with the preset MR value to determine whether the LPDDR chip has dual Rank or single Rank, and determine the corresponding first WCK-ON value and second WCK-ON value, so that the WCK-ON value can be determined for LPDDR chips that are compatible with both dual Rank and single Rank. There is no need to formulate different initialization schemes for single Rank and dual Rank respectively, the testing cost is low, the error probability caused by problems such as scheme switching is reduced, and the accuracy of WCK-ON value determination is improved.

[0020] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0021] like Figure 1As shown, an embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, which includes the following steps.

[0022] S100, obtaining a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; S200, obtaining a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; S300, comparing the first MR value and the second MR value with the preset MR value to obtain a first comparison result; S400, when the first comparison result indicates that the first MR value and / or the second MR value are equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, the first CHS mode indicating that the LPDDR chip has dual ranks and first synchronization coordination information between the ranks; S500. When the first comparison result indicates that the second MR value is not updated, the second MR value is corrected to the first MR value, a second CHS mode is determined according to the second MR value, and a second WCK-ON value of the LPDDR chip is determined according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between the Ranks.

[0023] Specifically, refer to Figure 2 In the LPDDR chip (this application takes LPDDR4 / 5 as an example), the MR (Mode Register) value plays a key role. It stores the configuration information of each Rank (storage channel) inside the LPDDR chip. The first MR value here corresponds to the first configuration information of the first Rank, and the second MR value corresponds to the second configuration information of the second Rank. These configuration information covers many aspects, such as working mode (different operating settings such as high-performance mode and low-power mode), timing parameters of data transmission (including clock signal timing of read and write operations, data retention time, etc.), address mapping method (determines the corresponding relationship between the storage location of data in the storage channel and the external address) and related settings for working with other components, etc. The specific configuration information is not limited here. By obtaining the first MR value and the second MR value, the current specific configuration status of the first Rank and the second Rank is determined.

[0024] The preset MR value is a reference value pre-set based on the standard specifications of the LPDDR chip, conventional best practices, and design expectations, such as 0XFFFF. It is set according to actual needs and is not limited here. The preset MR value meets the configuration state required for normal and stable operation of the chip. For example, for dual-rank collaborative work or single-rank independent operation in common application scenarios, there will be a default, verified configuration state, and the MR value corresponding to this state is set to the preset MR value. By comparing it with it, it can be quickly determined whether the actual first MR value and the second MR value are within the expected reasonable range, and whether corresponding adjustments are needed or further acquisition of the WCK-ON value for initialization.

[0025] The first MR value and the second MR value are respectively compared with the preset MR value one by one. For example, the data bits corresponding to the working modes are compared to see whether they are the same, the timing parameter bits are consistent, etc., or the overall data bits are compared one by one, and the specific comparison method is not limited here. The first comparison result may present a variety of situations, such as the first MR value is equal to the preset MR value and the second MR value is not equal, or both are equal to the preset MR value, or both are not equal, etc.

[0026] When the first comparison result shows that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, it means that the initial configuration of at least one Rank meets normal expectations, and the second Rank has a new configuration change, indicating that the LPDDR chip is running in dual Rank mode (with dual Rank), and the first WCK-ON value of the dual Rank of the LPDDR chip is normal, and the initialization of the LPDDR chip can be performed or ended as needed.

[0027] The first CHS (Channel Synchronization) mode is determined based on the first MR value and the second MR value, because the configuration of both ranks has an impact on the synchronization coordination between the two ranks. For example, some parameters in the first MR value may specify some characteristics of the first Rank in data transmission (such as data transmission priority, acceptable clock delay range, etc.), and the updated part in the second MR value reflects the new requirements or changes of the second Rank (such as changes in data width or read and write order, etc.). It is necessary to combine this information to determine the coordination method between the two ranks. Through the mapping relationship between the configuration information and the CHS mode, the key configuration parameters extracted from the first MR value and the second MR value are matched according to the mapping relationship to determine the first CHS mode. This mode indicates in detail the first synchronization coordination information between the ranks of the LPDDR chip in the dual-rank state, such as the clock synchronization method of the two ranks (strictly the same frequency and phase, or allowing a certain phase difference, etc.), the order of data selection, and some interaction rules during data transmission.

[0028] The first WCK-ON value is determined based on the determined first CHS mode, because the WCK-ON value (write clock turn-on value) is closely related to the synchronization and coordination between the ranks. In the dual-rank mode, in order to ensure that the data can be accurately written into the storage units corresponding to the two ranks at the same time, it is necessary to accurately set the first WCK-ON value according to the synchronization and coordination requirements specified in the first CHS mode. For example, if the first CHS mode requires strict clock synchronization and the data is written at a specific clock edge, then the first WCK-ON value must be accurate to the specific time point in the corresponding clock cycle to ensure that the write clock signal is turned on at the right time so that the two ranks can cooperate to complete the data writing operation; if the first CHS mode allows a certain clock phase difference and a looser data writing time window, the value range of the first WCK-ON value will be adjusted accordingly, but it must still meet the accuracy and synchronization requirements of dual-rank data writing. The first WCK-ON value is represented by a binary code, and the specific representation method is not limited here.

[0029] When the first comparison result shows that the second MR value is not updated, it means that the second Rank is not enabled or does not exist (that is, the LPDDR chip is in single Rank mode at this time). Therefore, the second Rank is assumed to be enabled or exists, and the second MR value of the virtual second Rank is corrected to the first MR value, so that the second WCK-ON value can be determined by the first MR value of the first Rank itself, that is, it complies with the determination method of the dual Rank mode and does not affect the reading of the WCK-ON value of the single Rank.

[0030] In some embodiments, the process of determining the second CHS mode is as follows: the second CHS mode is determined according to the revised second MR value (which is the same as the first MR value at this time). This mode mainly reflects the second synchronization coordination information between the ranks of the LPDDR chip when it is in a single Rank (actually, it is the coordination of the single Rank itself at this time, and the second Rank is a virtual Rank). Since the single Rank work has different characteristics and requirements in terms of data transmission and clock synchronization compared to the dual Rank collaborative work, the corresponding second CHS mode will be determined according to the relevant rules and coordination methods when the single Rank is running. For example, in the single Rank mode, data transmission only needs to consider its own read and write timing and internal coordination, and does not need to involve synchronization issues with another Rank. The coordination rules for the control of the clock signal, data selection, etc. will be relatively simple and direct. The second CHS mode is determined based on these rules and the revised second MR value information.

[0031] In some embodiments, the process of determining the second WCK-ON value: Similarly, the second WCK-ON value is determined based on the determined second CHS mode. In the single Rank mode, the activation time of the write clock mainly focuses on meeting the read and write timing requirements of the Rank itself, and there is no need to consider the synchronization problem with another Rank, so the determination of the second WCK-ON value will focus more on ensuring that the data can be accurately and efficiently written to the storage unit within this single Rank. For example, according to the parameters such as the read and write speed and data retention time of the single Rank, combined with the coordination rules for the clock signal and data operation in the second CHS mode, a suitable second WCK-ON value is calculated or set to ensure that the data write operation in the single Rank mode can proceed smoothly.

[0032] In some optional embodiments, the method further includes: when the first comparison result indicates that the first MR value is not equal to the preset MR value, and the second MR value is not equal to the preset MR value, and the second MR value is updated, configuring the first CHS mode as the first mode, and configuring the first WCK-ON value as the first value according to the first mode; when the first comparison result indicates that the first MR value and / or the second MR value are equal to the preset MR value, and the second MR value is updated, configuring the first CHS mode as the second mode, and configuring the first WCK-ON value as the second value according to the second mode.

[0033] Specifically, when the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, it indicates that the current configuration information of the first Rank and the second Rank (represented by the first MR value and the second MR value, respectively) are inconsistent with the preset standard configuration (preset MR value). However, the configuration of the second Rank is updated, which means that the LPDDR chip has dual ranks, and the configuration states of the first Rank and the second Rank deviate from the conventional expectations, and corresponding initialization is required. The first CHS mode is configured as the first mode, and the first mode can be a low-level signal mode (specifically not limited). The first CHS mode is set to the first mode by writing specific instructions or parameters to the relevant control register in the LPDDR chip. The settings of these instructions and parameters follow the communication protocol and operation specifications specified by the chip manufacturer, involving the code for specifying the mode selection and some basic parameter settings matching the mode, such as the approximate range of clock synchronization, the default mode of data strobe, etc., so as to enable the synchronization coordination mechanism in the first mode. Once the first mode is determined, the first WCK-ON value needs to be configured accordingly to be the first value. Specifically, in the first mode, the first WCK-ON value is configured to be “0”, so that the LPDDR chip is initialized according to the first WCK-ON value.

[0034] When the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, it indicates that at least one Rank configuration meets the preset standard configuration, and the second Rank configuration has been updated. Part of the overall LPDDR chip configuration is in a normal expected state, and the second Rank is updated, which means that the LPDDR chip has dual Ranks, and the configuration state of the first Rank and / or the second Rank meets normal expectations. The first CHS mode is configured as the second mode, which can be a high-level mode, and there is no specific limitation. The second mode is generally an optimized synchronization and coordination mode suitable for scenarios where some Ranks meet the preset standards and there are Rank updates. It will make full use of the advantages of the Rank configuration that meets the standards, and combine the content of the second Rank update to achieve more efficient and accurate synchronization and coordination between the dual Ranks.

[0035] After the second mode is determined, the first WCK-ON value is configured to be a second value, and the specific second value may be "1", which is not limited here. The LPDDR chip may be selectively initialized or exited from initialization according to the second value, which is not limited here.

[0036] In some optional embodiments, the second CHS mode is determined according to the second MR value, and the second WCK-ON value of the LPDDR chip is determined according to the second CHS mode, including: when the second MR value is equal to the preset MR value, the second CHS mode is configured as the second mode, and the second WCK-ON value is configured as the second value according to the second mode; when the second MR value is not equal to the preset MR value, the second CHS mode is configured as the first mode, and the second WCK-ON value is configured as the first value according to the first mode.

[0037] Specifically, when the second MR value is equal to the preset MR value, it means that the configuration of the second Rank is in a standard state that meets conventional expectations, and the second CHS mode is configured as the second mode. When the second MR value is not equal to the preset MR value, it means that the configuration of the second Rank does not meet conventional expectations, and the second CHS mode is configured as the first mode. More accurate and efficient synchronization and coordination of LPDDR chips in a single Rank (the second Rank is a virtual Rank, equivalent to single Rank operation) or between Ranks (self-coordination situation) is achieved. The CHS mode of the single-Rank LPDDR chip is determined, and then the second WCK-ON value is determined. According to the judgment criteria of the LPDDR chip in dual Rank, when the first MR and / or the second MR is equal to the preset MR value, the first CHS mode is configured as the second mode; when processing the single Rank situation, a virtual second Rank is cleverly established, and the second MR value is configured as the first MR value, so that the original judgment rules for dual Rank can be applied to the single Rank scenario. A unified processing framework is logically constructed, so that single Rank and dual Rank follow similar rules in determining configuration parameters (especially CHS mode and subsequent WCK-ON value determination), reducing the complexity of designing different judgment and configuration methods for different working modes / storage structures (single Rank or dual Rank). Therefore, when the LPDDR chip is in single Rank, a virtual second Rank is established and the second MR value is configured as the first MR value, so that the judgment rules of the dual Rank are applicable to the single Rank, thereby being compatible with both single Rank and dual Rank LPDDR chips for WCK-ON value testing, with low testing costs.

[0038] In some optional embodiments, when the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, the first CHS mode is determined according to the first MR value and the second MR value, including: when the first comparison result indicates that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, configuring the LPDDR chip to the dual Rank mode; obtaining a first synchronization coordination table corresponding to the dual Rank mode; determining the first CHS mode according to the first synchronization coordination table, the first MR value and the second MR value.

[0039] Specifically, when the first comparison result shows that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, it means that at least part of the configuration state of the chip is in line with conventional expectations (that is, the configuration of at least one Rank is consistent with the preset standard), and at the same time, the second Rank has a new configuration change. Then the LPDDR chip operates in dual-rank mode, and needs to coordinate the work between the two ranks according to their respective states.

[0040] The first synchronization coordination table corresponding to the dual-rank mode is a synchronization coordination table for the LPDDR chip between the ranks when the dual-rank operation is in progress. This table records in detail the correspondence between different rank configurations (specifically different MR value combinations and different settings of parameters related to each rank) and the specific synchronization coordination mode (i.e., CHS mode) of the LPDDR chip in the dual-rank mode, and also covers many detailed parameter settings related to the dual-rank collaborative work. For example, the table contains information about the clock synchronization method between ranks (strictly the same frequency and same phase synchronization, or synchronization that allows a certain phase difference, etc.), the coordination mechanism of the data selection signal (how to ensure accurate transmission and switching of data between the two ranks), the order of read and write operations, and the corresponding time interval requirements, etc., aiming to provide a comprehensive and accurate guidance basis for achieving efficient and stable data processing in the dual-rank mode, and to help users quickly determine the appropriate synchronization coordination mode and related parameters based on the actual rank configuration.

[0041] After obtaining the first synchronization coordination table, it is necessary to determine the first CHS mode based on the current first MR value and the second MR value. First, each key information bit in the first MR value and the second MR value is analyzed in detail, because these information bits carry specific details about the current configuration of the two Ranks. For example, certain specific bits in the first MR value represent the first Rank's setting of the data transmission rate, the accuracy requirements of clock synchronization, or the priority of read and write operations; similarly, the updated part of the second MR value also contains key information similar to the new configuration of the second Rank, such as the changed data width, the new clock mode, or the different address mapping method. Then, these key configuration information extracted from the first MR value and the second MR value are fully matched and searched with the content in the first synchronization coordination table. According to the corresponding relationship specified in the table, carefully compare each parameter. When a record is found, all its parameters are completely consistent with the key configuration information extracted from the two MR values. The CHS mode corresponding to the record is the first CHS mode that needs to be determined. For example, assuming that the information parsed from the first MR value and the second MR value indicates that the first Rank adopts a higher data transmission rate and a looser clock synchronization method, the data width after the second Rank is updated is a specific value and the read and write operations have a specific order, by searching for the corresponding entries that meet these conditions in the first synchronization coordination table, if the corresponding entry in the table shows that the corresponding CHS mode in this case is "asynchronous data transmission, loose clock synchronization (the phase difference allowable range is ±5ns) and specific read and write order" mode, then it can be determined that this is the first CHS mode in the current situation. Subsequently, based on this determined first CHS mode, other key parameters such as the first WCK-ON value adapted to it can be further determined to ensure that the chip can perform stable data read and write operations in dual Rank mode according to accurate synchronization coordination rules.

[0042] In some optional embodiments, a first CHS mode is determined according to a first synchronization coordination table, a first MR value, and a second MR value, including: determining first configuration information and second configuration information according to the first MR value, the second MR value, and a preset configuration table; determining first synchronization coordination information according to the first configuration information and the second configuration information; searching the first synchronization coordination table for a first entry that matches the first synchronization coordination information; and configuring the CHS mode corresponding to the first entry as the first CHS mode.

[0043] Specifically, the preset configuration table is a reference table for parsing the specific configuration meaning represented by the MR value. It establishes a mapping relationship between each bit or bit segment in the MR value and the actual chip configuration parameters, covering many aspects of configuration information such as working mode, data transmission rate, clock synchronization mode, address mapping rules, etc. Through this table, the abstract MR value presented in binary form can be converted into intuitive and understandable specific configuration content, so as to obtain the detailed configuration corresponding to each Rank. For the first MR value, according to the preset configuration table, check the specific configuration meaning corresponding to the corresponding bit combination. For example, if a few bits of binary values ​​indicate that the data transmission rate of the first Rank is 1600Mbps per second according to the mapping relationship of the preset configuration table, and the other bits indicate that the clock synchronization method adopted is a loose synchronization mode that allows a certain phase difference, etc., by interpreting it bit by bit or segment by segment, the complete first configuration information of the first Rank can be determined, which includes specific parameter settings involving data reading and writing, synchronization coordination, etc. Similarly, the second MR value is also parsed according to the preset configuration table. Since the second MR value represents the configuration of the second Rank and is updated, the parsed second configuration information will reflect its latest settings, such as new data width, different read and write orders, etc. The first configuration information and the second configuration information are clarified respectively through the first MR value, the second MR value and the preset configuration table.

[0044] The first configuration information and the second configuration information contain many specific parameter settings of the two ranks, while the first synchronization and coordination information extracts the key contents closely related to how to synchronize and coordinate data reading and writing operations between the two ranks from the perspective of the overall collaborative work of the two ranks. Comprehensively consider multiple factors such as the differences in the requirements of the two ranks in clock synchronization, the interactive mode of data transmission, the order of read and write operations, and the guarantee mechanism for data accuracy and integrity. For example, the first configuration information shows that the data transmission rate of the first Rank is faster, but the clock synchronization accuracy requirement is relatively loose, while the second configuration information shows that the data width of the second Rank has changed and there are specific requirements for the read and write order. Based on these situations, the first synchronization and coordination information determined is "the two ranks use asynchronous data transmission, clock synchronization allows a certain phase difference, data transmission must be carried out in the order of the second Rank's priority reading and writing, and a specific verification mechanism is used to ensure data accuracy during the transmission process." Through the integration and analysis of the configuration information of the two ranks, the key coordination requirements for their collaborative work, that is, the first synchronization and coordination information, are sorted out, and matching entries are found in the first synchronization and coordination table.

[0045] The first synchronization coordination table is a pre-arranged table that records the correspondence between different synchronization coordination situations and corresponding CHS modes, covering the synchronization coordination modes corresponding to various possible dual-Rank configuration combinations. In this table, search for the first entry that matches the first synchronization coordination information to find the specific record entry that meets the requirements for the current collaborative work between the two ranks. During the search, it is necessary to compare each key element in the first synchronization coordination information, such as clock synchronization mode, data transmission sequence, data verification mechanism, etc., with the corresponding content of each entry in the table one by one to find the matching entry. After finding the matching first entry, configure its corresponding CHS mode to the first CHS mode. In the dual-Rank mode, the LPDDR chip can perform synchronization coordination and data reading and writing operations between ranks according to the accurate rules specified by the first CHS mode, ensuring that the two ranks can work together efficiently and stably, meeting the system's data processing requirements for the LPDDR chip in the dual-Rank application scenario, ensuring accurate transmission and storage of memory data, and improving the operating performance and reliability of the entire system.

[0046] In some optional embodiments, when the first comparison result indicates that the second MR value has not been updated, the second MR value is corrected to the first MR value, and the second CHS mode is determined according to the second MR value, including: when the first comparison result indicates that the second MR value has not been updated, configuring the LPDDR chip to a single Rank mode; correcting the second MR value to the first MR value based on the single Rank mode so that the second MR value is equal to the first MR value; obtaining a second synchronization coordination table corresponding to the single Rank mode; and determining the second CHS mode according to the second synchronization coordination table and the second MR value.

[0047] Specifically, when the first comparison result indicates that the second MR value has not been updated, the LPDDR chip is configured to the single Rank mode. After the single Rank mode is determined, the second MR value is corrected to the first MR value to ensure that the two ranks (although it is running in the single Rank mode at this time, there are originally two concepts of Rank, and the second Rank is a virtual Rank) are consistent in basic configuration, so that the single Rank LPDDR chip is applicable to the WCK-ON value determination method of the dual Rank LPDDR chip. The second synchronization coordination table corresponding to the single Rank mode is a reference table specially formulated for the chip in the single Rank operation, which records the correspondence between different MR values ​​(here the unified MR value after correction) and the specific synchronization coordination mode of the LPDDR chip (i.e., the second CHS mode) in the single Rank mode, as well as the relevant detailed parameter settings. The table covers many aspects such as the clock synchronization method within a single Rank (although there is no synchronization problem with another Rank, there are corresponding requirements for its own internal clock management), the coordination mechanism of the data selection signal (to ensure that the data is accurately transmitted and processed within this unique Rank), the order of read and write operations and the time interval requirements. It aims to provide a comprehensive and accurate guide for LPDDR chips to achieve efficient and stable data processing in single Rank mode, and help users quickly determine the appropriate synchronization coordination mode and related parameters based on the actual MR value.

[0048] After obtaining the second synchronization coordination table, it is necessary to determine the second CHS mode based on the current corrected second MR value. First, the key information bits in the second MR value must be parsed, because these information bits carry specific configuration details about the current unique Rank (equivalent to single Rank operation after configuration adjustment). For example, certain specific bits represent information such as data transmission rate, clock synchronization accuracy requirements, or read and write operation priorities. By interpreting the method specified in the chip specifications, the meanings represented by these binary bits are extracted and converted into specific configuration parameters. Then, these parsed key configuration parameters are matched and searched with the contents in the second synchronization coordination table. According to the corresponding relationship specified in the table, when the corresponding record is found, the CHS mode corresponding to the record is the second CHS mode that needs to be determined. For example, the information parsed from the second MR value shows that the data transmission rate is 1200Mbps, the clock synchronization adopts a stricter internal synchronization method, and the read and write operations are in the order of write first and read later. By searching the second synchronization coordination table for the corresponding entries that meet these conditions, if the corresponding entry in the table shows that the corresponding second CHS mode in this case is "strict internal clock synchronization, write first and read later, specific data selection mechanism" mode, then it can be determined that this is the second CHS mode in the current situation. Subsequently, based on this determined second CHS mode, other key parameters such as the second WCK-ON value adapted to it can be further determined to ensure that the chip can perform stable data read and write operations in single Rank mode according to accurate synchronization coordination rules.

[0049] In some optional embodiments, determining the second CHS mode according to the second synchronization coordination table and the second MR value includes: determining the second synchronization coordination information according to the second MR value and the preset configuration table; searching the second synchronization coordination table for a second entry matching the second synchronization coordination information; and configuring the CHS mode corresponding to the second entry as the second CHS mode.

[0050] Specifically, the second synchronization coordination table is formulated by LPDDR for the single Rank mode of the chip, and records the mapping relationship between various synchronization coordination information combinations and corresponding CHS (Channel Synchronization) modes under the single Rank operation. The table covers the CHS modes corresponding to different data transmission rates, different clock synchronization modes, and various read and write sequences, providing a reference for accurately determining the specific synchronization coordination mode of the chip in the single Rank mode. When searching for the second entry matching the second synchronization coordination information in the table, it is necessary to compare each key element in the previously determined second synchronization coordination information, such as data transmission rate, clock synchronization mode, read and write operation sequence, etc., with the corresponding content of each entry in the table one by one. The matching second entry is accurately found in the second synchronization coordination table, and its corresponding CHS mode is configured as the second CHS mode. This enables the LPDDR chip to perform internal data reading and writing, clock synchronization and other operations in the single Rank mode according to the rules specified by the accurate second CHS mode, ensuring that data can be efficiently and stably transmitted and processed in this unique Rank, and avoiding data errors, low read and write efficiency and other problems due to improper synchronization coordination. It meets the system's requirement for determining the WCK-ON value of the LPDDR chip in a single-rank application scenario, thereby ensuring the initialization accuracy of the single-rank LPDDR chip.

[0051] Implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, including: obtaining a first MR value of the LPDDR chip, the first MR value representing first configuration information corresponding to a first Rank; obtaining a second MR value of the LPDDR chip, the second MR value representing second configuration information corresponding to a second Rank; comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; when the first comparison result represents that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, the first CHS mode indicating that the LPDDR chip has dual Ranks and first synchronization coordination information between Ranks; when the first comparison result represents that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, the second CHS mode indicating that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks. After obtaining the first MR value and the second MR value of the first Rank and the second Rank, they are compared with the preset MR value to determine whether the LPDDR chip has dual Rank or single Rank, and determine the corresponding first WCK-ON value and second WCK-ON value, so that the WCK-ON value can be determined for LPDDR chips that are compatible with both dual Rank and single Rank. There is no need to formulate different initialization schemes for single Rank and dual Rank respectively, the testing cost is low, the error probability caused by problems such as scheme switching is reduced, and the accuracy of WCK-ON value determination is improved.

[0052] Second, refer to Figure 3 , an embodiment of the present invention provides a system for determining a WCK-ON value of an LPDDR chip, comprising: The first module is used to obtain a first storage capacity of the LPDDR chip, where the first storage capacity represents the storage capacity corresponding to the first Rank; The second module is used to obtain a second storage capacity of the LPDDR chip, where the second storage capacity represents the storage capacity corresponding to the second Rank; A third module, configured to compare the first storage capacity and the second storage capacity with the preset storage capacity respectively to obtain a first comparison result; A fourth module is used to obtain a first EMI value and a second EMI value according to the first comparison result, a first storage table and a second storage table, wherein the first storage table represents a relationship table between the first parameter value and the storage capacity, the second storage table represents a relationship table between the second parameter value and the storage capacity, the first EMI value represents the EMI value of the first Rank, and the second EMI value represents the EMI value of the second Rank; The fifth module is used to determine the EMI value of the LPDDR chip according to the first EMI value and the second EMI value.

[0053] It can be seen that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0054] Thirdly, refer to Figure 4 , an embodiment of the present invention provides a memory testing device, comprising: at least one processor; at least one memory for storing at least one program; When at least one program is executed by at least one processor, the at least one processor implements the above method.

[0055] It can be seen that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0056] In a fourth aspect, in addition, the embodiments of the present application further disclose a computer program product or a computer program, which is stored in a computer storable medium. The processor of a computer device can read the computer program from a computer readable storage medium, and the processor executes the computer program so that the computer device executes the above method or the above system. Similarly, the contents in the above method embodiments are all applicable to the storage medium embodiments, and the functions specifically implemented by the storage medium embodiments are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0057] It is understood that all or some steps and systems in the disclosed method above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as processors, such as software executed by a central processing unit, a digital information processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, program modules, or other data in modulated data information such as carrier waves or other transport mechanisms, and may include any information delivery media.

[0058] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A method for determining the WCK-ON value of an LPDDR chip, characterized in that: include: Acquire a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to the first Rank; Acquire a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; Comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; When the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, a first CHS mode is determined according to the first MR value and the second MR value, and a first WCK-ON value of the LPDDR chip is determined according to the first CHS mode, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between the ranks; When the first comparison result indicates that the second MR value has not been updated, the second MR value is corrected to the first MR value, a second CHS mode is determined according to the second MR value, and a second WCK-ON value of the LPDDR chip is determined according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

2. The method according to claim 1, characterized in that: The determining a first CHS mode according to the first MR value and the second MR value when the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated includes: When the first comparison result indicates that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, configuring the LPDDR chip to a dual Rank mode; Obtain the first synchronization coordination table corresponding to the dual Rank mode; The first CHS mode is determined according to the first synchronization coordination table, the first MR value, and the second MR value.

3. The method according to claim 2, characterized in that The determining the first CHS mode according to the first synchronization coordination table, the first MR value and the second MR value includes: Determine the first configuration information and the second configuration information according to the first MR value, the second MR value and a preset configuration table; Determine the first synchronization coordination information according to the first configuration information and the second configuration information; Searching the first synchronization coordination table for a first entry that matches the first synchronization coordination information; The CHS mode corresponding to the first entry is configured as the first CHS mode.

4. The method according to claim 1, characterized in that The method further comprises: When the first comparison result indicates that the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, configuring the first CHS mode as the first mode, and configuring the first WCK-ON value as the first value according to the first mode; When the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, the first CHS mode is configured as a second mode, and the first WCK-ON value is configured as a second value according to the second mode.

5. The method according to claim 4, characterized in that The determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, includes: When the second MR value is equal to the preset MR value, configuring the second CHS mode to the second mode, and configuring the second WCK-ON value to a second value according to the second mode; When the second MR value is not equal to the preset MR value, the second CHS mode is configured as the first mode, and the second WCK-ON value is configured as a first value according to the first mode.

6. The method according to claim 1, characterized in that When the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, and determining a second CHS mode according to the second MR value, includes: When the first comparison result indicates that the second MR value is not updated, configuring the LPDDR chip to a single Rank mode; Correcting the second MR value to the first MR value based on a single Rank mode, so that the second MR value is equal to the first MR value; Obtain the second synchronization coordination table corresponding to the single Rank mode; The second CHS mode is determined according to the second synchronization coordination table and the second MR value.

7. The method according to claim 6, characterized in that The determining the second CHS mode according to the second synchronization coordination table and the second MR value includes: Determine the second synchronization coordination information according to the second MR value and a preset configuration table; Searching the second synchronization coordination table for a second entry matching the second synchronization coordination information; The CHS mode corresponding to the second entry is configured as the second CHS mode.

8. A system for determining the WCK-ON value of an LPDDR chip, characterized in that: include: The first module is used to obtain a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; The second module is used to obtain a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; A third module, configured to compare the first MR value and the second MR value with a preset MR value to obtain a first comparison result; a fourth module, configured to determine a first CHS mode according to the first MR value and the second MR value, and determine a first WCK-ON value of the LPDDR chip according to the first CHS mode, when the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between ranks; The fifth module is used to correct the second MR value to the first MR value when the first comparison result indicates that the second MR value is not updated, determine a second CHS mode according to the second MR value, and determine a second WCK-ON value of the LPDDR chip according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

9. A memory testing device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

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