Method, System, Device and Storage Medium for Determining WCK-ON Value of an LPDDR Chip

Abstract

The present invention discloses a method, system, device and storage medium for determining the WCK-ON value of an LPDDR chip. The method includes: obtaining a first MR value of the LPDDR chip; obtaining a second MR value of the LPDDR chip; respectively comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; in the case where the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode; in the case where the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode. It can be compatible with both dual-Rank and single-Rank LPDDR chips to determine the WCK-ON value, with low test cost, reduce the error probability caused by the problem of scheme switching, and improve the accuracy of determining the WCK-ON value.

Description

Technical Field

[0001] The present invention relates to the technical field of memory testing, and particularly to a method, system, device and storage medium for determining the WCK-ON value of an LPDDR chip. Background Art

[0002] LPDDR (Low-Power Double Data Rate SDRAM) is a memory used in electronic devices with strict power consumption requirements such as mobile devices and Internet of Things devices; while meeting the device's memory capacity and performance requirements, it focuses on reducing power consumption and extending the device's battery life.

[0003] Existing LPDDR chips are usually designed with a dual-channel architecture or a single-channel architecture, that is, an LPDDR chip includes two channels (i.e., dual Rank) or one channel (i.e., single Rank). Before initializing the LPDDR chip, it is necessary to obtain the WCK-ON (Write Clock-ON) value, so as to initialize the LPDDR chip according to the WCK-ON value. However, there is currently no universal solution to simultaneously compatible the WCK-ON acquisition of single Rank and dual Rank. When facing LPDDR chips with different Rank configurations, different initialization schemes need to be formulated for single Rank and dual Rank respectively to obtain the WCK-ON value and initialize, which not only increases the test cost, but also easily increases the error probability due to problems such as scheme switching, and reduces the accuracy of determining the WCK-ON value. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a method, system, device and storage medium for determining the WCK-ON value of an LPDDR chip, which can simultaneously compatible LPDDR chips of single Rank and dual Rank, accurately test the WCK-ON value of the LPDDR chip, and has a low test cost.

[0005] In a first aspect, an embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, including:

[0006] Obtain the first MR value of the LPDDR chip, where the first MR value represents the first configuration information corresponding to the first Rank;

[0007] Obtain the second MR value of the LPDDR chip, where the second MR value represents the second configuration information corresponding to the second Rank;

[0008] Compare the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result;

[0009] When the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, determine a first CHS mode according to the first MR value and the second MR value, and determine a first WCK-ON value of the LPDDR chip according to the first CHS mode, where the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronous coordination information between the ranks;

[0010] When the first comparison result indicates that the second MR value is not updated, correct the second MR value to the first MR value, determine a second CHS mode according to the second MR value, and determine a second WCK-ON value of the LPDDR chip according to the second CHS mode, where the second CHS mode indicates that the LPDDR chip has a single rank and second synchronous coordination information between the ranks.

[0011] In some alternative embodiments, when the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value includes:

[0012] When the first comparison result indicates that the first MR value is equal to the preset MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, configure the LPDDR chip into a dual-rank mode;

[0013] Obtain a first synchronous coordination table corresponding to the dual-rank mode;

[0014] Determine the first CHS mode according to the first synchronous coordination table, the first MR value and the second MR value.

[0015] In some alternative embodiments, determining the first CHS mode according to the first synchronous coordination table, the first MR value and the second MR value includes:

[0016] Determine a first configuration information and a second configuration information according to the first MR value, the second MR value and a preset configuration table;

[0017] Determine the first synchronous coordination information according to the first configuration information and the second configuration information;

[0018] Search for a first entry in the first synchronous coordination table that matches the first synchronous coordination information;

[0019] Configure the CHS mode corresponding to the first entry as the first CHS mode.

[0020] In some alternative embodiments, the method further includes:

[0021] When the first comparison result indicates that the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, configure the first CHS mode as the first mode, and configure the first WCK-ON value as a first numerical value according to the first mode;

[0022] When the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, configure the first CHS mode as the second mode, and configure the first WCK-ON value as a second numerical value according to the second mode.

[0023] In some alternative embodiments, determining the second CHS mode according to the second MR value and determining the second WCK-ON value of the LPDDR chip according to the second CHS mode includes:

[0024] When the second MR value is equal to the preset MR value, configure the second CHS mode as the second mode, and configure the second WCK-ON value as a second numerical value according to the second mode;

[0025] When the second MR value is not equal to the preset MR value, configure the second CHS mode as the first mode, and configure the second WCK-ON value as a first numerical value according to the first mode.

[0026] In some alternative embodiments, determining the second CHS mode according to the second MR value and determining the second WCK-ON value of the LPDDR chip according to the second CHS mode includes:

[0027] When the second MR value is equal to the preset MR value, configure the second CHS mode as the second mode, and configure the second WCK-ON value as a second numerical value according to the second mode;

[0028] When the second MR value is not equal to the preset MR value, configure the second CHS mode as the first mode, and configure the second WCK-ON value as a first numerical value according to the first mode.

[0029] In some alternative embodiments, determining the second CHS mode according to the second synchronization coordination table and the second MR value includes:

[0030] Determine the second synchronization coordination information according to the second MR value and the preset configuration table;

[0031] Search for a second entry in the second synchronization coordination table that matches the second synchronization coordination information;

[0032] Configure the CHS mode corresponding to the second entry as the second CHS mode.

[0033] In a second aspect, an embodiment of the present invention provides a system for determining the WCK-ON value of an LPDDR chip, including:

[0034] A first module for obtaining a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank;

[0035] A second module for obtaining a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to a second Rank;

[0036] A third module for comparing the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result;

[0037] A fourth module for, when the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, where the first CHS mode indicates that the LPDDR chip has a dual Rank and first synchronization coordination information between the Ranks;

[0038] A fifth module for, when the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, where the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between the Ranks.

[0039] In a third aspect, an embodiment of the present invention provides a memory test device applied to a smart card, and the device includes:

[0040] At least one processor;

[0041] At least one memory for storing at least one program;

[0042] When the at least one program is executed by the at least one processor, the at least one processor implements the method as described above.

[0043] Fourthly, an embodiment of the present invention provides a computer-readable storage medium, which stores a program executable by a processor. The program executable by the processor is used to execute the method as described above when executed by the processor.

[0044] Implementing the embodiments of the present invention includes the following beneficial effects: An embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, including: obtaining a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; obtaining a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to a second Rank; comparing the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result; in the case where the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, where the first CHS mode indicates that the LPDDR chip has a dual Rank and first synchronization coordination information between the Ranks; in the case where the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, where the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between the Ranks. After obtaining the first MR value and the second MR value of the first Rank and the second Rank and comparing them with the preset MR value, it is determined whether the LPDDR chip has a dual Rank or a single Rank, and the corresponding first WCK-ON value and second WCK-ON value are determined. Therefore, it is possible to simultaneously determine the WCK-ON value for LPDDR chips with both dual Rank and single Rank, without the need to separately formulate different initialization schemes for single Rank and dual Rank, the test cost is low, the error probability caused by problems such as scheme switching is reduced, and the accuracy of WCK-ON value determination is improved. Description of the Drawings

[0045] Figure 1 It is a schematic flowchart of the steps of a method for determining the WCK-ON value of an LPDDR chip provided by an embodiment of the present invention;

[0046] Figure 2 It is a schematic diagram of the first Rank and the second Rank of an LPDDR chip provided by an embodiment of the present invention;

[0047] Figure 3It is a structural block diagram of a WCK-ON value determination system for an LPDDR chip provided by an embodiment of the present invention;

[0048] Figure 4 It is a structural block diagram of a memory test device provided by an embodiment of the present invention. Detailed implementation manners

[0049] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] It should be noted that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. Terms such as "first" and "second" in the specification, claims or the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0051] An embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, including: obtaining a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; obtaining a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to a second Rank; comparing the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result; in the case where the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, where the first CHS mode indicates that the LPDDR chip has dual Ranks and first synchronization coordination information between the Ranks; in the case where the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, where the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between the Ranks. By obtaining the first MR value and the second MR value of the first Rank and the second Rank, comparing them with the preset MR value, and then determining whether the LPDDR chip has dual Ranks or a single Rank, and determining the corresponding first WCK-ON value and second WCK-ON value, it is possible to simultaneously determine the WCK-ON value for LPDDR chips with both dual Ranks and single Ranks, without the need to develop different initialization schemes for single Ranks and dual Ranks respectively, resulting in low test costs and reducing the error probability caused by issues such as scheme switching, thereby improving the accuracy of WCK-ON value determination.

[0052] The following further elaborates on the embodiments of the present invention in conjunction with the accompanying drawings.

[0053] As Figure 1 shown, an embodiment of the present invention provides a method for determining the WCK-ON value of an LPDDR chip, and the steps included are as follows.

[0054] S100. Obtain a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank;

[0055] S200. Obtain a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to a second Rank;

[0056] S300. Compare the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result;

[0057] S400. When the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determine the first CHS mode according to the first MR value and the second MR value, and determine the first WCK-ON value of the LPDDR chip according to the first CHS mode. The first CHS mode indicates that the LPDDR chip has dual ranks and the first synchronization coordination information between the ranks.

[0058] S500. When the first comparison result indicates that the second MR value is not updated, correct the second MR value to the first MR value, determine the second CHS mode according to the second MR value, and determine the second WCK-ON value of the LPDDR chip according to the second CHS mode. The second CHS mode indicates that the LPDDR chip has a single rank and the second synchronization coordination information between the ranks.

[0059] Specifically, referring to Figure 2 , in the LPDDR chip (taking LPDDR4 / 5 in this application as an example), the MR (Mode Register) value plays a key role. It stores the configuration information of each rank (memory channel) inside the LPDDR chip. Here, the first MR value corresponds to the first configuration information of the first rank, and the second MR value corresponds to the second configuration information of the second rank. These configuration information cover multiple aspects, such as the working mode (different operation settings such as high-performance mode, low-power mode, etc.), the timing parameters of data transmission (including the clock signal timing of read and write operations, data hold time, etc.), the address mapping method (determines the correspondence between the storage location of data in the memory channel and the external address), and the related settings for cooperating with other components. The specific configuration information is not limited here. By obtaining the first MR value and the second MR value, the current specific configuration status of the first rank and the second rank can be determined.

[0060] The preset MR value is a reference value preset based on factors such as the standard specification of the LPDDR chip, conventional best practices, and design expectations, such as 0XFFFF. It is specifically set according to actual requirements and is not limited here. The preset MR value conforms to the configuration status required for the normal and stable operation of the chip. For example, for the cooperation of dual ranks or the independent operation of a single rank in common application scenarios, there is a default and verified configuration status, and the MR value corresponding to this status is set as the preset MR value. By comparing with it, it can be quickly judged whether the actual first MR value and second MR value are within the expected reasonable range, and whether corresponding adjustments need to be made or the WCK-ON value needs to be further obtained for initialization.

[0061] The first MR value and the second MR value are respectively compared with a preset MR value one by one. For example, compare whether the data bits corresponding to the comparison working mode are the same, whether the timing parameter bits are consistent, etc., or compare the overall data bits one by one. The specific comparison method is not limited here. The first comparison result will present various situations. For example, the first MR value is equal to the preset MR value while the second MR value is not, or both are equal to the preset MR value, or both are not equal, etc.

[0062] When the first comparison result shows that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, it means that the initial configuration of at least one Rank meets the normal expectation, and at the same time, there is a new configuration change in the second Rank, indicating that the LPDDR chip operates in a dual-Rank mode (with dual Ranks), and the first WCK-ON value of the dual Ranks of the LPDDR chip is normal, and the initialization of the LPDDR chip can be carried out or ended according to requirements.

[0063] The first CHS (Channel Synchronization) mode is determined jointly according to the first MR value and the second MR value, because the configurations of both Ranks affect the synchronization and coordination between the dual Ranks. For example, some parameters in the first MR value may specify some characteristics of the first Rank in data transmission (such as the priority of data transmission, the acceptable clock delay range, etc.), and the updated part in the second MR value reflects the new requirements or changes of the second Rank (such as changing the data width or read / write order, etc.). It is necessary to synthesize this information to determine the coordination method between the dual Ranks. Through the mapping relationship between the configuration information and the CHS mode, according to the mapping relationship, the key configuration parameters extracted from the first MR value and the second MR value are matched to determine the first CHS mode. This mode details the first synchronization and coordination information between the Ranks of the LPDDR chip in the dual-Rank state, such as specifying the clock synchronization method of the two Ranks (whether it is strictly the same frequency and in-phase, or allowing a certain phase difference, etc.), the order of data strobe, and some interaction rules during data transmission.

[0064] Determine the first WCK-ON value based on the determined first CHS mode, because the WCK-ON value (write clock enable value) is closely related to the synchronization and coordination between Ranks. In the dual-Rank mode, in order to ensure that data can be accurately written into the storage units corresponding to the two Ranks simultaneously, it is necessary to accurately set the first WCK-ON value according to the synchronization and coordination requirements specified by the first CHS mode. For example, if the first CHS mode requires strict clock synchronization and data is written at a specific clock edge, then the first WCK-ON value should be accurate to that specific time point within the corresponding clock cycle to ensure that the write clock signal is enabled at the correct moment, enabling the two Ranks to cooperate to complete the data writing operation; if the first CHS mode allows a certain clock phase difference and a relatively loose data writing time window, the value range of the first WCK-ON value will be adjusted accordingly, but still needs to meet the accuracy and synchronization requirements for dual-Rank data writing. The first WCK-ON value is represented by binary code, and the specific representation method is not limited here.

[0065] When the first comparison result shows that the second MR value has not been updated, it indicates that the second Rank is not enabled or does not exist (that is, the LPDDR chip is in the single-Rank mode at this time). Therefore, assume that the second Rank is enabled or exists, and correct the second MR value of the virtual second Rank to the first MR value, so that the second WCK-ON value can be determined through the first MR value of the first Rank itself, that is, it conforms to the determination method of the dual-Rank mode and does not affect the reading of the WCK-ON value of the single Rank.

[0066] In some embodiments, the process of determining the second CHS mode: Determine the second CHS mode according to the corrected second MR value (which is the same as the first MR value at this time). This mode mainly reflects the second synchronization and coordination information between Ranks when the LPDDR chip is in the single-Rank mode (actually, it is the coordination situation of the single Rank itself at this time, and the second Rank is a virtual Rank). Since the single-Rank operation has different characteristics and requirements in terms of data transmission and clock synchronization compared to the dual-Rank cooperative operation, the corresponding second CHS mode will be determined according to the relevant rules and coordination methods during the single-Rank operation. For example, in the single-Rank mode, data transmission only needs to consider its own read and write timings and internal coordination, without involving synchronization issues with another Rank. The coordination rules for clock signal control, data strobe, etc. will be relatively simple and direct, and the second CHS mode is determined based on these rules and the corrected second MR value information.

[0067] In some embodiments, the process of determining the second WCK-ON value: Similarly, the second WCK-ON value is determined according to the determined second CHS mode. In the single-Rank mode, the activation time of the write clock mainly focuses on meeting the read / write timing requirements of this Rank itself and does not need to consider the synchronization issue with another Rank. Therefore, the determination of the second WCK-ON value will focus more on ensuring that data can be accurately and efficiently written into the storage unit within this single Rank. For example, according to parameters such as the read / write speed and data retention time of the single Rank, combined with the coordination rules regarding the clock signal and data operation in the second CHS mode, a suitable second WCK-ON value is calculated or set to ensure the smooth progress of the data write operation in the single-Rank mode.

[0068] In some alternative embodiments, the method further includes: when the first comparison result indicates that the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, configuring the first CHS mode as the first mode and configuring the first WCK-ON value as the first numerical value according to the first mode; when the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, configuring the first CHS mode as the second mode and configuring the first WCK-ON value as the second numerical value according to the second mode.

[0069] Specifically, when the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, it indicates that the current configuration information of the first Rank and the second Rank (represented by the first MR value and the second MR value respectively) is inconsistent with the preset standard configuration (preset MR value). However, the configuration of the second Rank has been updated, which means that the LPDDR chip has a dual Rank, and the configuration states of the first Rank and the second Rank deviate from the normal expectation, and corresponding initialization is required. Configure the first CHS mode as the first mode, and the first mode can specifically be a low-level signal mode (not specifically limited). The first CHS mode is set to the first mode by writing specific instructions or parameters to the relevant control registers in the LPDDR chip. The setting of these instructions and parameters follows the communication protocol and operation specifications stipulated by the chip manufacturer, involving the code for specifying the mode selection and some basic parameter settings supporting this mode, such as the approximate range of clock synchronization and the default method of data strobe, so as to enable the synchronization and coordination mechanism in the first mode. Once the first mode is determined, the first WCK-ON value needs to be configured as the first numerical value accordingly. Specifically, the first WCK-ON value is configured as "0" in the first mode, and thus the LPDDR chip is initialized according to the first WCK-ON value.

[0070] When the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, it indicates that the configuration of at least one Rank meets the preset standard configuration. At the same time, there is an update in the configuration of the second Rank, and the overall LPDDR chip configuration is partially in the normal expected state. Moreover, the update of the second Rank indicates that the LPDDR chip has dual Ranks, and the configuration status of the first Rank and / or the second Rank meets the conventional expectations. Configure the first CHS mode to the second mode, which can specifically be the high-level mode, and no specific limitation is made here. The second mode is usually an optimized synchronization and coordination mode applicable to the scenario where some Ranks meet the preset standards and there are Rank updates. It will make full use of the advantages of the Rank configurations that have met the standards and combine the updated content of the second Rank to achieve more efficient and accurate synchronization and coordination between the dual Ranks.

[0071] After the second mode is determined, correspondingly, configure the first WCK-ON value to the second value. Specifically, the second value can be "1", and no specific limitation is made here. According to the second value, the LPDDR chip can be selectively initialized or exited from initialization, and no specific limitation is made here.

[0072] In some alternative embodiments, determine the second CHS mode according to the second MR value, and determine the second WCK-ON value of the LPDDR chip according to the second CHS mode, including: when the second MR value is equal to the preset MR value, configure the second CHS mode to the second mode, and configure the second WCK-ON value to the second value according to the second mode; when the second MR value is not equal to the preset MR value, configure the second CHS mode to the first mode, and configure the second WCK-ON value to the first value according to the first mode.

[0073] Specifically, when the second MR value is equal to the preset MR value, it means that the configuration of the second Rank is in a standard state that meets the conventional expectations, and the second CHS mode is configured as the second mode. When the second MR value is not equal to the preset MR value, it means that the configuration of the second Rank does not meet the standard state of the conventional expectations, and the second CHS mode is configured as the first mode. This realizes more accurate and efficient synchronization and coordination of the LPDDR chip in a single Rank (the second Rank is a virtual Rank, equivalent to running in a single Rank) or between Ranks (self-coordination situation). It realizes the determination of the CHS mode for the LPDDR chip in a single Rank, and further determines the second WCK-ON value. According to the determination criteria of the LPDDR chip in the dual-Rank case, when the first MR and / or the second MR is equal to the preset MR value, the first CHS mode is configured as the second mode; when dealing with the single-Rank situation, by cleverly establishing a virtual second Rank and configuring the second MR value as the first MR value, the determination rules originally for the dual-Rank can be applied to the single-Rank scenario. A unified processing framework is logically constructed, enabling the single Rank and the dual Rank to follow similar rules in determining configuration parameters (especially the CHS mode and the subsequent determination of the WCK-ON value), reducing the complexity of having to separately design different determination and configuration methods due to different working modes / storage structures (single Rank or dual Rank). Therefore, when the LPDDR chip is in a single Rank, by establishing a virtual second Rank and configuring the second MR value as the first MR value, the determination rules for the dual Rank are applicable to the single Rank, thus enabling the simultaneous compatibility of the LPDDR chips in both single Rank and dual Rank for the WCK-ON value test, with low test costs.

[0074] In some alternative embodiments, when the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining the first CHS mode according to the first MR value and the second MR value includes: when the first comparison result indicates that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, configuring the LPDDR chip as a dual-Rank mode; obtaining the first synchronization coordination table corresponding to the dual-Rank mode; and determining the first CHS mode according to the first synchronization coordination table, the first MR value, and the second MR value.

[0075] Specifically, when the first comparison result shows that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, it means that at least part of the configuration state of the chip meets the conventional expectations (i.e., the configuration of at least one Rank conforms to the preset standard), and at the same time, there are new configuration changes in the second Rank. Then the LPDDR chip operates in the dual-Rank mode and needs to coordinate the work between the two Ranks according to the respective states of the two Ranks.

[0076] The first synchronization coordination table corresponding to the dual-Rank mode is the synchronization coordination table between each Rank when the LPDDR chip operates in the dual-Rank mode. This table details the corresponding relationship between different Rank configuration situations (specifically reflected as different combinations of MR values and different settings of various Rank-related parameters) and the specific synchronization coordination mode (i.e., the CHS mode) of the LPDDR chip in the dual-Rank mode, and at the same time covers many detailed parameter settings related to the coordinated work of the dual-Rank. For example, the table includes the clock synchronization method between the Ranks (whether it is strict same-frequency and same-phase synchronization, or synchronization allowing a certain phase difference, etc.), the coordination mechanism of the data strobe signal (how to ensure accurate data transmission and switching between the two Ranks), the sequence of read and write operations, and the corresponding time interval requirements, etc., aiming to provide a comprehensive and accurate guiding basis for achieving efficient and stable data processing in the dual-Rank mode, and helping users quickly determine the appropriate synchronization coordination mode and related parameters according to the actual Rank configuration situation.

[0077] After obtaining the first synchronization coordination table, it is necessary to determine the first CHS mode based on the current first MR value and second MR value. First, each key information bit in the first MR value and the second MR value is parsed in detail because these information bits carry specific details about the current configurations of the two Ranks. For example, certain specific bit positions in the first MR value represent information such as the data transfer rate setting of the first Rank, the precision requirement for clock synchronization, or the priority of read / write operations, etc.; similarly, the updated part of the second MR value also contains key information reflecting the new configuration of the second Rank, such as the changed data width, the new clock mode, or different address mapping methods, etc. Then, these key configuration information parsed and extracted from the first MR value and the second MR value are comprehensively matched and searched in the content of the first synchronization coordination table. According to the corresponding relationship specified in the table, each parameter is carefully compared. When a record is found whose all parameters are exactly the same as the key configuration information extracted from the two MR values, the CHS mode corresponding to this record is the first CHS mode to be determined. For example, assume that the information parsed from the first MR value and the second MR value indicates that the first Rank uses a higher data transfer rate and a looser clock synchronization method, the data width of the second Rank after update is a specific value, and there is a specific order for read / write operations. By searching in the first synchronization coordination table for the corresponding entry that meets these conditions, if the corresponding entry in the table shows that the CHS mode corresponding to this situation is the "asynchronous data transfer, loose clock synchronization (phase difference allowable range is ±5 ns) and specific read / write order" mode, then it can be determined that this is the first CHS mode in the current situation. Subsequently, based on this determined first CHS mode, other key parameters such as the first WCK - ON value adapted to it can be further determined to ensure that the chip can perform stable data read / write operations according to accurate synchronization coordination rules in the dual - Rank mode.

[0078] In some alternative embodiments, determining the first CHS mode according to the first synchronization coordination table, the first MR value, and the second MR value includes: determining first configuration information and second configuration information according to the first MR value, the second MR value, and a preset configuration table; determining first synchronization coordination information according to the first configuration information and the second configuration information; searching for the first entry that matches the first synchronization coordination information in the first synchronization coordination table; configuring the CHS mode corresponding to the first entry as the first CHS mode.

[0079] Specifically, the preset configuration table is a reference table used to parse the specific configuration meanings represented by MR values. It establishes the mapping relationship between each bit or bit segment in the MR value and the actual chip configuration parameters, covering configuration information in many aspects such as working mode, data transfer rate, clock synchronization method, address mapping rules, etc. Through this table, the abstract MR value presented in binary form can be converted into intuitive and understandable specific configuration content, so as to obtain the detailed configuration of each Rank. For the first MR value, according to the preset configuration table, check the specific configuration meanings corresponding to the corresponding bit combinations. For example, if several binary values represent that the data transfer rate of the first Rank is 1600 Mbps per second according to the mapping relationship of the preset configuration table, and several other bits represent that the clock synchronization method it adopts is a loose synchronization mode allowing a certain phase difference, etc. By interpreting bit by bit or by segment in this way, the complete first configuration information of the first Rank can be determined, including specific parameter settings in many aspects such as data reading and writing, synchronization coordination, etc. Similarly, for the second MR value, it is also parsed according to the preset configuration table. Since the second MR value represents the configuration of the second Rank and there are updates, the second configuration information parsed will reflect its latest settings, such as changes in the new data width, different read and write orders, etc. Through the first MR value, the second MR value and the preset configuration table, the first configuration information and the second configuration information are respectively clarified.

[0080] The first configuration information and the second configuration information contain many specific parameter settings of the two Ranks respectively, while the first synchronization coordination information is extracted from the perspective of the overall coordinated work of the two Ranks, and those key contents closely related to how they synchronize and coordinate data reading and writing operations are refined. Multiple factors are comprehensively considered, such as the differences in clock synchronization requirements between the two Ranks, the interaction mode of data transfer, the order of read and write operations, and the mechanism for ensuring data accuracy and integrity. For example, the first configuration information shows that the data transfer rate of the first Rank is relatively fast, but the requirement for clock synchronization accuracy is relatively loose, while the second configuration information indicates that the data width of the second Rank has changed and there are specific requirements for the read and write order. Considering these situations comprehensively, the determined first synchronization coordination information is that "the two Ranks adopt an asynchronous data transfer method, the clock synchronization allows a certain phase difference, the data transfer needs to be carried out in the order of the second Rank's priority for reading and writing, and a specific verification mechanism is used to ensure data accuracy during the transfer process". Through such integration and analysis of the configuration information of the two Ranks, the key coordination requirements for their coordinated work are sorted out, that is, the first synchronization coordination information, and a matching entry is searched in the first synchronization coordination table.

[0081] The first synchronization coordination table is a pre-organized table that records the corresponding relationships between different synchronization coordination situations and the corresponding CHS modes, covering the synchronization coordination modes corresponding to various possible dual-Rank configuration combinations. Search for the first entry in this table that matches the first synchronization coordination information to find the specific record entry that meets the requirements for the current cooperation between the two Ranks. When searching, it is necessary to compare each key element in the first synchronization coordination information, such as the clock synchronization method, data transmission order, data verification mechanism, etc., with the corresponding content of each entry in the table one by one to find the matching entry. After finding the first matching entry, configure the corresponding CHS mode as the first CHS mode. This enables the LPDDR chip in the dual-Rank mode to perform operations such as synchronization coordination and data read / write between Ranks according to the rules specified by the accurate first CHS mode, ensuring that the two Ranks can cooperate efficiently and stably, meeting the data processing requirements of the LPDDR chip in the dual-Rank application scenario, ensuring the accurate transmission and storage of memory data, and improving the operating performance and reliability of the entire system.

[0082] In some alternative embodiments, when the first comparison result indicates that the second MR value has not been updated, the second MR value is corrected to the first MR value, and the second CHS mode is determined according to the second MR value, including: when the first comparison result indicates that the second MR value has not been updated, configure the LPDDR chip into the single-Rank mode; based on the single-Rank mode, correct the second MR value to the first MR value so that the second MR value is equal to the first MR value; obtain the second synchronization coordination table corresponding to the single-Rank mode; determine the second CHS mode according to the second synchronization coordination table and the second MR value.

[0083] Specifically, when the first comparison result indicates that the second MR value has not been updated, the LPDDR chip is configured in the single Rank mode. After determining to adopt the single Rank mode, the second MR value is corrected to the first MR value to ensure that the two Ranks (although operating in the single Rank mode at this time, there is originally the concept of two Ranks, and the second Rank is a virtual Rank) are consistent in the basic configuration, so that the single Rank LPDDR chip can apply the WCK-ON value determination method of the dual Rank LPDDR chip. The second synchronization coordination table corresponding to the single Rank mode is a reference table specifically formulated for the chip operating in the single Rank mode, which records the correspondence between different MR values (the unified MR values after correction here) and the specific synchronization coordination mode (i.e., the second CHS mode) of the LPDDR chip in the single Rank mode, as well as the relevant detailed parameter settings. This table covers aspects such as the internal clock synchronization method within the single Rank (although there is no synchronization problem with another Rank, there are corresponding requirements for its own internal clock management), the coordination mechanism of the data strobe signal (ensuring accurate data transmission and processing within this single Rank), the order and time interval requirements of read and write operations, etc., aiming to provide a comprehensive and accurate guiding basis for the LPDDR chip to achieve efficient and stable data processing in the single Rank mode, and helping users quickly determine the appropriate synchronization coordination mode and related parameters according to the actual MR value situation.

[0084] After obtaining the second synchronization coordination table, it is necessary to determine the second CHS mode based on the currently corrected second MR value. First, each key information bit in the second MR value needs to be parsed because these information bits carry the specific configuration details of the current unique Rank (equivalent to single-Rank operation after configuration adjustment). For example, certain specific bit positions represent information such as data transfer rate, precision requirements for clock synchronization, or priorities for read and write operations. By following the interpretation method specified in the chip specifications, the meanings represented by these binary bits are extracted and converted into specific configuration parameters. Then, these key configuration parameters parsed are matched and searched in the content of the second synchronization coordination table. According to the corresponding relationship specified in the table, when the corresponding record is found, the CHS mode corresponding to this record is the second CHS mode to be determined. For example, the information parsed from the second MR value indicates that the data transfer rate is 1200 Mbps per second, the clock synchronization adopts a relatively strict internal synchronization method, and the read and write operations are in the order of write first and then read. By searching in the second synchronization coordination table for the corresponding entry that meets these conditions, if the corresponding entry in the table shows that the second CHS mode corresponding to this situation is the "strict internal clock synchronization, write-first and then-read order, specific data strobe mechanism" mode, then this can be determined as the second CHS mode in the current situation. Subsequently, based on this determined second CHS mode, other key parameters such as the second WCK-ON value adapted to it can be further determined to ensure that the chip can perform stable data read and write operations according to accurate synchronization coordination rules in the single-Rank mode.

[0085] In some alternative embodiments, determining the second CHS mode according to the second synchronization coordination table and the second MR value includes: determining the second synchronization coordination information according to the second MR value and a preset configuration table; searching for a second entry in the second synchronization coordination table that matches the second synchronization coordination information; and configuring the CHS mode corresponding to the second entry as the second CHS mode.

[0086] Specifically, the second synchronization coordination table is formulated by LPDDR for the single-Rank mode of the chip, which records the mapping relationship between various different combinations of synchronization coordination information and the corresponding CHS (Channel Synchronization) modes under the single-Rank operation condition. The table covers the corresponding CHS modes under different data transfer rates, different clock synchronization methods, and various parameter combinations such as read / write orders, providing a reference for accurately determining the specific synchronization coordination mode of the chip in the single-Rank mode. When searching for the second entry that matches the second synchronization coordination information in this table, it is necessary to compare each key element in the previously determined second synchronization coordination information, such as data transfer rate, clock synchronization method, read / write operation order, etc., with the corresponding content of each entry in the table one by one. If a matching second entry is accurately found in the second synchronization coordination table, the corresponding CHS mode is configured as the second CHS mode. This enables the LPDDR chip to perform internal data read / write, clock synchronization, etc. according to the rules specified by the accurate second CHS mode in the single-Rank mode, ensuring efficient and stable transmission and processing of data within this single Rank, and avoiding problems such as data errors and low read / write efficiency caused by improper synchronization coordination. It meets the system's requirement for determining the WCK-ON value of the LPDDR chip in the single-Rank application scenario, thereby ensuring the initialization accuracy of the single-Rank LPDDR chip.

[0087] The implementation of the embodiments of the present invention includes the following beneficial effects: The embodiments of the present invention provide a method for determining the WCK-ON value of an LPDDR chip, including: obtaining a first MR value of the LPDDR chip, where the first MR value represents the first configuration information corresponding to the first Rank; obtaining a second MR value of the LPDDR chip, where the second MR value represents the second configuration information corresponding to the second Rank; comparing the first MR value and the second MR value with a preset MR value respectively to obtain a first comparison result; in the case where the first comparison result indicates that the first MR value and / or the second MR value is equal to the preset MR value and the second MR value is updated, determining a first CHS mode according to the first MR value and the second MR value, and determining a first WCK-ON value of the LPDDR chip according to the first CHS mode, where the first CHS mode indicates that the LPDDR chip has dual Ranks and first synchronous coordination information between the Ranks; in the case where the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, where the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronous coordination information between the Ranks. By obtaining the first MR value and the second MR value of the first Rank and the second Rank, comparing them with the preset MR value, and then determining whether the LPDDR chip has dual Ranks or a single Rank, and determining the corresponding first WCK-ON value and second WCK-ON value, it is possible to simultaneously be compatible with LPDDR chips with dual Ranks and single Ranks to determine the WCK-ON value, without the need to separately formulate different initialization schemes for single Ranks and dual Ranks, the test cost is low, the error probability caused by problems such as scheme switching is reduced, and the accuracy of determining the WCK-ON value is improved.

[0088] In a second aspect, referring to Figure 3 , the embodiments of the present invention provide a system for determining the WCK-ON value of an LPDDR chip, including:

[0089] A first module, configured to obtain a first storage capacity of the LPDDR chip, where the first storage capacity represents the storage capacity corresponding to the first Rank;

[0090] A second module, configured to obtain a second storage capacity of the LPDDR chip, where the second storage capacity represents the storage capacity corresponding to the second Rank;

[0091] A third module, configured to compare the first storage capacity and the second storage capacity with a preset storage capacity respectively to obtain a first comparison result;

[0092] A fourth module, configured to obtain a first EMI value and a second EMI value according to the first comparison result, the first storage table, and the second storage table, where the first storage table represents a relationship table between a first parameter value and a storage capacity, the second storage table represents a relationship table between a second parameter value and a storage capacity, the first EMI value represents the EMI value of a first Rank, and the second EMI value represents the EMI value of a second Rank;

[0093] A fifth module, configured to determine the EMI value of the LPDDR chip according to the first EMI value and the second EMI value.

[0094] It can be seen that the content in the above method embodiments is applicable to the present system embodiment. The functions specifically implemented in the present system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0095] In a third aspect, referring to Figure 4 , an embodiment of the present invention provides a memory test device, including:

[0096] At least one processor;

[0097] At least one memory, configured to store at least one program;

[0098] When the at least one program is executed by the at least one processor, the at least one processor implements the method as described above.

[0099] It can be seen that the content in the above method embodiments is applicable to the present device embodiment. The functions specifically implemented in the present device embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0100] In a fourth aspect, in addition, an embodiment of the present application further discloses a computer program product or a computer program. The computer program product or the computer program is stored in a computer-readable storage medium. The processor of the computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the method or the system as described above. Similarly, the content in the above method embodiments is applicable to the present storage medium embodiment. The functions specifically implemented in the present storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0101] It can be understood that all or some of the steps and systems disclosed in the above methods can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital information processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0102] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the scope of knowledge possessed by those of ordinary skill in the art.

Claims

1. A method for determining the WCK-ON value of an LPDDR chip, characterized in that: include: Acquire a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to the first Rank; Acquire a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; Comparing the first MR value and the second MR value with a preset MR value to obtain a first comparison result; When the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, a first CHS mode is determined according to the first MR value and the second MR value, and a first WCK-ON value of the LPDDR chip is determined according to the first CHS mode, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between the ranks; When the first comparison result indicates that the second MR value has not been updated, the second MR value is corrected to the first MR value, a second CHS mode is determined according to the second MR value, and a second WCK-ON value of the LPDDR chip is determined according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

2. The method according to claim 1, characterized in that The determining a first CHS mode according to the first MR value and the second MR value when the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated includes: When the first comparison result indicates that the first MR value is equal to the preset MR value, and / or the second MR value is equal to the preset MR value, and the second MR value is updated, configuring the LPDDR chip to a dual Rank mode; Obtain the first synchronization coordination table corresponding to the dual Rank mode; The first CHS mode is determined according to the first synchronization coordination table, the first MR value, and the second MR value.

3. The method according to claim 2, characterized in that The determining the first CHS mode according to the first synchronization coordination table, the first MR value and the second MR value includes: Determine the first configuration information and the second configuration information according to the first MR value, the second MR value and a preset configuration table; Determine the first synchronization coordination information according to the first configuration information and the second configuration information; Searching the first synchronization coordination table for a first entry that matches the first synchronization coordination information; The CHS mode corresponding to the first entry is configured as the first CHS mode.

4. The method according to claim 1, characterized in that: The method further comprises: When the first comparison result indicates that the first MR value is not equal to the preset MR value, the second MR value is not equal to the preset MR value, and the second MR value is updated, configuring the first CHS mode as the first mode, and configuring the first WCK-ON value as the first value according to the first mode; When the first comparison result indicates that the first MR value and / or the second MR value is equal to a preset MR value and the second MR value is updated, the first CHS mode is configured as a second mode, and the first WCK-ON value is configured as a second value according to the second mode.

5. The method according to claim 4, characterized in that The determining a second CHS mode according to the second MR value, and determining a second WCK-ON value of the LPDDR chip according to the second CHS mode, includes: When the second MR value is equal to the preset MR value, configuring the second CHS mode to the second mode, and configuring the second WCK-ON value to a second value according to the second mode; When the second MR value is not equal to the preset MR value, the second CHS mode is configured as the first mode, and the second WCK-ON value is configured as a first value according to the first mode.

6. The method according to claim 1, characterized in that When the first comparison result indicates that the second MR value is not updated, correcting the second MR value to the first MR value, and determining a second CHS mode according to the second MR value, includes: When the first comparison result indicates that the second MR value is not updated, configuring the LPDDR chip to a single Rank mode; Correcting the second MR value to the first MR value based on a single Rank mode, so that the second MR value is equal to the first MR value; Obtain the second synchronization coordination table corresponding to the single Rank mode; The second CHS mode is determined according to the second synchronization coordination table and the second MR value.

7. The method according to claim 6, characterized in that The determining the second CHS mode according to the second synchronization coordination table and the second MR value includes: Determine the second synchronization coordination information according to the second MR value and a preset configuration table; Searching the second synchronization coordination table for a second entry matching the second synchronization coordination information; The CHS mode corresponding to the second entry is configured as the second CHS mode.

8. A system for determining the WCK-ON value of an LPDDR chip, characterized in that: include: The first module is used to obtain a first MR value of the LPDDR chip, where the first MR value represents first configuration information corresponding to a first Rank; The second module is used to obtain a second MR value of the LPDDR chip, where the second MR value represents second configuration information corresponding to the second Rank; A third module, configured to compare the first MR value and the second MR value with a preset MR value to obtain a first comparison result; a fourth module, configured to determine a first CHS mode according to the first MR value and the second MR value, and determine a first WCK-ON value of the LPDDR chip according to the first CHS mode, when the first comparison result indicates that the first MR value and / or the second MR value are equal to a preset MR value and the second MR value is updated, wherein the first CHS mode indicates that the LPDDR chip has dual ranks and first synchronization coordination information between ranks; The fifth module is used to correct the second MR value to the first MR value when the first comparison result indicates that the second MR value is not updated, determine a second CHS mode according to the second MR value, and determine a second WCK-ON value of the LPDDR chip according to the second CHS mode, wherein the second CHS mode indicates that the LPDDR chip has a single Rank and second synchronization coordination information between Ranks.

9. A memory testing device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

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