Packaging method of double-sided bump packaging chip and corresponding structure of double-sided bump packaging chip

Abstract

The invention discloses a packaging method of a double-sided bump packaging chip, which overcomes the defects that the double-sided bump packaging chip is easy to oxidize and leak electricity, and ensures the quality and the working stability of the double-sided bump packaging chip. The method is characterized by comprising the following steps of: after the operation on the front surface of a wafer is finished, bonding the front surface of the wafer with glass and then reversely arranging, grinding a Si surface on the back surface of the wafer, releasing stress, operating a SiO2 layer on the surface of the Si layer, sputtering a Ti / Cu layer on the surface of the SiO2 layer, electroplating Cu on the surface of the Ti / Cu layer to form an electroplated Cu layer, and forming an RDL (Reduced DL) of a corresponding pattern on the back surface of the wafer through photoetching, the manufacturing method comprises the following steps of: preparing a back surface of a wafer through photoetching, Ti / Cu layer etching and photoresist removing operation, performing plasma treatment on the back surface of the wafer after the back surface Cu operation is completed, performing protection on an RDL surface in a chemical plating manner, performing inversion again, performing de-bonding by irradiating UV light, separating glass from the wafer, and performing mechanical cutting to form a complete single chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, in particular to a packaging method for a double-sided bump packaged chip. The present invention also provides a packaging structure for the double-sided bump packaged chip. Background Art

[0002] Figure 1 A conventional double-sided Cu chip packaging structure is shown. The prior art packaging method corresponding to the chip is as follows: a PI layer 40' is made on the die surface 2' of the wafer 1' to expose the pad 30' area, and then a Ti / Cu seed layer 50' is sputtered in the pad 30' area, and then a bump 60' is generated by photolithography, electroplating, debonding and Ti / Cu etching. At this point, the bump 60' operation on the front side of the wafer is completed. After the bump on the front side of the wafer 1' is completed, a layer of bonding glue is applied, and it is temporarily pressed with the glass, and the back side of the wafer 1' is operated to place the wafer After the back surface of the wafer 1' is ground and thinned, the Si surface is etched to release the stress, and then a Ti / Cu layer 20' is formed on the surface of the back surface of the wafer 1' by sputtering, and then Cu is electroplated. After the Cu is electroplated, a photolithography pattern is performed on the Cu surface, and the RDL10' of the back Cu is formed by Ti / Cu etching and debonding. The packaging structure of the double-sided Cu chip manufactured by this method is prone to oxidation and leakage problems. Therefore, it is urgent to develop a new packaging method suitable for double-sided Cu chip packaging to solve the oxidation and leakage problems that are prone to occur in double-sided Cu chips. Summary of the invention

[0003] In view of the above problems, the present invention provides a packaging method for a double-sided bump packaged chip, which solves the defects of the double-sided bump packaged chip being easy to oxidize and leak electricity, and ensures the quality and working stability of the double-sided bump packaged chip.

[0004] A packaging method for a double-sided bump packaged chip, characterized in that:

[0005] After the front side operation of the wafer is completed, the front side of the wafer is bonded to the glass and then inverted. Then, the Si side of the back side of the wafer is ground and stress released. Then, a SiO2 layer is operated on the surface of the Si layer. Then, a Ti / Cu layer is sputtered on the surface of the SiO2 layer. Then, Cu is electroplated on the surface of the Ti / Cu layer to form an electroplated Cu layer. Then, through photolithography, an RDL with corresponding patterns is formed on the back side of the wafer. Then, through photolithography, Ti / Cu layer etching and degumming operations, the production of the back Cu is completed. After the back Cu operation is completed, the back side of the wafer is plasma treated, and then the RDL surface is protected by chemical plating. After being inverted again, UV light is used for debonding, the glass and the wafer are separated, and a complete single chip is formed by mechanical cutting.

[0006] It is further characterized by:

[0007] The SiO2 layer is obtained by chemical vapor deposition operation;

[0008] In the Ti / Cu layer sputtered on the SiO2 layer, Ti is used as a barrier layer and Cu is used as a conductive seed layer. The thickness of the electroplated Cu layer is within 15 um, and photolithography is performed on the surface of the electroplated Cu layer.

[0009] Its further feature is that its specific operation steps are as follows:

[0010] S1, incoming wafers, the wafers include the bottom Si layer and the upper Pad and functional layers;

[0011] S2, cleaning and baking the wafer, and plasma treating the wafer surface, after which a PI layer is covered on the upper surface of the wafer and the Pad is exposed;

[0012] S3, after the PI layer is completed, a bump operation is performed on the wafer to form a plurality of convex bumps on the upper surface of the wafer;

[0013] S4, after applying a layer of bonding glue on the upper surface of the wafer, the glass and the wafer are pressed together to form a whole;

[0014] S5, turning the wafer upside down, and operating the back side of the wafer, firstly thinning the back side of the wafer by grinding, thinning the Si layer, and in order to reduce grinding stress damage, etching the Si layer on the back side of the wafer to release its stress;

[0015] S6. After the Si layer is ground and thinned, a SiO2 layer is formed on the surface of the Si layer by chemical vapor deposition to prevent leakage.

[0016] S7, sputtering a Ti / Cu layer on the surface of the SiO2 layer as a seed layer, then electroplating Cu on the surface of the seed layer, the thickness of the electroplated Cu layer is within 15um, then photolithography is performed on the surface of the Cu layer to form a pattern distribution, and the required RDL is formed by TiCu etching, and then a debonding operation is performed to completely expose the RDL;

[0017] S8, performing plasma treatment on the surface of the back side of the wafer, and then forming a metal protective layer on the surface of the RDL by chemical plating;

[0018] S9, attaching a dicing film on the back of the wafer;

[0019] S10, turn the wafer upside down, then irradiate with UV, debond, and separate the wafer from the glass;

[0020] S11: Cut the wafer and remove the dicing film to make it into single chips, which are then shipped.

[0021] It is further characterized by:

[0022] In step S5, the Si layer is thinned to a thickness of 10 to 150 um, and the specific thickness requirement is determined according to the thickness of the entire chip;

[0023] In step S8, a NiAu metal protective layer is formed by chemical plating.

[0024] The packaging structure of a double-sided bump packaged chip is characterized in that it comprises:

[0025] A substrate comprising a lower Si layer, an upper pad and a functional layer;

[0026] Several convex pumps;

[0027] and several convex RDLs;

[0028] A Pi layer is arranged on the functional layer of the substrate, a first Ti / Cu seed layer is arranged on the upper surface of the PAD and the periphery of the PAD, a corresponding pump is arranged on the first Ti / Cu seed layer and is arranged convexly, a SiO2 layer, a second Ti / Cu layer, and a Cu layer are sequentially arranged on the lower surface of the Si layer of the substrate, a plurality of convex RDLs are arranged on the lower surface of the Cu layer, and the periphery of the RDL is coated with a metal protective layer.

[0029] Its further feature is that the metal protective layer is a NiAu metal protective layer.

[0030] After adopting the above technical scheme, a SiO2 layer is processed on the surface of the Si layer, and then a Ti / Cu layer is sputtered on the surface of the SiO2 layer, which can effectively prevent leakage. In addition, after the RDL is formed and the Cu operation on the back is completed, the back of the wafer is plasma treated, and then the RDL surface is protected by chemical plating. The metal protective film formed by plasma treatment and chemical plating can effectively prevent RDL oxidation. In summary, it solves the defects of easy oxidation and leakage of double-sided bump chips, and ensures the quality and working stability of double-sided bump packaged chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The packaging structure of the existing double-sided Cu chip;

[0032] Figure 2 Schematic diagram of step S1 of the process flow of the packaging method of the present invention;

[0033] Figure 3 Schematic diagram of step S2 of the process flow of the packaging method of the present invention;

[0034] Figure 4Schematic diagram of step S3 of the process flow of the packaging method of the present invention;

[0035] Figure 5 Schematic diagram of step S4 of the process flow of the packaging method of the present invention;

[0036] Figure 6 is a schematic diagram of step S5 of the process flow of the packaging method of the present invention;

[0037] Figure 7 Schematic diagram of step S6 of the process flow of the packaging method of the present invention;

[0038] Figure 8 Schematic diagram of step S7 of the process flow of the packaging method of the present invention;

[0039] Fig. 9 Schematic diagram of step S8 of the process flow of the packaging method of the present invention;

[0040] Fig.10 Schematic diagram of step S9 of the process flow of the packaging method of the present invention;

[0041] Fig.11 Schematic diagram of step S10 of the process flow of the packaging method of the present invention;

[0042] Fig.12 It is a schematic diagram of step S11 of the process flow of the packaging method of the present invention, and is also a schematic diagram of the packaging structure corresponding to the present invention.

[0043] The names corresponding to the serial numbers in the figure are as follows:

[0044] Wafer 1', Die surface 2', RDL 10', Ti / Cu layer 20', pad 30', PI layer 40', Ti / Cu seed layer 50', bump 60';

[0045] Wafer 1, Si layer 10, Pad 20, functional layer 30, PI layer 40, first Ti / Cu seed layer 50, bump 60, bonding glue 70, glass 80, SiO2 layer 90, second Ti / Cu seed layer 100, RDL 110, surface metal protective layer 120, outer ring area metal protective layer 130, and dicing film 140. DETAILED DESCRIPTION

[0046] A packaging method for a double-sided bump package chip, see Figure 2-Figure 12: After the front side operation of wafer 1 is completed, the front side of wafer 1 is bonded to glass 80 and then inverted, then the Si layer 10 on the back side of wafer 1 is ground and stress released, then a SiO2 layer 90 is operated on the surface of Si layer 10, then a Ti / Cu layer is sputtered on the surface of SiO2 layer 90, then Cu is electroplated on the surface of Ti / Cu layer to form an electroplated Cu layer, then RDL110 of corresponding pattern is formed on the back side of wafer through photolithography, then the back side Cu layer is made through photolithography, Ti / Cu layer etching and degumming, after the back side Cu layer operation is completed, plasma treatment is performed on the back side of wafer 1, then chemical plating is performed to protect the surface of RDL110, after being inverted again, UV light is used for debonding, glass 80 and wafer 1 are separated, and a complete single chip is formed through mechanical cutting.

[0047] In a specific implementation, in the Ti / Cu layer sputtered on the SiO2 layer 90, Ti is used as a barrier layer and Cu is used as a conductive seed layer. The thickness of the electroplated Cu layer is within 15 um, and photolithography is performed on the surface of the electroplated Cu layer.

[0048] The specific steps are as follows:

[0049] S1, Wafer 1 incoming, Wafer 1 includes Si layer 10 at the bottom and Pad 20 and functional layer 30 at the top (see Figure 2 );

[0050] S2, cleaning and baking the wafer 1, and plasma treating the surface of the wafer 1, after which the upper surface of the wafer 1 is covered with a PI layer 40 and the Pad 20 is exposed (see Figure 3 );

[0051] S3, after the PI layer 40 is completed, a bump operation is performed on the wafer 1 to form a plurality of convex bumps 60 on the upper surface of the wafer (see Figure 4 ): a first Ti / Cu seed layer 50 is firstly sputtered on the PI layer, a photolithography operation is performed on the first Ti / Cu seed layer 50 to arrange the pattern, Cu and SnAg are electroplated after the photolithography to generate bumps 60, and after the bumps 60 are completed, the adhesive is removed to completely expose the bumps 60, and then Ti / Cu etching is performed to remove the seed layer in other areas except the bumps, so as to form a plurality of convex bumps 60 on the surface of the wafer;

[0052] S4, after applying a layer of bonding glue 70 on the upper surface of the wafer 1, the glass 80 and the wafer 1 are pressed together to form a whole (see Figure 5 );

[0053] S5, invert the wafer 1, and perform operations on the back side of the wafer 1. First, thin the back side of the wafer by grinding, thin the Si layer 10, and the thinning thickness of the Si layer is 10 to 150um. The specific thickness requirement is determined according to the thickness of the entire chip. In order to reduce the grinding stress damage, the Si layer 10 on the back side of the wafer is etched to release its stress (see Figure 6 );

[0054] S6. After the Si layer 10 is ground and thinned, in order to prevent leakage, a SiO2 layer 90 (see FIG. 1 ) is formed on the surface of the Si layer by chemical vapor deposition. Figure 7 );

[0055] S7, sputtering a Ti / Cu layer on the surface of the SiO2 layer 90 as a second Ti / Cu seed layer 100, then electroplating Cu on the surface of the seed layer, the thickness of the electroplated Cu layer is within 15um, then photolithography is performed on the surface of the Cu layer to form a pattern distribution, and the required RDL110 is formed by TiCu etching, and then a debonding operation is performed to completely expose the RDL110 (see Figure 8 );

[0056] S8, plasma treatment is performed on the surface of the back side of the wafer 1, and then a metal protective layer is formed on the surface of the RDL by chemical plating, the metal protective layer including a surface metal protective layer 120, an outer ring area metal protective layer 130 (see Fig. 9 );

[0057] S9, then a dicing film 140 is attached to the back of the wafer (see Fig.10 );

[0058] S10, invert the wafer 1, and then irradiate with UV to debond and separate the wafer 1 from the glass 80 (see Fig.11 );

[0059] S11, cutting the wafer 1, removing the dicing film 140, making it into single chips, and then shipping (see Fig.12 ).

[0060] In step S8 of the specific embodiment, a NiAu metal protective layer is formed by chemical plating.

[0061] The packaging structure of the double-sided bump package chip, see Fig.12 , which includes a substrate, a plurality of upwardly convex pumps, and a plurality of downwardly convex RDLs, wherein the substrate is the area of ​​a unit area formed after the wafer 1 is cut.

[0062] The substrate includes a lower Si layer 10, an upper pad20 and a functional layer 30; a Pi layer 40 is arranged on the functional layer 30 of the substrate, a first Ti / Cu seed layer 50 is arranged on the upper surface of PAD20 and the periphery of PAD20, a corresponding pump60 is arranged on the first Ti / Cu seed layer 50 and is arranged convexly, a SiO2 layer 90, a second Ti / Cu seed layer 100, and a Cu layer are sequentially arranged on the lower surface of the Si layer 10 of the substrate, a plurality of convex RDL110 are arranged on the lower surface of the Cu layer, and the periphery of the RDL110 is coated with a metal protective layer.

[0063] In a specific implementation, the metal protective layer is a NiAu metal protective layer, and the metal protective layer includes a surface metal protective layer 120 and an outer ring area metal protective layer 130 to ensure reliable protection for the RDL 110 .

[0064] The principle is as follows: a SiO2 layer is worked on the surface of the Si layer, and then a Ti / Cu layer is sputtered on the surface of the SiO2 layer, which can effectively prevent leakage; in addition, after the RDL is formed and the Cu operation on the back is completed, the back of the wafer is plasma treated, and then the RDL surface is protected by chemical plating. The metal protective film formed by plasma treatment and chemical plating can effectively prevent RDL oxidation.

[0065] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0066] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A packaging method for a double-sided bump packaged chip, characterized in that: After the front side operation of the wafer is completed, the front side of the wafer is bonded to the glass and then inverted. Then, the Si side of the back side of the wafer is ground and stress released. Then, a SiO2 layer is operated on the surface of the Si layer. Then, a Ti / Cu layer is sputtered on the surface of the SiO2 layer. Then, Cu is electroplated on the surface of the Ti / Cu layer to form an electroplated Cu layer. Then, through photolithography, an RDL with corresponding patterns is formed on the back side of the wafer. Then, through photolithography, Ti / Cu layer etching and degumming operations, the production of the back Cu is completed. After the back Cu operation is completed, the back side of the wafer is plasma treated, and then the RDL surface is protected by chemical plating. After being inverted again, UV light is used for debonding, the glass and the wafer are separated, and a complete single chip is formed by mechanical cutting.

2. The packaging method of a double-sided bump packaged chip according to claim 1, characterized in that: The SiO2 layer is obtained by chemical vapor deposition.

3. The packaging method of a double-sided bump packaged chip according to claim 1, characterized in that: In the Ti / Cu layer sputtered on the SiO2 layer, Ti is used as a barrier layer and Cu is used as a conductive seed layer. The thickness of the electroplated Cu layer is within 15 um, and photolithography is performed on the surface of the electroplated Cu layer.

4. The packaging method of a double-sided bump packaged chip according to claim 1, characterized in that: The specific steps are as follows: S1, incoming wafers, the wafers include the bottom Si layer and the upper Pad and functional layers; S2, cleaning and baking the wafer, and plasma treating the wafer surface, after which a PI layer is covered on the upper surface of the wafer and the Pad is exposed; S3, after the PI layer is completed, a bump operation is performed on the wafer to form a plurality of convex bumps on the upper surface of the wafer; S4, after applying a layer of bonding glue on the upper surface of the wafer, the glass and the wafer are pressed together to form a whole; S5, turning the wafer upside down, and operating the back side of the wafer, firstly thinning the back side of the wafer by grinding, thinning the Si layer, and in order to reduce grinding stress damage, etching the Si layer on the back side of the wafer to release its stress; S6. After the Si layer is ground and thinned, a SiO2 layer is formed on the surface of the Si layer by chemical vapor deposition to prevent leakage. S7, sputtering a Ti / Cu layer on the surface of the SiO2 layer as a seed layer, then electroplating Cu on the surface of the seed layer, the thickness of the electroplated Cu layer is within 15um, then photolithography is performed on the surface of the Cu layer to form a pattern distribution, and the required RDL is formed by TiCu etching, and then a debonding operation is performed to completely expose the RDL; S8, performing plasma treatment on the surface of the back side of the wafer, and then forming a metal protective layer on the surface of the RDL by chemical plating; S9, attaching a dicing film on the back of the wafer; S10, turn the wafer upside down, then irradiate with UV, debond, and separate the wafer from the glass; S11: Cut the wafer and remove the dicing film to make it into single chips, which are then shipped.

5. The packaging method of a double-sided bump packaged chip according to claim 4, characterized in that: In step S5, the Si layer is thinned to a thickness of 10 to 150 um, and the specific thickness requirement is determined according to the thickness of the entire chip.

6. The packaging method of a double-sided bump packaged chip according to claim 4, characterized in that: In step S8, a NiAu metal protective layer is formed by chemical plating.

7. A packaging structure of a double-sided bump packaged chip, which is manufactured by a packaging method of a double-sided bump packaged chip as claimed in any one of claims 1 to 6, characterized in that: It includes: A substrate comprising a lower Si layer, an upper pad and a functional layer; Several convex pumps; and several convex RDLs; A Pi layer is arranged on the functional layer of the substrate, a first Ti / Cu seed layer is arranged on the upper surface of the PAD and the periphery of the PAD, a corresponding pump is arranged on the first Ti / Cu seed layer and is arranged convexly, a SiO2 layer, a second Ti / Cu layer, and a Cu layer are sequentially arranged on the lower surface of the Si layer of the substrate, a plurality of convex RDLs are arranged on the lower surface of the Cu layer, and the periphery of the RDL is coated with a metal protective layer.

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