Semiconductor device

Abstract

The invention provides a semiconductor device, which is easy to miniaturize and can inhibit quality reduction. This semiconductor device is provided with: a first semiconductor chip and a second semiconductor chip provided so as to be separated from each other, each of the first semiconductor chip and the second semiconductor chip having a first main electrode on the upper surface side and a second main electrode on the lower surface side; and a printed circuit board provided around the first semiconductor chip and the second semiconductor chip, the printed circuit board having a plurality of wiring layers including an uppermost first wiring layer and a lowermost second wiring layer, and an insulating layer provided between the plurality of wiring layers, the first wiring layer is electrically connected to a first main electrode of a first semiconductor chip via a connecting member, the second wiring layer is electrically connected to the first wiring layer via a via, and the second wiring layer is electrically connected to a second main electrode of a second semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor device (semiconductor module) having a built-in power semiconductor element. Background Art

[0002] Patent document 1 discloses a composite ceramic multilayer substrate, which comprises a glass ceramic insulating layer including a wiring layer, and a high thermal conductivity ceramic insulating layer composed of a ceramic material having a higher thermal conductivity than that of the glass ceramic insulating layer, wherein the glass ceramic insulating layer is formed directly and / or via the wiring layer on one main surface or both main surfaces of the high thermal conductivity ceramic insulating layer, and the composite ceramic multilayer substrate has one or more heating element mounting portions, wherein the one or more heating element mounting portions are surrounded by the glass ceramic insulating layer when viewed in a direction perpendicular to the main surface of the composite ceramic multilayer substrate, and heating element mounting wiring formed on the main surface of the high thermal conductivity ceramic insulating layer is exposed at the one or more heating element mounting portions.

[0003] Patent document 2 discloses a semiconductor module comprising a power wiring provided with a power element, a glass ceramic multilayer substrate provided with a control element for controlling the power element, and a high thermal conductivity ceramic substrate made of a ceramic material having a thermal conductivity higher than that of the glass ceramic contained in the glass ceramic multilayer substrate, wherein the power wiring is provided on the high thermal conductivity ceramic substrate, and the glass ceramic multilayer substrate is directly provided on the high thermal conductivity ceramic substrate.

[0004] Patent document 3 discloses that: a bonding layer is provided between a low-temperature sintered multilayer substrate and an aluminum nitride substrate, and the two substrates are firmly bonded by the bonding layer; and glass paste is used as the bonding layer. Patent document 4 discloses a ceramic circuit substrate, which has a glass ceramic sheet mounted on an aluminum nitride substrate and has a hole for mounting a semiconductor chip in the center of the ceramic circuit substrate. Patent document 5 discloses that: a control wiring substrate is arranged on a laminated substrate via a bonding material; and the control wiring substrate is set as a multilayer substrate.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2018 / 181523

[0008] Patent Document 2: International Publication No. 2018 / 179538

[0009] Patent Document 3: Japanese Patent Application Laid-Open No. 4-288854

[0010] Patent Document 4: Japanese Patent Application Laid-Open No. 2-238642

[0011] Patent Document 5: Japanese Patent Application Publication No. 2021-141220 Summary of the invention

[0012] Problem that the invention aims to solve

[0013] In the existing semiconductor module, when the power semiconductor element mounted on the insulating circuit substrate is connected to the terminal housing or the external connection terminal via a connection member such as a bonding wire, a bonding area (connection area) needs to be provided on the insulating circuit substrate, and the semiconductor module is difficult to be miniaturized. In addition, when the printed circuit board is placed opposite to the upper side of the power semiconductor element mounted on the insulating circuit substrate and the power semiconductor element is connected to the printed circuit board via a pin terminal, the power semiconductor element and other components are hidden by the printed circuit board, making it difficult to perform alignment when installing the components and to inspect the joints, and the quality may be reduced.

[0014] In view of the above problems, an object of the present invention is to provide a semiconductor device that can be easily miniaturized and can suppress a decrease in quality.

[0015] Solutions for solving problems

[0016] The main purpose of one embodiment of the present invention is a semiconductor device comprising: a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip are arranged separately from each other, the first semiconductor chip and the second semiconductor chip each having a first main electrode on the upper surface side and a second main electrode on the lower surface side; and a printed circuit board, which is arranged around the first semiconductor chip and the second semiconductor chip, and has a plurality of wiring layers and an insulating layer arranged between the plurality of wiring layers, the plurality of wiring layers include a first wiring layer as the top layer and a second wiring layer as the bottom layer, the first wiring layer is electrically connected to the first main electrode of the first semiconductor chip via a connecting member, the second wiring layer is electrically connected to the first wiring layer via a passage, and the second wiring layer is electrically connected to the second main electrode of the second semiconductor chip.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to provide a semiconductor device that can be easily miniaturized and can suppress degradation in quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view of the semiconductor device according to the first embodiment.

[0020] Figure 2 So Figure 1 A vertical cross-sectional view obtained by cutting along the AA′ line.

[0021] Figure 3 This is a horizontal cross-sectional view through the lowest wiring layer of the printed circuit board.

[0022] Figure 4 It is a horizontal cross-sectional view passing through the wiring layer which is the second layer from the bottom of the printed circuit board.

[0023] Figure 5 It is a horizontal cross-sectional view passing through the wiring layer which is the third layer from the bottom of the printed circuit board.

[0024] Figure 6 It is a horizontal cross-sectional view through the uppermost wiring layer of the printed circuit board.

[0025] Figure 7 It is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0026] Figure 8 It is a cross-sectional view in the vertical direction of the semiconductor device according to the first comparative example.

[0027] Fig. 9 It is a side view of a semiconductor device according to a second comparative example.

[0028] Fig.10 It is a top view of the semiconductor device according to the second embodiment.

[0029] Fig.11 So Fig.10 A vertical cross-sectional view obtained by cutting along the AA′ line.

[0030] Fig.12 It is a top view of a semiconductor device according to a third embodiment.

[0031] Fig.13 So Fig.12 A vertical cross-sectional view obtained by cutting along the AA′ line.

[0032] Fig.14 It is a top view of a semiconductor device according to a fourth embodiment.

[0033] Fig.15 It is a vertical cross-sectional view of the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION

[0034] The first to fifth embodiments are described below with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar figure notations, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane dimensions, the ratio of thickness of each layer, etc. are sometimes different from the actual. In addition, the drawings may also contain parts with different dimensional relationships and ratios. In addition, the first to fifth embodiments shown below are examples of devices and methods for concretizing the technical ideas of the present invention. The technical ideas of the present invention do not specify the material, shape, structure, configuration, etc. of the structural components as the following materials, shapes, structures, configurations, etc.

[0035] In addition, regarding the "first main electrode" in this specification, if it is an insulated gate bipolar transistor (IGBT), the "first main electrode" refers to either the emitter electrode or the collector electrode. In the case of a field effect transistor (FET) or a static induction transistor (SIT), the "first main electrode" refers to either the source electrode or the drain electrode. In the case of a static induction thyristor (SI thyristor), a gate turn-off thyristor (GTO), or a diode, the "first main electrode" refers to either the anode electrode or the cathode electrode. In addition, regarding the "second main electrode", if it is an IGBT, the "second main electrode" refers to either the emitter electrode or the collector electrode that is not the first main electrode. In the case of a FET or a SIT, the "second main electrode" refers to either the source electrode or the drain electrode that is not the first main electrode. In the case of an SI thyristor, a GTO, or a diode, the "second main electrode" refers to either the anode electrode or the cathode electrode that is not the first main electrode. That is, if the "first main electrode" is a source electrode, the "second main electrode" refers to a drain electrode. If the "first main electrode" is an emitter electrode, the "second main electrode" refers to a collector electrode. If the "first main electrode" is an anode electrode, the "second main electrode" refers to a cathode electrode.

[0036] In addition, the definitions of directions such as "up", "down", "up and down", "left", "right", "left and right" in this specification are only for the convenience of explanation and are not used to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, "up and down" can be converted into "left and right" to read, and if the object is rotated 180° to observe, "up and down" can be reversed to read, which is self-evident.

[0037] (First Embodiment)

[0038] As the semiconductor device according to the first embodiment, a so-called “2-in-1” semiconductor module having functions corresponding to two power semiconductor elements is exemplified.

[0039] Figure 1is a top view of a semiconductor device according to the first embodiment, Figure 2 So Figure 1 The vertical cross-sectional view is obtained by cutting the AA′ line. Figure 1 and Figure 2 As shown, the semiconductor device involved in the first embodiment includes an insulating circuit substrate 1, power semiconductor elements (semiconductor chips) 3a~3d arranged on the upper surface side of the insulating circuit substrate 1, and a printed circuit board (multilayer substrate) 2 arranged on the upper surface side of the insulating circuit substrate 1 in a manner surrounding the side surfaces of the semiconductor chips 3a~3d.

[0040] like Figure 2 As shown, the insulating circuit substrate 1 includes an insulating substrate 11, conductive plates (circuit boards) 12a, 12b provided on the upper surface side of the insulating substrate 11 in a manner separated from each other, and a conductive plate (heat sink) 13 provided on the lower surface side of the insulating substrate 11. The insulating circuit substrate 1 may be, for example, a direct copper bonding (DCB) substrate, an active metal brazing (AMB) substrate, or the like. The insulating substrate 11 may be, for example, a ceramic substrate composed of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or a resin insulating substrate composed of a polymer material or the like. The circuit boards 12a, 12b and the heat sink 13 have a substantially rectangular plane pattern. The circuit boards 12a, 12b and the heat sink 13 may be, for example, composed of a conductive material such as a conductor foil composed of copper (Cu), aluminum (Al), or the like.

[0041] like Figure 2 As shown, the upper surface side of the circuit board 12a is bonded with the semiconductor chip 3a on the upper arm side via a bonding member 4c such as solder or sintered material, or by a direct bonding technique. The upper surface side of the circuit board 12b is bonded with the semiconductor chip 3b on the lower arm side via a bonding member 4d such as solder or sintered material, or by a direct bonding technique. Similar to the semiconductor chip 3a, the upper surface side of the circuit board 12a is bonded with the semiconductor chip 3b on the lower arm side via a bonding member 4d such as solder or sintered material, or by a direct bonding technique. Figure 1 The semiconductor chip 3c on the upper arm side is shown. Similar to the semiconductor chip 3b, the semiconductor chip 3d on the lower arm side is bonded to the upper surface of the circuit board 12b via a bonding member such as solder or sintered material, or by direct bonding technology.

[0042] The semiconductor chips 3a to 3d can be made of silicon (Si), for example, or can be made of wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), etc. The types of semiconductor chips 3a to 3d vary depending on the application, for example, power semiconductor elements such as field effect transistors (FET), insulated gate bipolar transistors (IGBT), electrostatic induction (SI) thyristors, gate turn-off (GTO) thyristors, and rectifier elements such as freewheeling diodes (FWD) can be used. In the semiconductor device involved in the first embodiment, the case where the semiconductor chips 3a to 3d are MOSFETs is exemplified.

[0043] exist Figure 1 and Figure 2 In the example, four semiconductor chips 3a to 3d are shown, but the number of semiconductor chips is not particularly limited and can be appropriately selected according to the rated current, etc. Figure 1 and Figure 2 As shown, the semiconductor chip 3a has a source electrode 32a as a first main electrode (upper surface electrode) and a gate electrode 31a as a control electrode on the upper surface side, and has a drain electrode 33a as a second main electrode (lower surface electrode) on the lower surface side. The semiconductor chip 3b has a source electrode 32b as a first main electrode (upper surface electrode) and a gate electrode 31b as a control electrode on the upper surface side, and has a drain electrode 33b as a second main electrode (lower surface electrode) on the lower surface side.

[0044] Figure 1 The semiconductor chip 3c shown has a source electrode 32c as a first main electrode (upper surface electrode) and a gate electrode 31c as a control electrode on the upper surface side, and has a drain electrode (not shown) as a second main electrode (lower surface electrode) on the lower surface side. Figure 1 The semiconductor chip 3d shown has a source electrode 32d as a first main electrode (upper surface electrode) and a gate electrode 31d as a control electrode on the upper surface side, and has a drain electrode (not shown) as a second main electrode (lower surface electrode) on the lower surface side.

[0045] like Figure 1 and Figure 2As shown, the printed circuit board 2 is provided on the upper surface side of the circuit boards 12a and 12b of the insulating circuit substrate 1. The printed circuit board 2 has a plurality of (multiple) wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o which are electrically connected to each other via vias (connecting members) such as via filling to electrically connect the source electrodes 32a and 32c of the semiconductor chips 3a and 3c with the drain main electrodes 33d of the semiconductor chips 3b and 3d, and an insulating layer 20 provided between the plurality of wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o.

[0046] Among the wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, and 24a to 24o, the first and lowest wiring layers (first wiring layers) 21a and 21b from the bottom are bonded to the insulating circuit board 1.

[0047] The second wiring layer (second wiring layer) 22a, 22b, 22d, 22e from the bottom among the multi-layer wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o is provided on the upper surface side of the first wiring layers 21a and 21b via the insulating layer 20. The second wiring layers 22a, 22b, 22d, 22e constitute a main circuit through which a main current flows, a control circuit for controlling the semiconductor chips 3a to 3d, and the like.

[0048] Among the multi-layer wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o, the third wiring layer from the bottom (third wiring layer) 23a, 23c, 23e, 23g is provided on the upper surface side of the second wiring layers 22a, 22b, 22d, 22e via the insulating layer 20. The third wiring layers 23a, 23c, 23e, 23g constitute a main circuit through which a main current flows, a control circuit for controlling the semiconductor chips 3a to 3d, and the like.

[0049] Among the multi-layer wiring layers 21a, 21b, 22a, 22b, 22d, 22e, 23a, 23c, 23e, 23g, 24a to 24o, the fourth and uppermost wiring layers (fourth wiring layers) 24a to 24o from the bottom are provided on the upper surface side of the third wiring layers 23a, 23c, 23e, 23g via the insulating layer 20. The fourth wiring layers 24a to 24o are provided with connection areas (bonding areas) for connection members such as bonding wires connected to the semiconductor chips 3a to 3d, and are equipped with external connection terminals for connection to an external circuit.

[0050] The insulating layer 20 is made of insulating materials such as ceramics or resins mainly composed of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. The insulating layer 20 may also be made of insulating materials such as polyimide resin, glass fiber and epoxy resin.

[0051] The first wiring layer 21a, 21b, the second wiring layer 22a, 22b, 22d, 22e, the third wiring layer 23a, 23c, 23e, 23g and the fourth wiring layer 24a~24o are composed of conductive materials such as copper (Cu), Cu alloy with Cu as the main component, aluminum (Al), or Al alloy with Al as the main component.

[0052] like Figure 2 As shown, the first wiring layers 21a and 21b are bonded to the circuit boards 12a and 12b of the insulating circuit substrate 1. The first wiring layer 21a is bonded to the circuit board 12a via a bonding member 4a such as solder or sintered material, or by a direct bonding technique. The first wiring layer 21b is bonded to the circuit board 12b via a bonding member 4b such as solder or sintered material, or by a direct bonding technique. The upper surface side of the first wiring layers 21a and 21b is bonded to the insulating layer 20.

[0053] like Figure 2 As shown, the second wiring layers 22a, 22b, 22d, and 22e are buried in the insulating layer 20. The second wiring layer 22a is arranged above the position overlapping with the first wiring layer 21a through the insulating layer 20. The second wiring layer 22b is arranged above the position overlapping with the first wiring layer 21a and a part of the first wiring layer 21b through the insulating layer 20. The second wiring layer 22b is electrically connected to the first wiring layer 21b via the via 81b penetrating the through hole provided in the insulating layer 20. The second wiring layer 22d is arranged above the position overlapping with a part of the first wiring layer 21b through the insulating layer 20. The second wiring layer 22e is arranged above the position overlapping with the first wiring layer 21b through the insulating layer 20.

[0054] like Figure 2As shown, the third wiring layers 23a, 23c, 23e, and 23g are buried in the insulating layer 20. The third wiring layer 23a is arranged above the position overlapping with the second wiring layer 22a through the insulating layer 20. The third wiring layer 23a is provided with a through hole 231. The third wiring layer 23c is arranged above the position overlapping with the second wiring layer 22b through the insulating layer 20. The third wiring layer 23c is electrically connected to the second wiring layer 22b via the vias 82e and 82f penetrating the through holes provided in the insulating layer 20. The third wiring layer 23e is arranged above the position overlapping with the second wiring layer 22d through the insulating layer 20. The third wiring layer 23e is electrically connected to the second wiring layer 22d through the via 82g penetrating the through holes provided in the insulating layer 20. The third wiring layer 23g is arranged above the position overlapping with the second wiring layer 22e through the insulating layer 20. The third wiring layer 23g is provided with a through hole 235 .

[0055] like Figure 2 As shown, the fourth wiring layer 24e, 24c, 24i, and 24m are bonded to the upper surface side of the insulating layer 20. The fourth wiring layer 24e is provided above the position overlapping with the third wiring layer 23a via the insulating layer 20. The fourth wiring layer 24e is electrically connected to the second wiring layer 22a via the via 82b penetrating the through hole provided in the insulating layer 20 and the through hole 231 provided in the third wiring layer 23a. The fourth wiring layer 24c is provided above the position overlapping with the third wiring layer 23c via the insulating layer 20. The fourth wiring layer 24c is electrically connected to the third wiring layer 23c via the vias 83e and 83f penetrating the through holes provided in the insulating layer 20.

[0056] The fourth wiring layer 24i is provided above the position overlapping with the third wiring layer 23e via the insulating layer 20. The fourth wiring layer 24i is electrically connected to the third wiring layer 23e via the via 83g penetrating the through hole provided in the insulating layer 20. The fourth wiring layer 24m is provided above the position overlapping with the third wiring layer 23g via the insulating layer 20. The fourth wiring layer 24m is electrically connected to the second wiring layer 22e via the via 82i penetrating the through hole provided in the insulating layer 20 and the through hole 235 provided in the third wiring layer 23g.

[0057] like Figure 1 As shown, the insulating layer 20 is provided with openings 2a to 2d in a manner surrounding the outer periphery (side) of the semiconductor chips 3a to 3d. The openings 2a to 2d penetrate from the upper surface to the lower surface of the insulating layer 20. The upper surfaces of the semiconductor chips 3a to 3d are exposed through the openings 2a to 2d. The fourth wiring layers 24a to 24o are provided at the mounting positions of the semiconductor chips 3a to 3d and around the openings 2a to 2d of the insulating layer 20.

[0058] On the fourth wiring layer 24a, the lower end of the control terminal (gate control terminal) 6a as an external connection terminal is bonded via a bonding member such as solder or sintered material, or by direct bonding technology. The gate control terminal 6a extends toward the top of the fourth wiring layer 24a. The upper end of the gate control terminal 6a is connected to an external circuit (not shown). The gate control terminal 6a is electrically connected to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c. The gate control terminal 6a applies a control signal for controlling the on and off of the semiconductor chips 3a and 3c to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c.

[0059] On the fourth wiring layer 24b, the lower end of the control terminal (auxiliary source terminal) 6b as an external connection terminal is joined via a joining member such as solder or sintered material, or by direct joining technology. The auxiliary source terminal 6b extends toward the top of the fourth wiring layer 24b. The upper end of the auxiliary source terminal 6b is connected to an external circuit (not shown). The auxiliary source terminal 6b is electrically connected to the source electrodes 32a and 32c of the semiconductor chips 3a and 3c. The auxiliary source terminal 6b is used to detect the current flowing through the semiconductor chips 3a and 3c.

[0060] The source electrode 32a of the semiconductor chip 3a is connected to the fourth wiring layer 24c via a bonding wire 72a as a connection member. Also, the source electrode 32c of the semiconductor chip 3c is connected to the fourth wiring layer 24c via a bonding wire 72b as a connection member.

[0061] like Figure 1 and Figure 2 As shown, on the fourth wiring layer 24c, the lower end of the output terminal 5c, which is an external connection terminal on the output side, is joined via a joining member 4e such as solder or sintered material, or by direct joining technology. The output terminal 5c extends toward the upper side of the insulating circuit substrate 1. The upper end of the output terminal 5c is connected to an external circuit (not shown). The output terminal 5c is electrically connected to the source electrodes 32a, 32c of the semiconductor chips 3a, 3c and the drain electrode 33b of the semiconductor chips 3b, 3d. When the semiconductor chips 3a, 3c are in the on state, the output terminal 5c allows the current from the source electrodes 32a, 32c of the semiconductor chips 3a, 3c to flow to the external circuit. When the semiconductor chips 3b, 3d are in the on state, the output terminal 5c provides the current from the external circuit to the drain electrode 33b of the semiconductor chips 3b, 3d.

[0062] like Figure 1As shown, the gate electrode 31a of the semiconductor chip 3a is connected to the fourth wiring layer 24d via the bonding wire 71a as a connecting member. The source electrode 32a of the semiconductor chip 3a is connected to the fourth wiring layer 24e via the bonding wire 73a as a connecting member. The gate electrode 31c of the semiconductor chip 3c is connected to the fourth wiring layer 24f via the bonding wire 71c as a connecting member. The source electrode 32c of the semiconductor chip 3c is connected to the fourth wiring layer 24g via the bonding wire 73c as a connecting member.

[0063] On the fourth wiring layer 24h, the lower end of the positive terminal (P terminal) 5a, which is an external connection terminal on the high potential side, is joined via a joining member such as solder or sintered material, or by direct joining technology. The P terminal 5a extends upward toward the fourth wiring layer 24h. The upper end of the P terminal 5a is connected to an external circuit (not shown). The P terminal 5a is electrically connected to the drain electrode 33a of the semiconductor chip 3a, 3c. The P terminal 5a supplies current to the drain electrode 33a of the semiconductor chip 3a, 3c via the external circuit.

[0064] The fourth wiring layer 24i is connected to the source electrode 32b of the semiconductor chip 3b via a bonding wire 72b as a connection member. Also, the fourth wiring layer 24i is connected to the source electrode 32d of the semiconductor chip 3d via a bonding wire 72d as a connection member.

[0065] On the fourth wiring layer 24i, the lower end of the negative terminal (N terminal) 5b, which is an external connection terminal on the low potential side, is joined via a joining member such as solder or sintered material, or by direct joining technology. The N terminal 5b extends toward the top of the fourth wiring layer 24i. The upper end of the N terminal 5b is connected to an external circuit (not shown). The N terminal 5b is electrically connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d. The N terminal 5b allows the current from the source electrodes 32b and 32d of the semiconductor chips 3b and 3d to flow to the external circuit.

[0066] On the fourth wiring layer 24j, the lower end of the control terminal (auxiliary source terminal) 6c as an external connection terminal is joined via a joining member such as solder or sintered material, or by direct joining technology. The auxiliary source terminal 6c extends toward the top of the fourth wiring layer 24j. The upper end of the auxiliary source terminal 6c is connected to an external circuit (not shown). The auxiliary source terminal 6c is electrically connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d. The auxiliary source terminal 6c is used to detect the current flowing through the semiconductor chips 3b and 3d.

[0067] On the fourth wiring layer 24k, the lower end of the control terminal (gate control terminal) 6d as an external connection terminal is bonded via a bonding member such as solder or sintered material, or using a direct bonding technique. The gate control terminal 6d extends toward the top of the fourth wiring layer 24k. The upper end of the gate control terminal 6d is connected to an external circuit (not shown). The gate control terminal 6d is electrically connected to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d. The gate control terminal 6d applies a control signal for controlling the on and off of the semiconductor chips 3b and 3d to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d.

[0068] The gate electrode 31b of the semiconductor chip 3b is connected to the fourth wiring layer 24l via a bonding wire 71b as a connecting member. The source electrode 32b of the semiconductor chip 3b is connected to the fourth wiring layer 24m via a bonding wire 73b as a connecting member. The gate electrode 31d of the semiconductor chip 3d is connected to the fourth wiring layer 24n via a bonding wire 71d as a connecting member. The source electrode 32d of the semiconductor chip 3d is connected to the fourth wiring layer 24o via a bonding wire 73d as a connecting member.

[0069] Figure 1 and Figure 2 The bonding wires 71a to 71d, 72a to 72d, and 73a to 73d shown as connecting members are made of a conductive material such as aluminum (Al). The thickness and number of the bonding wires 71a to 71d, 72a to 72d, and 73a to 73d are not particularly limited and can be adjusted as appropriate.

[0070] Figure 1 and Figure 2 The gate control terminals 6a, 6d, auxiliary source terminals 6b, 6c, P terminal 5a, N terminal 5b, and output terminal 5c shown are made of a conductive material made of a metal such as copper (Cu), a Cu alloy mainly composed of Cu, aluminum (Al), or an Al alloy mainly composed of Al. The gate control terminals 6a, 6d, auxiliary source terminals 6b, 6c, P terminal 5a, N terminal 5b, and output terminal 5c may be made of the same material as each other, or may be made of different materials.

[0071] exist Figure 1 and Figure 2In the embodiment, the gate control terminals 6a, 6d, the auxiliary source terminals 6b, 6c, the P terminal 5a, the N terminal 5b, and the output terminal 5c are exemplified as being cylindrical or rod-shaped, but the shapes of the gate control terminals 6a, 6d, the auxiliary source terminals 6b, 6c, the P terminal 5a, the N terminal 5b, and the output terminal 5c are not particularly limited, and for example, they may be in the shape of a polygonal column or a flat plate. The thickness of the gate control terminals 6a, 6d and the auxiliary source terminals 6b, 6c may be thinner than that of the P terminal 5a, the N terminal 5b, and the output terminal 5c.

[0072] Figure 3 2 is a horizontal cross-sectional view through the first wiring layers 21a and 21b of the printed circuit board 2. Figure 3 In FIG. 1 , the insulating layer 20 on the upper surface side of the first wiring layers 21a and 21b and the vias 81a and 81b connected to the upper surface side of the first wiring layers 21a and 21b are schematically shown by dotted lines. Figure 3 As shown, the first wiring layers 21a and 21b are provided separately from each other.

[0073] The first wiring layer 21a has a rectangular planar pattern. The first wiring layer 21a is provided with an opening 21x that surrounds the openings 2a and 2c of the insulating layer 20. A via 81a is connected to the upper surface side of the first wiring layer 21a. The number of vias 81a and the connection position are not particularly limited.

[0074] The first wiring layer 21b has a rectangular planar pattern. The first wiring layer 21b is provided with an opening 21y that surrounds the openings 2b and 2d of the insulating layer 20. A via 81b is connected to the upper surface side of the first wiring layer 21b. The number of vias 81b and the connection position are not particularly limited.

[0075] Figure 4 2 is a horizontal cross-sectional view through the second wiring layers 22a to 22e of the printed circuit board 2. Figure 4 In FIG. 1 , vias 82a to 82j connected to the upper surface side of the second wiring layers 22a to 22e are schematically shown by dotted lines. Figure 4 As shown, the second wiring layers 22 a to 22 e are provided to be separated from each other via the insulating layer 20 .

[0076] The second wiring layer 22a has an L-shaped planar pattern. The second wiring layer 22a is provided on the same side as the insulating layer 20. Figure 3 The first wiring layer 21a shown in FIG. is partially overlapped. Vias 82a to 82c are connected to the upper surface side of the second wiring layer 22a. The number of vias 82a to 82c and the connection position are not particularly limited. Figure 4A passage 82b is shown in FIG. Figure 2 Three passages 82b are shown.

[0077] The second wiring layer 22b has an L-shaped planar pattern. Figure 3 The first wiring layers 21a and 21b are provided above the positions overlapping with a part of the first wiring layers 21a and 21b. Figure 3 The second wiring layer 22b is electrically connected to the first wiring layer 21b through the via 81b. The vias 82e and 82f are connected to the upper surface of the second wiring layer 22b. The number of vias 82e and 82f and the connection position are not particularly limited. Figure 4 One passage 82e and one passage 82f are shown, but in Figure 2 Three passages 82e and three passages 82f are shown.

[0078] The second wiring layer 22c has a rectangular planar pattern. The second wiring layer 22c is provided on the insulating layer 20. Figure 3 The first wiring layer 21a shown in FIG. is partially overlapped with the first wiring layer 21a. Figure 3 The via 81a is shown. The second wiring layer 22c is electrically connected to the first wiring layer 21a through the via 81a. The via 82d is joined to the second wiring layer 22c. The number of vias 82d and the joining position are not particularly limited.

[0079] The second wiring layer 22d has a U-shaped planar pattern. The second wiring layer 22d is provided on the insulating layer 20. Figure 3 The first wiring layer 21b shown in FIG. 2 is partially overlapped with the first wiring layer 21b. A via 82g is connected to the second wiring layer 22d. The number of vias 82g and the connection position are not particularly limited. Figure 4 A passage 82g is shown in FIG. Figure 2 Three pathways 82g are shown.

[0080] The second wiring layer 22e has an L-shaped planar pattern. The second wiring layer 22e is provided on the same side as the insulating layer 20. Figure 3 The second wiring layer 22e is connected to vias 82h to 82j. The number of vias 82h to 82j and the connection position are not particularly limited. Figure 4 A passage 82i is shown in FIG. Figure 2 Three pathways 82i are shown.

[0081] Figure 5 FIG. 2 is a horizontal cross-sectional view through the third wiring layers 23a to 23g of the printed circuit board 2. Figure 5 In FIG. 1 , vias 83a to 83j connected to the upper surface side of the third wiring layers 23a to 23g are schematically shown by dotted lines. Figure 5 As shown, the third wiring layers 23 a to 23 g are provided to be separated from each other via the insulating layer 20 .

[0082] The third wiring layer 23a has a rectangular planar pattern. The third wiring layer 23a is provided on the same side as the insulating layer 20. Figure 4 The third wiring layer 23a is provided with through holes 231 and 232 for the vias 82b and 82c to pass through. The vias 83a to 83c are joined to the upper surface side of the third wiring layer 23a. The number of vias 83a to 83c and the joining position are not particularly limited.

[0083] The third wiring layer 23b has a rectangular planar pattern. The third wiring layer 23b is provided on the insulating layer 20. Figure 4 The third wiring layer 23b is provided with a through hole 233 through which the via 82a passes.

[0084] The third wiring layer 23c has an L-shaped planar pattern. The third wiring layer 23c is provided on the insulating layer 20. Figure 4 The third wiring layer 23c is bonded to the lower surface side of the third wiring layer 23c. Figure 4 The vias 82e and 82f are shown. The third wiring layer 23c is electrically connected to the second wiring layer 22b through the vias 82e and 82f. The vias 83e and 83f are joined to the upper surface of the third wiring layer 23c. The number of vias 83e and 83f and the joining positions are not particularly limited. Figure 5 One passage 83e and one passage 83f are shown, but in Figure 2 Three passages 83e and three passages 83f are shown.

[0085] The third wiring layer 23d has a rectangular planar pattern. The third wiring layer 23d is provided on the same side as the insulating layer 20. Figure 4 The third wiring layer 23d is bonded to the lower surface side of the third wiring layer 23d. Figure 4 The via 82d is shown. The third wiring layer 23d is electrically connected to the second wiring layer 22c through the via 82d. The via 83d is joined to the upper surface side of the third wiring layer 23d. The number of vias 83d and the joining position are not particularly limited.

[0086] The third wiring layer 23e has a U-shaped planar pattern. Figure 4 The third wiring layer 23e is bonded to the lower surface side of the third wiring layer 23e. Figure 4 The third wiring layer 23e is electrically connected to the second wiring layer 22d through the via 82g. The via 83g is bonded to the upper surface of the third wiring layer 23e. The number of vias 83g and the bonding position are not particularly limited. Figure 5 A passage 83g is shown in FIG. Figure 2 Three pathways 83g are shown.

[0087] The third wiring layer 23f has a rectangular planar pattern. The third wiring layer 23f is provided on the same side as the insulating layer 20. Figure 4 The third wiring layer 23f is provided with a through hole 234 through which the via 82h passes.

[0088] The third wiring layer 23g has a rectangular planar pattern. The third wiring layer 23g is provided on the same side as the insulating layer 20. Figure 4 The third wiring layer 23g is provided with through holes 235 and 236 for the vias 82i and 82j to pass through. The vias 83h to 83j are joined to the upper surface side of the third wiring layer 23g. The number of vias 83h to 83j and the joining position are not particularly limited.

[0089] Figure 6 FIG. 2 is a horizontal cross-sectional view passing through the fourth wiring layers 24a to 24o of the printed circuit board 2. Figure 6 In FIG. 1 , the insulating layer 20 on the lower surface side of the fourth wiring layers 24a to 24o is schematically shown by a dotted line. Figure 6 As shown, the fourth wiring layers 24a to 24o are provided separately from each other.

[0090] The fourth wiring layer 24a has a rectangular planar pattern. The fourth wiring layer 24a is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23a shown in FIG. is partially overlapped. The fourth wiring layer 24a is bonded to the lower surface side. Figure 5 The fourth wiring layer 24a is electrically connected to the third wiring layer 23a through the via 83a.

[0091] The fourth wiring layer 24b has a rectangular planar pattern. The fourth wiring layer 24b is provided on the same plane as the insulating layer 20. Figure 5The third wiring layer 23b is overlapped with the third wiring layer 23b shown in FIG. Figure 5 The via 82a is shown. The fourth wiring layer 24b is electrically connected to the second wiring layer 22a through the via 82a.

[0092] The fourth wiring layer 24c has an L-shaped planar pattern. The fourth wiring layer 24c is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23c shown in FIG. is overlapped with the third wiring layer 23c. The fourth wiring layer 24c is bonded to the lower surface side. Figure 5 The fourth wiring layer 24c is electrically connected to the third wiring layer 23c through the vias 83e and 83f.

[0093] The fourth wiring layer 24d has a rectangular planar pattern. The fourth wiring layer 24d is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23a shown in FIG. is partially overlapped. Figure 5 The fourth wiring layer 24d is electrically connected to the third wiring layer 23a through the via 83b.

[0094] The fourth wiring layer 24e has a rectangular planar pattern. The fourth wiring layer 24e is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23a shown in FIG. is partially overlapped with the third wiring layer 23a. Figure 5 The via 82b is shown. The fourth wiring layer 24e is electrically connected to the second wiring layer 22a through the via 82b.

[0095] The fourth wiring layer 24f has a rectangular planar pattern. The fourth wiring layer 24f is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23a shown in FIG. is partially overlapped. The fourth wiring layer 24f is bonded to the lower surface side. Figure 5 The via 83c is shown. The fourth wiring layer 24f is electrically connected to the third wiring layer 23a through the via 83c.

[0096] The fourth wiring layer 24g has a rectangular planar pattern. The fourth wiring layer 24g is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23a shown in FIG. is partially overlapped. Figure 5 The via 82c is shown. The fourth wiring layer 24g is electrically connected to the second wiring layer 22a through the via 82c.

[0097] The fourth wiring layer 24h has a rectangular planar pattern. The fourth wiring layer 24h is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23d is overlapped with the third wiring layer 23d shown in FIG. Figure 5 The fourth wiring layer 24h is electrically connected to the third wiring layer 23d through the via 83d.

[0098] The fourth wiring layer 24i has a U-shaped planar pattern. The fourth wiring layer 24i is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23e is overlapped with the third wiring layer 23e shown in FIG. Figure 5 The via 83g is shown. The fourth wiring layer 24i is electrically connected to the third wiring layer 23e through the via 83g.

[0099] The fourth wiring layer 24j has a rectangular planar pattern. The fourth wiring layer 24j is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23f is overlapped with the third wiring layer 23f shown in FIG. Figure 5 The via 82h is shown. The fourth wiring layer 24j is electrically connected to the second wiring layer 22e through the via 82h.

[0100] The fourth wiring layer 24k has a rectangular planar pattern. The fourth wiring layer 24k is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23g shown in FIG. is partially overlapped with the third wiring layer 23g. Figure 5 The fourth wiring layer 24k is electrically connected to the third wiring layer 23g through the via 83h.

[0101] The fourth wiring layer 241 has a rectangular planar pattern. The fourth wiring layer 241 is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23g shown in FIG. is partially overlapped with the third wiring layer 23g. Figure 5 The fourth wiring layer 241 is electrically connected to the third wiring layer 23g through the via 83i.

[0102] The fourth wiring layer 24m has a rectangular planar pattern. The fourth wiring layer 24m is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23g shown in FIG. is partially overlapped. Figure 5The via 82i is shown. The fourth wiring layer 24m is electrically connected to the second wiring layer 22e through the via 82i.

[0103] The fourth wiring layer 24n has a rectangular planar pattern. The fourth wiring layer 24n is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23g shown in FIG. is partially overlapped. Figure 5 The fourth wiring layer 24n is electrically connected to the third wiring layer 23g through the via 83j.

[0104] The fourth wiring layer 24o has a rectangular planar pattern. The fourth wiring layer 24o is provided on the same plane as the insulating layer 20. Figure 5 The third wiring layer 23g shown in FIG. is partially overlapped with the third wiring layer 23g. Figure 5 The via 82j is shown. The fourth wiring layer 24o is electrically connected to the second wiring layer 22e through the via 82j.

[0105] Figure 7 An example of an equivalent circuit of the semiconductor device according to the first embodiment is shown. Figure 7 As shown, the semiconductor device according to the first embodiment constitutes a part of a three-phase bridge circuit.

[0106] The drain-side terminal P is connected to the second main electrode (drain electrode) of the transistor T1 on the upper arm side, and the source-side terminal N is connected to the first main electrode (source electrode) of the transistor T2 on the lower arm side. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1. The source electrode of the transistor T2 is connected to the auxiliary source terminal S2.

[0107] The gate electrode of the transistor T1 is connected to the gate control terminal G1. The gate electrode of the transistor T2 is connected to the gate control terminal G2. The transistor T1 has a body diode D1 as a freewheeling diode (FWD) connected in reverse parallel. The transistor T2 has a body diode D2 as a freewheeling diode (FWD) connected in reverse parallel.

[0108] Figure 7 The drain side terminal P, source side terminal N and output terminal U shown are Figure 1 The P terminal 5a, N terminal 5b and output terminal 5c shown correspond. Figure 7 The transistor T1 shown with Figure 1 The semiconductor chips 3a, 3c shown correspond. Figure 7 The transistor T2 shown with Figure 1 The semiconductor chips 3b and 3d shown correspond. Figure 7 The gate control terminals G1, G2 and Figure 1 The gate control terminals 6a, 6d shown correspond. Figure 7 The auxiliary source terminals S1, S2 are shown with Figure 1 The auxiliary source terminals 6b, 6c shown correspond.

[0109] exist Figure 1 and Figure 2 During the switching operation of the semiconductor device according to the first embodiment shown, a control signal for controlling the on / off of the semiconductor chips 3a and 3c is applied to the gate electrodes 31a and 31c of the semiconductor chips 3a and 3c via the gate control terminal 6a, and a control signal for controlling the on / off of the semiconductor chips 3b and 3d is applied to the gate electrodes 31b and 31d of the semiconductor chips 3b and 3d via the gate control terminal 6d. Thus, the semiconductor chips 3a and 3c and the semiconductor chips 3b and 3d are alternately turned on and off repeatedly.

[0110] When the semiconductor chips 3a and 3c on the upper arm side are in the on state, the current entering from the P terminal 5a flows to the drain electrode 33a of the semiconductor chips 3a and 3c via the fourth wiring layer 24h, the via 83d, the third wiring layer 23d, the via 82d, the second wiring layer 22c, the via 81a and the first wiring layer 21a of the printed circuit board 2, and the circuit board 12a. In addition, the current from the source electrodes 32a and 32c of the semiconductor chips 3a and 3c flows from the output terminal 5c to the external circuit via the bonding wires 72a and 72c and the fourth wiring layer 24c of the printed circuit board 2.

[0111] In addition, when the semiconductor chips 3b and 3d on the lower arm side are in the on state, the current entering the output terminal 5c from the external circuit flows to the drain electrode 33b of the semiconductor chips 3b and 3d on the lower arm side via the fourth wiring layer 24i, the path 83g, the third wiring layer 23e, the path 82g, the second wiring layer 22d, the path 81b and the first wiring layer 21b of the printed circuit board 2, and the circuit board 12b. Moreover, the current from the source electrodes 32b and 32d of the semiconductor chips 3b and 3d flows from the N terminal 5b to the external circuit via the bonding wires 72b and 72d and the fourth wiring layer 24i of the printed circuit board 2.

[0112] <Method for manufacturing semiconductor device>

[0113] Next, an example of a method for manufacturing (assembling method) the semiconductor device according to the first embodiment will be described. Figure 1 and Figure 2The insulating circuit substrate 1 and the printed circuit board 2 are shown. Then, the first wiring layers 21a and 21b of the bottom layer of the printed circuit board 2 are bonded to the upper surface side of the circuit boards 12a and 12b of the insulating circuit substrate 1. Next, the printed circuit board 2 is used as a jig for alignment, and the semiconductor chips 3a and 3c are aligned by means of the openings 2a and 2c of the printed circuit board 2, and the semiconductor chips 3a and 3c are bonded to the upper surface side of the circuit board 12a of the insulating circuit substrate 1. In addition, the semiconductor chips 3b and 3d are aligned by means of the openings 2b and 2d of the printed circuit board 2, and the semiconductor chips 3b and 3d are bonded to the upper surface side of the circuit board 12b of the insulating circuit substrate 1.

[0114] Then, if Figure 1 As shown, the gate control terminal 6a is joined to the fourth wiring layer 24a on the top layer of the printed circuit board 2, the auxiliary source terminal 6b is joined to the fourth wiring layer 24b, the output terminal 5c is joined to the fourth wiring layer 24c, the P terminal 5a is joined to the fourth wiring layer 24h, the N terminal 5b is joined to the fourth wiring layer 24i, the auxiliary source terminal 6c is joined to the fourth wiring layer 24j, and the gate control terminal 6a is joined to the fourth wiring layer 24k.

[0115] Next, the fourth wiring layer 24d, 24l, 24f, 24n on the top of the printed circuit board 2 is connected to the gate electrodes 31a to 31d of the semiconductor chips 3a to 3d, respectively, using bonding wires 71a to 71d. The fourth wiring layer 24c on the top of the printed circuit board 2 is connected to the source electrodes 32a and 32c of the semiconductor chips 3a and 3c, respectively, using bonding wires 72a and 72c. The fourth wiring layer 24i on the top of the printed circuit board 2 is connected to the source electrodes 32b and 32d of the semiconductor chips 3b and 3d, respectively, using bonding wires 72b and 72d. The fourth wiring layer 24e, 24g, 24m, 24o on the top of the printed circuit board 2 is connected to the source electrodes 32a to 32d of the semiconductor chips 3a to 3d, respectively, using bonding wires 73a to 73d.

[0116] Next, the semiconductor chips 3a to 3d and the printed circuit board 2 are sealed with a sealing member as required. Figure 1 and Figure 2 The semiconductor device according to the first embodiment shown is completed.

[0117] <First Comparative Example>

[0118] Next, a semiconductor device according to a first comparative example is described. Figure 8As shown, a semiconductor chip 103 is bonded to the upper surface side of the insulating circuit substrate 102 via solder 109. A terminal housing 104 and external connection terminals 105 and 106 are connected to the upper surfaces of the insulating circuit substrate 102 and the semiconductor chip 103 via bonding wires (aluminum wires) 110 and 111. A copper base 101 is bonded to the lower surface side of the insulating circuit substrate 102 via solder 108. The periphery of the semiconductor chip 103 is covered with a gel sealing member 107.

[0119] In the semiconductor device according to the first comparative example, a bonding region needs to be provided on the upper surface side of the insulating circuit substrate 102 in order to form a circuit, and it is difficult to miniaturize the module. Figure 1 and Figure 2 As shown, a multilayered printed circuit board 2 is arranged around the semiconductor chips 3a~3d, thereby enabling connection areas such as bonding areas to be provided on the top layer of the printed circuit board 2, and forming a main circuit and a control circuit on a layer different from the connection area inside the printed circuit board 2, so that the semiconductor module can be miniaturized (high-density mounting).

[0120] <Second Comparative Example>

[0121] Next, a semiconductor device according to a second comparative example will be described. Fig. 9 As shown, the semiconductor device according to the second comparative example includes an insulating circuit substrate 201, which includes an insulating substrate 211, circuit boards 212a and 212b provided on the upper surface side of the insulating substrate 211, and a heat sink 213 provided on the lower surface side of the insulating substrate 211. Semiconductor chips 202a and 202b are bonded to the upper surface sides of the circuit boards 212a and 212b.

[0122] A printed circuit board 204 is provided above the semiconductor chips 202a and 202b. The semiconductor chips 202a and 202b are connected to the printed circuit board 204 via post electrodes (pin terminals) 203a and 203b. The printed circuit board 204 includes an insulating layer 241, a wiring layer 242 on the upper surface side of the insulating layer 241, and a wiring layer 243 on the lower surface side of the insulating layer 241. An external connection terminal 206a is bonded to the upper surface side of the circuit board 212a. An external connection terminal 206b is bonded to the upper surface side of the wiring layer 242. An external connection terminal 206c is bonded to the upper surface side of the circuit board 212b.

[0123] In the structure in which the printed circuit board 204 is arranged above the semiconductor chips 202a and 202b and the semiconductor chips 202a and 202b are connected to the printed circuit board 204 through the pillar electrodes 203a and 203b as in the semiconductor device involved in the second comparative example, there is no need to provide a bonding area as in the semiconductor device involved in the first comparative example, so it is easy to miniaturize. However, since the printed circuit board 204 above the semiconductor chips 202a and 202b hides the components such as the semiconductor chips 202a and 202b, it is difficult to align the components during installation and inspect the joints, and the quality may be reduced. In contrast, according to the semiconductor device involved in the first embodiment, Figure 1 and Figure 2 As shown, when the semiconductor device according to the first embodiment is viewed from above, the upper surfaces of the semiconductor chips 3a to 3d are exposed through the openings 2a to 2d of the printed circuit board 2. As a result, the arrangement of components such as the semiconductor chips 3a to 3d can be confirmed, and alignment during component mounting and inspection of the joints can be easily performed, thereby suppressing a decrease in quality and improving reliability.

[0124] Furthermore, according to the semiconductor device involved in the first embodiment, during chip mounting, compared with the conventional method of using a jig such as a carbon jig to align the semiconductor chip, the printed circuit board 2 itself functions as a jig, and the semiconductor chips 3a to 3d can be mounted in the openings 2a to 2d of the printed circuit board 2. Thus, a jig such as a carbon jig is not required, and chip mounting is easy.

[0125] Furthermore, according to the semiconductor device involved in the first embodiment, the printed circuit board 2 is joined to the upper surface side of the insulating circuit substrate 1. Therefore, compared with the case where the printed circuit board is arranged above the semiconductor chip as in the semiconductor device involved in the second comparative example, it is easy to transfer the heat of the printed circuit board 2 to the insulating circuit substrate 1 and easy to cool the printed circuit board 2.

[0126] Furthermore, according to the semiconductor device according to the first embodiment, the gate control terminal 6a is electrically connected to the gate control terminal 6a. Figure 5 The third wiring layer 23a shown is electrically connected to the auxiliary source terminal 6b. Figure 4 The second wiring layer 22a shown is arranged to face each other with the insulating layer 20 interposed therebetween and to electrically connect the gate control terminal 6d. Figure 5 The third wiring layer 23g shown is electrically connected to the auxiliary source terminal 6c. Figure 4 The second wiring layer 22e shown is arranged to face each other via the insulating layer 20. Thus, currents flow in opposite directions between the third wiring layer 23a and the second wiring layer 22a, and between the third wiring layer 23g and the second wiring layer 22e, thereby reducing wiring inductance.

[0127] (Second Embodiment)

[0128] Fig.10 is a top view of a semiconductor device according to a second embodiment. Fig.11 So Fig.10 The semiconductor device according to the second embodiment is a vertical cross-sectional view obtained by cutting along the AA′ line. Figure 1 and Figure 2 The structure of the semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.10 and Fig.11 As shown, the source electrodes 32a, 32c of the semiconductor chips 3a, 3c are connected to the fourth wiring layer 24c of the printed circuit board 2 via lead frames 81, 83 as connecting components, and the source electrodes 32b, 32d of the semiconductor chips 3b, 3d are connected to the fourth wiring layer 24i of the printed circuit board 2 via lead frames 82, 84 as connecting components.

[0129] One end of the lead frame 81 is bonded to the source electrode 32a of the semiconductor chip 3a, and the other end of the lead frame 81 is bonded to the fourth wiring layer 24c. One end of the lead frame 82 is bonded to the source electrode 32b of the semiconductor chip 3b, and the other end of the lead frame 82 is bonded to the fourth wiring layer 24i. One end of the lead frame 83 is bonded to the source electrode 32c of the semiconductor chip 3c, and the other end of the lead frame 83 is bonded to the fourth wiring layer 24c. One end of the lead frame 84 is bonded to the source electrode 32d of the semiconductor chip 3d, and the other end of the lead frame 84 is bonded to the fourth wiring layer 24i. The other structures of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, repeated descriptions are omitted.

[0130] According to the semiconductor device involved in the second embodiment, similarly to the semiconductor device involved in the first embodiment, the semiconductor module can be miniaturized (high-density mounting), and alignment during component mounting and inspection of the joint portion can be easily performed, thereby suppressing the degradation of quality. Furthermore, by using lead frames 81 to 84 as connecting members, reliability can be improved.

[0131] (Third Embodiment)

[0132] Fig.12 is a top view of a semiconductor device according to a third embodiment. Fig.13 So Fig.12 The semiconductor device according to the third embodiment is a vertical cross-sectional view obtained by cutting along the AA′ line. Figure 1 and Figure 2 The structure of the semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.12 and Fig.13 As shown, the semiconductor chips 3a to 3d are connected to fourth wiring layers 24c, 24d, 24e, 24f, 24g, 24i, 241, 24m, 24n, and 24o via flexible substrates 9a to 9d as connection members.

[0133] The flexible substrate 9a includes an insulating film (insulating layer) 90a, and copper foils (conductive layers) 91a, 92a, and 93a provided on the lower surface side of the insulating film 90a. Fig.12 In FIG. 1 , copper foils 91a, 92a, and 93a hidden under the insulating film 90a are schematically shown by dotted lines. The same is true for the flexible substrates 9b to 9d. The copper foil 91a connects the fourth wiring layer 24d with the gate electrode 31a of the semiconductor chip 3a (see FIG. 1 ). Figure 1 ) is electrically connected. The copper foil 92a connects the fourth wiring layer 24e to the source electrode 32a (see Figure 1 ) is electrically connected. The copper foil 93a connects the source electrode 32a (see Figure 1 ) is electrically connected to the fourth wiring layer 24c.

[0134] like Fig.13 As shown, the thickness of copper foil 92a is thinner than the thickness of copper foil 93a. Copper foil 92a is bonded to source electrode 32a of semiconductor chip 3a via copper bump 94a. Fig.12 The thickness of the copper foil 91a shown is thinner than the thickness of the copper foil 93a. The copper foil 91a is bonded to the gate electrode 31a of the semiconductor chip 3a via a copper bump (not shown) similar to the copper bump 94a.

[0135] The flexible substrate 9b includes an insulating film 90b and copper foils 91b, 92b, and 93b provided on the lower surface of the insulating film 90b. The copper foil 91b connects the fourth wiring layer 241 with the gate electrode 31b of the semiconductor chip 3b (see Figure 1 ) is electrically connected. The copper foil 92b connects the fourth wiring layer 24m to the source electrode 32b (see Figure 1 ) is electrically connected. The copper foil 93b connects the source electrode 32b (see Figure 1 ) is electrically connected to the fourth wiring layer 24i.

[0136] like Fig.13 As shown, the thickness of copper foil 92b is thinner than the thickness of copper foil 93b. Copper foil 92b is bonded to source electrode 32b of semiconductor chip 3b via copper bump 94b. Fig.12 The thickness of copper foil 91b shown is thinner than that of copper foil 93b. Copper foil 91b is bonded to gate electrode 31b of semiconductor chip 3b via copper bumps (not shown) similar to copper bumps 94b.

[0137] Fig.12 The flexible substrate 9c shown in the figure includes an insulating film 90c and copper foils 91c, 92c, and 93c provided on the lower surface side of the insulating film 90c. The copper foil 91c connects the fourth wiring layer 24f with the gate electrode 31c of the semiconductor chip 3c (see Figure 1 ) is electrically connected. The copper foil 92c connects the fourth wiring layer 24g to the source electrode 32c (see Figure 1 ) is electrically connected. The copper foil 93c connects the source electrode 32c (see Figure 1 ) is electrically connected to the fourth wiring layer 24c. The structure of the flexible substrate 9c is the same as that of the flexible substrates 9a and 9b.

[0138] Fig.12 The flexible substrate 9d shown in the figure includes an insulating film 90d and copper foils 91d, 92d, and 93d provided on the lower surface side of the insulating film 90d. The copper foil 91d connects the fourth wiring layer 24n with the gate electrode 31d (see Figure 1 ) is electrically connected. The copper foil 92d connects the fourth wiring layer 24o to the source electrode 32d (see Figure 1 ) is electrically connected. The copper foil 93d connects the source electrode 32d (see Figure 1 ) is electrically connected to the fourth wiring layer 24i. The structure of the flexible substrate 9d is the same as that of the flexible substrates 9a and 9b. The other structures of the semiconductor device involved in the third embodiment are the same as those of the semiconductor device involved in the first embodiment, so repeated descriptions are omitted.

[0139] According to the semiconductor device involved in the third embodiment, similarly to the semiconductor device involved in the first embodiment, the semiconductor module can be miniaturized (high-density mounting), and alignment during component mounting and inspection of the joint portion can be easily performed, thereby suppressing the degradation of quality. Furthermore, by using the flexible substrates 9a to 9d as the connecting members, the reliability can be improved.

[0140] (Fourth Embodiment)

[0141] Fig.14 is a top view of a semiconductor device according to a fourth embodiment. Figure 1 The structure of the semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.14As shown in the figure, the insulating layer 20 of the printed circuit board 2 is not provided between the semiconductor chips 3a and 3c, and between the semiconductor chips 3b and 3d. The opening 2a surrounding the semiconductor chip 3a provided in the insulating layer 20 of the printed circuit board 2 is continuous with the opening 2c surrounding the semiconductor chip 3c. In addition, the opening 2b surrounding the semiconductor chip 3b provided in the insulating layer 20 of the printed circuit board 2 is continuous with the opening 2d surrounding the semiconductor chip 3d. The other structures of the semiconductor device involved in the fourth embodiment are the same as those of the semiconductor device involved in the first embodiment, and therefore, repeated descriptions are omitted.

[0142] According to the semiconductor device according to the fourth embodiment, similarly to the semiconductor device according to the first embodiment, the semiconductor module can be miniaturized (high-density mounting), and alignment during component mounting and inspection of bonding portions can be easily performed, thereby suppressing quality degradation.

[0143] (Fifth Embodiment)

[0144] Fig.15 is a cross-sectional view of a semiconductor device according to a fifth embodiment. Figure 2 The structure of the semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.15 As shown, the insulating circuit substrate 1 is not provided, and semiconductor chips 3 a and 3 b are provided on a part of the printed circuit board 2 .

[0145] The first wiring layers 21a and 21b of the printed circuit board 2 are buried in the insulating layer 20. A metal plate 7 is provided on the lower surface side of the first wiring layers 21a and 21b via the insulating layer 20. The metal plate 7 can be made of metal such as copper.

[0146] A portion of the upper surface of the first wiring layer 21a, 21b is exposed from the openings 2a, 2b of the insulating layer 20. A semiconductor chip 3a is bonded to the exposed upper surface of the first wiring layer 21a. The semiconductor chip 3a is disposed inside the opening 2a. A semiconductor chip 3b is bonded to the exposed upper surface of the first wiring layer 21b. The semiconductor chip 3b is disposed inside the opening 2b. The other structures of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0147] According to the semiconductor device according to the fifth embodiment, similarly to the semiconductor device according to the first embodiment, the semiconductor module can be miniaturized (high-density mounting), and alignment during component mounting and inspection of bonding portions can be easily performed, thereby suppressing a decrease in quality.

[0148] (Other embodiments)

[0149] As described above, the present invention is described through the first to fifth embodiments, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, those skilled in the art should be able to clearly understand various alternative embodiments, examples, and application technologies.

[0150] For example, the semiconductor device according to the first to fifth embodiments illustrates a "two-in-one" structure having functions corresponding to two power semiconductor elements, but is not limited to this and can also be applied to a "one-in-one" structure having functions corresponding to one power semiconductor element.

[0151] In addition, as the semiconductor device involved in the first embodiment to the fifth embodiment, the printed circuit board 2 is illustrated as having four wiring layers, but it is not limited to this, and the number of layers can be appropriately adjusted according to the complexity of the circuit pattern, the size of the main current, etc. For example, the printed circuit board 2 can also have more than five wiring layers. In addition, it is also possible to set the third wiring layer 23a, 23g electrically connected to the gate control terminal 6a, 6d and the second wiring layer 22a, 22e electrically connected to the auxiliary source terminal 6b, 6c to the same layer, or not set the auxiliary source terminal 6b, 6c, etc., so that the printed circuit board 2 has three wiring layers.

[0152] In addition, in the semiconductor devices involved in the first to fifth embodiments, the third wiring layers 23a and 23g electrically connected to the gate control terminals 6a and 6d are set as the upper layer, and the second wiring layers 22a and 22e electrically connected to the auxiliary source terminal 6b are set as the lower layer, but the upper and lower relationship can also be reversed.

[0153] In addition, the structures disclosed in the first embodiment to the fifth embodiment can be appropriately combined within the scope that does not cause contradictions. In this way, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined only by the inventive features involved in the claims that are appropriate based on the above description.

[0154] Description of Reference Numerals

[0155] 1: insulating circuit substrate; 2a-2d: opening; 3a-3d: semiconductor chip; 4a-4e: bonding member; 5a: P terminal; 5b: N terminal; 5c: output terminal; 6a, 6d: gate control terminal; 6b, 6c: auxiliary source terminal; 7: metal plate; 9a-9d: flexible substrate; 11: insulating substrate; 12a, 12b: circuit board; 13: heat sink; 20: insulating layer; 21x, 21y: opening; 21 a, 21b, 22a~22e, 23a~22e, 24a~24o: wiring layer; 31a~31d: gate electrode; 32a~32d: source electrode; 33a, 33b: drain electrode; 71a~71d, 72a~72d, 73a~73d: bonding wire; 81~84: lead frame; 81a, 81b, 82a~82j, 83a~83j: via; 90a~90d: insulating film; 91a~ 91d, 92a-92d, 93a-93d: copper foil; 94a, 94b: copper bump; 101: copper substrate; 102: insulating circuit substrate; 103: semiconductor chip; 104: terminal housing; 105, 106: external connection terminals; 107: gel sealing member; 110, 111: bonding wire; 201: insulating circuit substrate; 202a, 202b: semiconductor chip; 203a, 203b: post electrode; 204 : Printed circuit board; 206a~206c: external connection terminals; 211: insulating substrate; 212a, 212b: circuit board; 213: heat sink; 231~236: through holes; 241: insulating layer; 242, 242: wiring layer; D1, D2: body diode; G1, G2: gate control terminals; N: source side terminal; P: drain side terminal; S1, S2: auxiliary source terminals; T1, T2: transistors; U: output terminal.

Claims

1. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being provided separately from each other, the first semiconductor chip and the second semiconductor chip each having a first main electrode on an upper surface side and a second main electrode on a lower surface side; and A printed circuit board is arranged around the first semiconductor chip and the second semiconductor chip, and has a plurality of wiring layers and an insulating layer arranged between the plurality of wiring layers, the plurality of wiring layers including an uppermost first wiring layer and a lowermost second wiring layer, the first wiring layer is electrically connected to the first main electrode of the first semiconductor chip via a connecting member, the second wiring layer is electrically connected to the first wiring layer via a passage, and the second wiring layer is electrically connected to the second main electrode of the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein The connection member is any one of a bonding wire, a lead frame, and a flexible substrate.

3. The semiconductor device according to claim 1 or 2, wherein: The device further includes an external connection terminal electrically connected to the first wiring layer.

4. The semiconductor device according to claim 1 or 2, wherein: The multi-layer wiring layer further includes an uppermost third wiring layer, the third wiring layer being provided separately from the first wiring layer and electrically connected to the first main electrode of the second semiconductor chip via a connecting member.

5. The semiconductor device according to claim 4, wherein: An external connection terminal electrically connected to the third wiring layer is further provided.

6. The semiconductor device according to claim 1 or 2, wherein: The multi-layer wiring layer further comprises: a lowermost third wiring layer provided separately from the second wiring layer, the third wiring layer being electrically connected to the second main electrode of the first semiconductor chip; and The fourth wiring layer as the uppermost layer is provided separately from the first wiring layer, and the fourth wiring layer is electrically connected to the third wiring layer through a via.

7. The semiconductor device according to claim 6, wherein: An external connection terminal electrically connected to the fourth wiring layer is further provided.

8. The semiconductor device according to claim 1 or 2, wherein: The first semiconductor chip further has a control electrode on the upper surface side. The multi-layer wiring layer further comprises: an uppermost third wiring layer provided separately from the first wiring layer, the third wiring layer being electrically connected to the control electrode of the first semiconductor chip via a connecting member; a fourth wiring layer which is lower than the third wiring layer and is electrically connected to the third wiring layer via a via; as well as The fifth wiring layer as the uppermost layer is provided separately from the first wiring layer and the third wiring layer, and the fifth wiring layer is electrically connected to the fourth wiring layer through a via.

9. The semiconductor device according to claim 8, wherein: The device further includes a first control terminal electrically connected to the fifth wiring layer.

10. The semiconductor device according to claim 8, wherein The multi-layer wiring layer further comprises: an uppermost sixth wiring layer provided separately from the first wiring layer, the third wiring layer, and the fifth wiring layer, the sixth wiring layer being electrically connected to the first main electrode of the first semiconductor chip via a connecting member; a seventh wiring layer which is lower than the fourth wiring layer and is electrically connected to the sixth wiring layer via a via; as well as An uppermost eighth wiring layer is provided separately from the first wiring layer, the third wiring layer, the fifth wiring layer, and the sixth wiring layer, and is electrically connected to the seventh wiring layer through a via.

11. The semiconductor device according to claim 10, wherein The device further includes a second control terminal electrically connected to the eighth wiring layer.

12. The semiconductor device according to claim 10, wherein: The fourth wiring layer and the seventh wiring layer face each other with the insulating layer interposed therebetween.

13. The semiconductor device according to claim 12, wherein: The via connecting the seventh wiring layer and the eighth wiring layer passes through a through-hole provided in the fourth wiring layer.

14. The semiconductor device according to claim 1 or 2, wherein: The printed circuit board is provided with: a first opening portion surrounding the first semiconductor chip; and A second opening portion surrounds the second semiconductor chip.

15. The semiconductor device according to claim 1 or 2, wherein: The invention also includes an insulating circuit substrate, the insulating circuit substrate including an insulating substrate, a first circuit board and a second circuit board which are separately provided on the upper surface side of the insulating substrate, and a heat sink provided on the lower surface side of the insulating substrate. The first semiconductor chip is disposed on the first circuit board. The second semiconductor chip is disposed on the second circuit board.

16. The semiconductor device according to claim 1 or 2, wherein: The multi-layer wiring layer further includes a third wiring layer as a lowermost layer, the third wiring layer is provided separately from the second wiring layer, and the third wiring layer is electrically connected to the second main electrode of the first semiconductor chip. A portion of the upper surface of each of the second wiring layer and the third wiring layer is exposed from the insulating layer, The first semiconductor chip is disposed on the exposed upper surface of the third wiring layer, The second semiconductor chip is disposed on the exposed upper surface of the second wiring layer.

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