Phase-locked loop circuit, locking detection circuit and method

Abstract

The invention provides a phase-locked loop circuit, a locking detection circuit and a locking detection method, which are used for detecting whether a phase difference between a reference clock signal and a feedback clock signal input into a phase frequency detector in the phase-locked loop circuit is smaller than a preset time window or not and detecting whether a control voltage in the phase-locked loop circuit is within a preset voltage range or not. When the phase difference is smaller than a preset threshold value and the control voltage is within a preset voltage range, performing an operation of adding 1 to a count value when the rising edge of the reference clock signal comes, outputting a second flag bit to indicate phase loop locking when the count value is larger than a set value, and outputting a second flag bit to indicate phase loop locking when the phase difference is not smaller than the preset threshold value and / or the control voltage is not within the preset voltage range. And the count value is reset and a first flag bit is output to indicate phase ring lock loss. The system is simple and easy to operate, can work in combination with a state machine, and avoids the problem of loop lock loss caused by temperature and voltage changes.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loop lock detection technology, and in particular to a phase-locked loop circuit, a lock detection circuit and a method. Background Art

[0002] For the phase-locked loop, when the output frequency fout of the voltage-controlled oscillator operates at the set target frequency, the feedback clock and the reference clock are equal in frequency after being divided by the N-bit divider, and the phases are aligned. Therefore, the up current and down current of the input charge pump are turned on and off together, and the loop filter is neither charged nor discharged. Therefore, the control voltage of the filter output remains unchanged. At this time, the phase-locked loop has been locked. Therefore, it is possible to determine whether the phase-locked loop is locked by monitoring whether the control voltage is a DC level. In actual applications, when the ambient temperature ( Figure 1 T) or power supply voltage ( Figure 1 When the V in the voltage controlled oscillator changes, the inductance and capacitance of the voltage controlled oscillator will also change slightly, which will cause the attached Figure 1 The control voltage-output frequency curve moves up or down as a whole. Because the set target frequency has not changed, the locked control voltage Vctrl voltage will change from V1 to V2 or V3. Such a control voltage Vctrl is very unfavorable for the charge pump. The current tube in the charge pump has entered the linear region, the current is seriously mismatched, and even the current mirror cannot work normally, resulting in loop unlocking. For application scenarios with small voltage-controlled oscillator gain, the above situation will be more serious.

[0003] In the prior art, the voltage value of the control voltage Vctrl is tested to determine whether the loop is locked. Vctrl needs to be pulled out of the chip and then tested for voltage, which takes up a valuable input / output port. In addition, each time the target locking frequency is switched, this test method needs to be used to determine whether the loop is locked. The traditional method does not monitor the Vctrl voltage value in real time during use, so Vctrl may change to an unfavorable voltage value due to changes in temperature or power supply voltage, causing the phase-locked loop to lose lock. Summary of the invention

[0004] Based on the above problems, the present invention provides a phase-locked loop circuit, a lock detection circuit and a method, which only solve the technical problems of low reliability in detecting the lock of the phase-locked loop in the prior art.

[0005] A lock detection circuit for a phase-locked loop circuit, comprising:

[0006] A phase difference detection module, used to detect whether the phase difference between the reference clock signal input to the phase frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and obtain a first detection result;

[0007] A voltage detection module, used to detect whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range, and obtain a second detection result;

[0008] The arbitration module is connected to the phase difference detection module and the voltage detection module respectively, and is used to: generate an accumulation control signal when the first detection result is that the phase difference is less than the predetermined time window, and the second detection result is that the control voltage is within the predetermined voltage range; generate a clearing control signal when the first detection result is that the phase difference is not less than the predetermined time window and / or the second detection result is that the control voltage is not within the predetermined voltage range;

[0009] The counter module, connected to the decision module, is used to:

[0010] When receiving a reset control signal, a count value reset operation is performed and a first flag bit is output;

[0011] After receiving the accumulation control signal, the count value is incremented by 1 when the reference clock signal rises; and the second flag is output when the count value is greater than the set value.

[0012] Furthermore, the phase difference detection module includes:

[0013] A NOR gate, wherein two input terminals of the NOR gate receive the first output signal and the second output signal of the frequency and phase detector respectively;

[0014] A first trigger, wherein a D input terminal of the first trigger is connected to an output terminal of the NOR gate;

[0015] A first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the NOR gate;

[0016] A second trigger, a D input terminal of the second trigger inputs a high level, and a clock input terminal of the second trigger is connected to an output terminal of the first inverter;

[0017] A delay line, wherein an input end of the delay line is connected to a Q output end of the second flip-flop, an output end of the delay line is connected to a reset end of the second flip-flop, and a size of the predetermined time window is determined by the delay line;

[0018] A second inverter, an input end of the second inverter being connected to a Q output end of the second trigger;

[0019] A clock input terminal of the first trigger is connected to an output terminal of the second inverter;

[0020] The Q output terminal of the first trigger is used as the output terminal of the phase difference detection module to output the first detection result to the decision module.

[0021] Furthermore, the voltage detection module includes:

[0022] A first comparator, wherein a first reference voltage is input to a positive input terminal of the first comparator, and a control voltage is input to a negative input terminal of the first comparator;

[0023] a second comparator, wherein the control voltage is input to a positive input terminal of the second comparator, and a second reference voltage is input to a negative input terminal of the second comparator;

[0024] A first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the first comparator, and a second input terminal of the first AND gate is connected to an output terminal of the second comparator;

[0025] The output end of the first AND gate serves as the output end of the voltage detection module, and outputs the second detection result to the decision module;

[0026] The first reference voltage is greater than the second reference voltage.

[0027] Further, the decision module is a second AND gate;

[0028] A first input end of the second AND gate is connected to the output end of the phase difference detection module, and a second input end of the second AND gate is connected to the output end of the voltage detection module;

[0029] The output end of the second AND gate is connected to the counter module as the output end of the decision module.

[0030] Furthermore, the delay line is a 2-bit programmable delay line.

[0031] A phase-locked loop circuit, comprising:

[0032] A lock detection circuit for a phase-locked loop circuit as described above;

[0033] A frequency detector and a phase detector, for generating a first output signal and a second output signal according to a reference clock signal and a feedback clock signal;

[0034] A charge pump, the input end of which is connected to the output end of the frequency and phase detector, and is used to generate a control voltage according to the first output signal and the second output signal;

[0035] A loop filter, the input end of which is connected to the output end of the charge pump, and is used for filtering the control voltage generated by the charge pump;

[0036] A voltage controlled oscillator, an input end of which is connected to an output end of the loop filter, for generating an output frequency according to a filtered control voltage;

[0037] A frequency division module, the input end of which is connected to the output end of the voltage controlled oscillator, and the output end of the frequency division module is connected to the feedback input end of the frequency detector and phase detector, for dividing the output frequency to generate a feedback clock signal to the frequency detector and phase detector;

[0038] The input end of the phase difference detection module in the lock detection circuit is connected to the output end of the frequency and phase detector;

[0039] The input end of the voltage detection module in the lock detection circuit is connected to the output end of the loop filter.

[0040] Furthermore, the frequency division module includes:

[0041] An N-bit frequency divider, used for dividing the output frequency to obtain a feedback clock signal;

[0042] A Sigma-delta modulator, wherein the input end of the Sigma-delta modulator is connected to the output end of the N-bit frequency divider, and the output end of the Sigma-delta modulator is connected to the N-bit frequency divider, for performing signal modulation during frequency division processing of the N-bit frequency divider.

[0043] A lock detection method for a phase-locked loop circuit, using the aforementioned lock detection circuit for a phase-locked loop circuit, comprising:

[0044] Step A1, detecting whether the phase difference between the reference clock signal input to the phase frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and detecting whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range:

[0045] When the phase difference is not less than the predetermined time window and / or the control voltage is not within the predetermined voltage range, executing step A2;

[0046] When the phase difference is less than the predetermined time window and the control voltage is within the predetermined voltage range, executing step A3;

[0047] Step A2, performing a count value clearing operation and outputting a first flag bit;

[0048] Step A3, when the reference clock signal rises, the count value is incremented by 1, and then step A4 is performed:

[0049] Step A4, determine whether the count value is greater than a preset value:

[0050] If yes, go to step A5;

[0051] If not, return to step A1;

[0052] Step A5, output the second flag bit.

[0053] The beneficial technical effect of the present invention is that by setting up a lock detection circuit, the phase difference between the reference clock signal and the feedback clock signal is detected for a long period, and the control voltage Vctrl is detected in real time, and the final detection result is output in the form of a flag bit. It is concise, clear and easy to operate, and can work in conjunction with a state machine to avoid loop loss of lock due to temperature and voltage changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A diagram showing the relationship between the output frequency and the control voltage in a voltage controlled oscillator in the prior art;

[0055] Figure 2 It is a module schematic diagram of the lock detection circuit of the present invention;

[0056] Figure 3 is a circuit structure diagram of a lock detection circuit of the present invention;

[0057] Figure 4 is a circuit timing diagram of the lock detection circuit of the present invention;

[0058] Figure 5 is a circuit structure diagram of a phase-locked loop circuit of the present invention;

[0059] Figure 6 The present invention is a flowchart of the steps of a lock detection method for a phase-locked loop circuit. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0062] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0063] refer to Figure 2 The present invention provides a lock detection circuit for a phase-locked loop circuit, comprising:

[0064] A phase difference detection module (11) is used to detect whether the phase difference between a reference clock signal input to a phase frequency detector and a feedback clock signal in a phase-locked loop circuit is less than a predetermined time window, and obtain a first detection result;

[0065] A voltage detection module (12) is used to detect whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range, and obtain a second detection result;

[0066] The decision module (13) is connected to the phase difference detection module (11) and the voltage detection module (12) respectively, and is used to: generate an accumulation control signal when the first detection result is that the phase difference is less than the predetermined time window, and the second detection result is that the control voltage is within the predetermined voltage range; and generate a clearing control signal when the first detection result is that the phase difference is not less than the predetermined time window and / or the second detection result is that the control voltage is not within the predetermined voltage range;

[0067] The counter module (14) is connected to the decision module (13) and is used for:

[0068] When receiving a reset control signal, a count value reset operation is performed and a first flag bit is output;

[0069] After receiving the accumulation control signal, the count value is incremented by 1 when the reference clock signal rises; and the second flag is output when the count value is greater than the set value.

[0070] Through the time window combined with the counter, the phase-locked loop is locked and detected. It is only necessary to determine whether the loop is locked through the output flag. Ensure that the control voltage Vctrl voltage value is within a reasonable range when the phase-locked loop is locked. If the control voltage Vctrl voltage is not within a reasonable range after locking, the lock output first flag is 0, and the state machine re-triggers the automatic frequency calibration process of the voltage-controlled oscillator and re-selects the appropriate programmable capacitor to ensure that the control voltage Vctrl voltage value is in the appropriate position, thereby improving the reliability of the phase-locked loop in practical applications. The specific second flag is 1, indicating that the phase-locked loop is locked.

[0071] By setting up a lock detection circuit, the phase difference between the reference clock signal and the feedback clock signal is detected for a long period, and the control voltage Vctrl is detected in real time, and the final detection result is output in the form of a flag bit. It is concise and easy to operate, and can work in conjunction with the state machine to avoid loop loss of lock due to temperature and voltage changes.

[0072] refer to Figure 3 , further, the phase difference detection module (11) comprises:

[0073] A NOR gate (NOR), wherein two input ends of the NOR gate (NOR) respectively receive a first output signal and a second output signal of the frequency and phase detector;

[0074] A first trigger (D1), wherein a D input terminal of the first trigger (D1) is connected to an output terminal of the NOR gate;

[0075] A first inverter (INV1), wherein an input terminal of the first inverter (INV1) is connected to an output terminal of the NOR gate;

[0076] A second trigger (D2), a D input terminal of the second trigger (D2) inputting a high level, and a clock input terminal of the second trigger (D2) connected to an output terminal of the first inverter (INV1);

[0077] A delay line (delay), wherein an input end of the delay line (delay) is connected to a Q output end of the second flip-flop (D2), an output end of the delay line (delay) is connected to a reset end of the second flip-flop (D2), and a size of the predetermined time window is determined by the delay line (delay);

[0078] A second inverter (INV2), wherein an input end of the second inverter (INV2) is connected to a Q output end of the second flip-flop (D2);

[0079] A clock input terminal of the first trigger (D1) is connected to an output terminal of the second inverter (INV2);

[0080] The Q output end of the first trigger (D1) serves as the output end of the phase difference detection module (11), and outputs the first detection result to the decision module (13).

[0081] The inverse signal of the phase difference between the reference clock signal fref and the feedback clock signal ffb can be obtained at point A through the NOR gate. The pulse width includes the narrow pulse generated to overcome the "dead zone" problem of the frequency and phase detector.

[0082] Specifically, the first output signal of the phase frequency detector is an up signal, and the second output signal is a down signal.

[0083] If the up signal and the down signal have one high and one low output level, the NOR gate outputs a low level, that is, point A is 0. When point B rises, the Q output terminal point C of the first trigger D1 outputs a low level, that is, the logic level is 0, indicating that there is a phase difference between the reference clock signal and the feedback clock signal.

[0084] If the Q output terminal C of the first flip-flop D1 outputs a high level, that is, a logic level of 1, it indicates that there is no phase difference between the reference clock signal and the feedback clock signal.

[0085] Furthermore, the voltage detection module (12) comprises:

[0086] A first comparator (COM1), wherein a first reference voltage Vref1 is input to a positive input terminal of the first comparator (COM1), and a control voltage Vctrl is input to a negative input terminal of the first comparator (COM1);

[0087] a second comparator (COM2), wherein the control voltage Vctrl is input to a positive input terminal of the second comparator (COM2), and the second reference voltage Vref2 is input to a negative input terminal of the second comparator (COM2);

[0088] A first AND gate (AND1), wherein a first input end of the first AND gate (AND1) is connected to an output end of the first comparator (COM1), and a second input end of the first AND gate (AND1) is connected to an output end of the second comparator (COM2);

[0089] The output end of the first AND gate (AND1) serves as the output end of the voltage detection module (12), and outputs the second detection result to the decision module (13);

[0090] The first reference voltage is greater than the second reference voltage.

[0091] If the control voltage is between the first reference voltage and the second reference voltage, the first AND gate outputs a high level, indicating that the control voltage is within a predetermined voltage range formed by the first reference voltage and the second reference voltage.

[0092] Furthermore, the decision module (13) is a second AND gate (AND2);

[0093] A first input end of the second AND gate (AND2) is connected to an output end of the phase difference detection module (11), and a second input end of the second AND gate (AND2) is connected to an output end of the voltage detection module (12);

[0094] The output end of the second AND gate (AND2) is connected to the counter module (14) as the output end of the decision module (13).

[0095] Furthermore, the delay line (delay) is a 2-bit programmable delay line.

[0096] Specifically, the delay line (delay) is a 2-bit programmable delay line, that is, the predetermined time window of the present invention is also programmable, which is controlled by a 2-bit binary number Delay_ctrl<1:0>, and the predetermined time window can be 1ns, 2ns, 4ns, and 8ns respectively.

[0097] Specifically, the counter module of the present invention can be a programmable counter (Counter), Counter_bit<13:0>, that is, a 14-bit wide counter. When the programmable counter Counter_bit<13:0> is all 1 and the time window is 1ns, for a 32MHz reference clock signal, the minimum identifiable frequency difference is 62.5Hz, and for a voltage-controlled oscillator operating at 4.8GHz, the minimum identifiable frequency difference (frequency resolution) is 9.375KHz.

[0098] Combined schematic diagram Figure 3 and timing diagram Figure 4 , the detection principle of the lock detection circuit of the present invention is as follows:

[0099] If the lock flag bit is to be 1, that is, the second flag bit needs to meet 3 conditions simultaneously. Condition 1: The phase difference between the two input signals of the frequency discriminator and phase detector needs to be less than a set time window, that is, a predetermined time window. Condition 2: The control voltage Vctrl needs to fall within a suitable range, that is, it is necessary to satisfy Vref2 < Vctrl < Vref1. When the previous conditions are met simultaneously, a 14-bit programmable counter is started. Whenever the rising edge of the reference clock signal fref arrives, the counter is incremented by 1 until the count value is greater than the written set value, and the lock flag bit output is 1, that is, the first flag bit is output. If during the accumulation of the counter, either Condition 1 or Condition 2 is not met, the counter will be cleared and the counting will stop until both Condition 1 and Condition 2 are met, and the counter will start counting again.

[0100] By performing a NOR operation on the two output signals, the up signal and the down signal, of the phase frequency detector, an inverted signal of the phase difference between the input reference clock signal fref and the feedback clock signal ffb can be obtained at point A in the figure. This pulse width includes the narrow pulse generated to overcome the "dead zone" problem of the phase frequency detector. The signal at point A will be input to the D terminal of the first flip-flop D1. The inverted signal Ab of the signal at point A after being inverted by the first inverter will be used as the clock input (Clk input) of the second flip-flop D2. The input signal at the D input terminal of the second flip-flop D2 is constantly 1 (the logic level is 1, that is, always high level). The output signal at the Q output terminal will reset the second flip-flop after passing through a 2-bit programmable delay line. This delay line determines the size of the predetermined time window. Therefore, if the phase difference pulse is less than the predetermined time window and is inverted by the second inverter, when the rising edge of the clock at point B arrives, the phase difference inverted signal has passed through the phase difference pulse signal and becomes 1. So the output at point C is 1, that is, the phase difference pulse falls within the predetermined time window. Conversely, if the phase difference pulse is greater than the time window, then the output at point C will be 0. It should be noted that the path delays of the signals at points A and B are different. The delay at point B is much greater than that at point A. The additional delay at point B compared to point A is 2*Tinv + Tdff + Trst, where Tinv represents the delay of one inverter stage, Tdff is the path delay from the second flip-flop D2 to the Q output terminal, and Trst is the path delay from the reset terminal reset of the second flip-flop to the Q output terminal. And the additional delay at point B is close to the narrow pulse time to overcome the "dead zone". Therefore, considering the above non-ideal factors, the predetermined time window generated by the delay line can be approximately directly compared with the phase difference. When the control voltage Vctrl satisfies Vref2 < Vctrl < Vref1, the output at point D is 1; otherwise, the output at point D is 0. When both C and D are 1, the output at point E is 1 and is used as the input of the programmable counter to trigger the counter module to count. If the output at point E is 0, the trigger counter is cleared. This counter module is generated by digital synthesis. In addition to point E, the input terminals also include the input reference clock signal fref and the 14-bit count control word Counter_bit<13:0>. Point F is the corresponding flag bit of the output.

[0101] Reference Figure 4 , from top to bottom are Figure 4The waveforms of the up, down, A, Ab, B, Bb, C, D, E, and F nodes are ideal waveforms without considering the path delay. The reference clock is 32MHz, and the corresponding period T1 is 31.25ns. The reference clock signal fref and the feedback clock signal ffb are set to be of the same frequency and phase, Vref1=0.9V, Vref2=0.3V, and Vctrl always falls between the two. If the D node is 1, then after the set Counter_bit<13:0> reference cycles, the F node pulls up and outputs the second flag bit 1, indicating that the loop is locked. Now let the phase of the reference clock signal fref (ffb has a similar effect) suddenly advance in the Tnth cycle, and the phase difference between fref and ffb is Terror. The pulse width corresponding to Terror is greater than the pulse width corresponding to the predetermined time window. Therefore, in the Tnth cycle, the sampling result of point B to point A is 0, and the C node is 0, so the E node is 0, the counter is cleared, and the F node is 0, indicating that the loop is unlocked. At any time, if Vctrl falls outside Vref1 and Vref2, point D becomes 0, point E also becomes 0, and the counter is cleared. After Tn cycles, the reference clock signal fref is restored to the same frequency and phase as ffb. It still takes the set Counter_bit<13:0> reference cycles before the F node is pulled high and the loop is locked. It is worth noting that in this process, it is necessary to ensure that the phase difference between fref and ffb is always less than the predetermined time window, and Vctrl always falls within Vref1 and Vref2.

[0102] In practical applications, the flag bit output at point F can be used to indicate the working status of the phase-locked loop. If the loop is unlocked, the system state machine can use this flag bit as the first flag bit and restart the automatic frequency calibration process to relock the loop.

[0103] refer to Figure 5 The present invention also provides a phase-locked loop circuit, comprising:

[0104] A lock detection circuit (1) for a phase-locked loop circuit as described above;

[0105] A frequency detector and a phase detector (2), used for generating a first output signal and a second output signal according to a reference clock signal and a feedback clock signal;

[0106] A charge pump (3), the input end of which is connected to the output end of the frequency and phase detector (2), and is used to generate a control voltage according to the first output signal and the second output signal;

[0107] A loop filter (4), the input end of which is connected to the output end of the charge pump (3), and is used to filter the control voltage generated by the charge pump;

[0108] A voltage controlled oscillator (5), the input end of which is connected to the output end of the loop filter (4), and is used to generate an output frequency according to the filtered control voltage;

[0109] A frequency division module (6), the input end of which is connected to the output end of the voltage-controlled oscillator (5), and the output end of which is connected to the feedback input end of the frequency detector (2), for performing frequency division processing on the output frequency to generate a feedback clock signal to the frequency detector (2);

[0110] The input end of the phase difference detection module (11) in the lock detection circuit (1) is connected to the output end of the frequency and phase detector (2);

[0111] The input end of the voltage detection module (12) in the lock detection circuit (1) is connected to the output end of the loop filter (4).

[0112] Furthermore, the frequency division module (6) comprises:

[0113] An N-bit frequency divider (61), used for dividing the output frequency to obtain a feedback clock signal;

[0114] A Sigma-delta modulator (62) is provided, wherein the input end of the Sigma-delta modulator is connected to the output end of the N-bit frequency divider, and the output end of the Sigma-delta modulator is connected to the N-bit frequency divider, and is used for performing signal modulation during frequency division processing of the N-bit frequency divider.

[0115] refer to Figure 6 The present invention also provides a lock detection method for a phase-locked loop circuit, using a lock detection circuit for a phase-locked loop circuit as described above, characterized in that it includes:

[0116] Step A1, detecting whether the phase difference between the reference clock signal input to the phase frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and detecting whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range:

[0117] When the phase difference is not less than the predetermined time window and / or the control voltage is not within the predetermined voltage range, executing step A2;

[0118] When the phase difference is less than the predetermined time window and the control voltage is within the predetermined voltage range, executing step A3;

[0119] Step A2, performing a count value clearing operation and outputting a first flag bit;

[0120] Step A3, when the reference clock signal rises, the count value is incremented by 1, and then step A4 is performed:

[0121] Step A4, determine whether the count value is greater than a preset value:

[0122] If yes, go to step A5;

[0123] If not, return to step A1;

[0124] Step A5, output the second flag bit.

[0125] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A lock detection circuit for a phase-locked loop circuit, characterized in that: include: A phase difference detection module, used to detect whether the phase difference between the reference clock signal input to the phase frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and obtain a first detection result; A voltage detection module, used to detect whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range, and obtain a second detection result; a decision module, connected to the phase difference detection module and the voltage detection module respectively, and configured to: generate an accumulated control signal when the first detection result is that the phase difference is less than the predetermined time window, and the second detection result is that the control voltage is within the predetermined voltage range; When the first detection result is that the phase difference is not less than the predetermined time window and / or the second detection result is that the control voltage is not within the predetermined voltage range, generating a clear control signal; A counter module, connected to the decision module, is used to: When receiving the clear control signal, performing a count value clear operation and outputting a first flag bit; After receiving the accumulation control signal, the count value is incremented by 1 when the rising edge of the reference clock signal comes; and a second flag is output when the count value is greater than a set value.

2. A lock detection circuit for a phase-locked loop circuit as claimed in claim 1, characterized in that: The phase difference detection module comprises: A NOR gate, wherein two input terminals of the NOR gate receive the first output signal and the second output signal of the frequency and phase detector respectively; A first trigger, wherein a D input terminal of the first trigger is connected to an output terminal of the NOR gate; A first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the NOR gate; A second trigger, a D input terminal of the second trigger inputting a high level, and a clock input terminal of the second trigger connected to an output terminal of the first inverter; A delay line, wherein an input end of the delay line is connected to a Q output end of the second flip-flop, an output end of the delay line is connected to a reset end of the second flip-flop, and a size of the predetermined time window is determined by the delay line; A second inverter, an input end of the second inverter being connected to a Q output end of the second trigger; A clock input terminal of the first trigger is connected to an output terminal of the second inverter; The Q output terminal of the first trigger serves as the output terminal of the phase difference detection module, and outputs the first detection result to the decision module.

3. A lock detection circuit for a phase-locked loop circuit as claimed in claim 1, characterized in that: The voltage detection module comprises: A first comparator, wherein a first reference voltage is input to a positive input terminal of the first comparator, and the control voltage is input to a negative input terminal of the first comparator; a second comparator, wherein the control voltage is input to a positive input terminal of the second comparator, and a second reference voltage is input to a negative input terminal of the second comparator; a first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the first comparator, and a second input terminal of the first AND gate is connected to an output terminal of the second comparator; The output end of the first AND gate serves as the output end of the voltage detection module, and outputs the second detection result to the decision module; Wherein, the first reference voltage is greater than the second reference voltage.

4. A lock detection circuit for a phase-locked loop circuit as claimed in claim 1, characterized in that: The decision module is a second AND gate; The first input end of the second AND gate is connected to the output end of the phase difference detection module, and the second input end of the second AND gate is connected to the output end of the voltage detection module; The output end of the second AND gate is connected to the counter module as the output end of the decision module.

5. A lock detection circuit for a phase-locked loop circuit as claimed in claim 2, characterized in that: The delay line is a 2-bit programmable delay line.

6. A phase-locked loop circuit, characterized in that: include: A lock detection circuit for a phase-locked loop circuit as claimed in any one of claims 1 to 5; A frequency detector and a phase detector, for generating a first output signal and a second output signal according to a reference clock signal and a feedback clock signal; A charge pump, whose input end is connected to the output end of the frequency and phase detector, and is used to generate a control voltage according to the first output signal and the second output signal; A loop filter, the input end of which is connected to the output end of the charge pump, and is used to filter the control voltage generated by the charge pump; A voltage controlled oscillator, whose input end is connected to the output end of the loop filter and is used to generate an output frequency according to the filtered control voltage; A frequency division module, whose input end is connected to the output end of the voltage controlled oscillator, whose output end is connected to the feedback input end of the frequency detector, and is used to perform frequency division processing on the output frequency to generate the feedback clock signal to the frequency detector; The input end of the phase difference detection module in the lock detection circuit is connected to the output end of the frequency and phase detector; The input end of the voltage detection module in the lock detection circuit is connected to the output end of the loop filter.

7. A phase-locked loop circuit as claimed in claim 6, characterized in that: The frequency division module comprises: An N-bit frequency divider, used for dividing the output frequency to obtain the feedback clock signal; A Sigma-delta modulator, wherein the input end of the Sigma-delta modulator is connected to the output end of the N-bit frequency divider, and the output end of the Sigma-delta modulator is connected to the N-bit frequency divider, for performing signal modulation during frequency division processing of the N-bit frequency divider.

8. A lock detection method for a phase-locked loop circuit, characterized in that: A lock detection circuit for a phase-locked loop circuit according to any one of claims 1 to 5, characterized in that it comprises: Step A1, detecting whether the phase difference between the reference clock signal input to the phase frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and detecting whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range: When the phase difference is not less than the predetermined time window and / or the control voltage is not within the predetermined voltage range, executing step A2; When the phase difference is smaller than the predetermined time window and the control voltage is within the predetermined voltage range, executing step A3; Step A2, performing a count value clearing operation and outputting a first flag bit; Step A3, when the rising edge of the reference clock signal comes, the count value is incremented by 1, and then step A4 is performed: Step A4, determining whether the count value is greater than a preset value: If yes, go to step A5; If not, return to step A1; Step A5, output the second flag bit.

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