Master-slave frequency synchronization device and method for 5G indoor distribution wireless frequency shift

Abstract

The invention relates to a master-slave frequency synchronization device and method for 5G indoor distribution wireless frequency shift, belongs to the technical field of communication, and solves the problem that frequency offset is generated when the frequency of a master is converted to intermediate frequency and the frequency of a slave is recovered to the intermediate frequency when the frequencies of the master and the slave are different. The device comprises a host and a plurality of slaves, and each comprises a receiving module for receiving a base station signal or a Bluetooth signal; the demodulation module demodulates the base station signal or the Bluetooth signal and extracts a timing pulse of a preset time based on the demodulated base station signal or the Bluetooth signal; the FPGA performs frequency multiplication on the timing pulse of the preset time to obtain a given timing pulse T0, adjusts the duty ratio of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and outputs the adjusted square wave level; the RC integrating circuit is used for integrating the adjusted square wave level to generate an adjusting voltage; the voltage-controlled temperature-compensated oscillator oscillates according to the adjustment voltage to generate an output frequency, and generates a feedback clock frequency based on the output frequency. And the master and slave machines are calibrated and aligned to the base station.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a master-slave frequency synchronization device and method for 5G indoor wireless frequency shifting. Background Art

[0002] 5G is the fifth generation of mobile communication technology, which has the advantages of lower latency, larger capacity and faster speed. 2019 is the first year of 5G commercialization. In the following years, 5G networks have been laid out on a large scale and the number of users has also increased significantly. However, 5G signals have high frequencies and large spatial attenuation. As a result, there are some shops and office buildings with strong outdoor signals but weak indoor 5G signal coverage. Traditional wired indoor distribution solutions have problems such as high wiring construction costs and difficulty in property coordination.

[0003] The existing 5G communication room distribution scheme of wireless frequency shift cascade of master and slave machines, both the master and slave machines adopt different frequency transceiver. The host has two RF interfaces, one of which is the input of the downlink signal of the 5G base station and the output of the uplink signal, and the other interface is the downlink output of the intermediate frequency signal of the host after frequency shift and the uplink input of the intermediate frequency signal of the slave. The slave adopts a symmetrical frequency shift scheme, one interface is the transmission of the downlink signal of the 5G base station and the input of the uplink signal of the user, and the other interface is the downlink input of the intermediate frequency signal of the host after frequency shift and the uplink output of the intermediate frequency signal of the slave. In the system composed of master and slave machines, the host frequency-converts the 5G frequency to the intermediate frequency and transmits it wirelessly to the slave machine. The slave machine converts the received intermediate frequency back to the 5G frequency to cover the signal-free area. Advantage 1 of this scheme: Both the host and the slave machine are different frequency transceivers, and bandpass filters of different frequencies are used before and after the frequency conversion to increase the transceiver isolation of the single board, which is convenient for antenna installation, and built-in antennas can also be used. Advantage 2: No feeder is required to connect the master and slave machines, reducing the amount of engineering construction.

[0004] A key issue in the above-mentioned 5G communication room distribution scheme is that the frequencies of the master and slave machines need to be from the same source. If they are not from the same source, the master machine will convert the frequency to the intermediate frequency, and a frequency deviation will occur when the slave machine restores the intermediate frequency signal. If this frequency deviation is not calibrated, it cannot meet the basic requirements of 5G communication and affects the signal transmission quality. Summary of the invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a master-slave frequency synchronization device and method for 5G indoor wireless frequency shifting, so as to solve the problem that when the frequencies of the master and slave machines are different, the host machine changes the frequency to the intermediate frequency, and the slave machine will produce frequency deviation when restoring the intermediate frequency signal, thereby failing to meet the basic requirements of 5G communication and affecting the signal transmission quality.

[0006] On the one hand, an embodiment of the present invention provides a master-slave frequency synchronization device for 5G indoor wireless frequency shifting, including a host and multiple slaves, wherein the host and the slaves both include: a receiving module, used to receive a base station signal or a Bluetooth signal; a demodulation module, used to demodulate the base station signal or the Bluetooth signal, and extract a timing pulse of a predetermined time based on the demodulated base station signal or the Bluetooth signal; an FPGA, used to multiply the timing pulse of the predetermined time to obtain a given timing pulse T0, adjust the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and output the adjusted square wave level; an RC integrator circuit, used to integrate the adjusted square wave level to generate an adjustment voltage; and a voltage-controlled temperature-compensated oscillator, used to oscillate according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

[0007] The beneficial effects of the above technical solution are as follows: the embodiment of the present invention adopts Bluetooth networking to realize a frequency calibration architecture with one master and multiple slaves; the anti-interference problem in the wireless communication process is realized through the application of Bluetooth protocol; the host of the present invention adopts 5G_modem to calibrate and align to the base station, and the slave adopts Bluetooth module to calibrate and align to the base station, which solves the frequency offset problem existing in the frequency conversion system and realizes low cost.

[0008] Based on the further improvement of the above device, the FPGA includes a theoretical rising edge acquisition module, a calibration rising edge acquisition module, a comparison module and an adjustment module. The theoretical rising edge acquisition module is used to obtain the theoretical rising edge number N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0; the calibration rising edge acquisition module is used to calibrate the frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB The comparison module is used to compare the difference between the theoretical number of rising edges and the calibrated number of rising edges with the target number of rising edges N offset performing comparison; and the adjusting module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level.

[0009] Based on the further improvement of the above device, the adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level, including: when the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FBWhen the difference in rising edges is greater than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is reduced; when the comparison result is that the difference in rising edges is greater than the target number of rising edges N offset And the number of rising edges after calibration N FB When the comparison result is that the rising edge difference is less than or equal to the target rising edge number N0, the duty cycle X of the square wave level of the FPGA is increased; and when the comparison result is that the rising edge difference is less than or equal to the target rising edge number N offset , the duty cycle X of the square wave level of the FPGA remains unchanged.

[0010] Based on further improvements of the above-mentioned device, the host and the slave also include a two-power divider and a frequency conversion system, which are used to power-divide the output frequency of the voltage-controlled temperature-compensated oscillator to generate a feedback clock frequency and a calibrated reference clock frequency, wherein, when the demodulation module is a 5G modem arranged on the host, the frequency conversion system on the host is connected to one output end of the two-power divider on the host to receive the calibrated reference clock frequency of the host, and the other output end of the two-power divider on the host is used to output the feedback clock frequency to the FPGA on the host; or when the demodulation module is a Bluetooth module arranged on the slave, wherein the frequency conversion system on the slave is connected to one output end of the two-power divider on the slave to receive the calibrated reference clock frequency of the slave, and the other output end of the two-power divider on the slave is used to output the feedback clock frequency to the FPGA on the slave.

[0011] Based on further improvement of the above-mentioned device, the host also includes a host oscillator, and the slave also includes a slave oscillator, wherein the host oscillator oscillates based on the calibrated reference clock frequency of the host to generate a host local oscillator clock frequency synchronized with the base station clock frequency; the slave oscillator oscillates based on the calibrated reference clock frequency of the slave to generate a slave local oscillator clock frequency synchronized with the host local oscillator clock frequency.

[0012] Based on the further improvement of the above-mentioned device, the 5G modem is used to demodulate the base station signal from the 5G base station, and extract a 5ms timing pulse from the demodulated base station signal as the timing pulse of the predetermined time; the FPGA of the host is used to use the 5ms timing pulse as an interrupt instruction to trigger an interrupt, and then send the interrupt instruction to the Bluetooth module on the host, and control the Bluetooth module on the host to transmit a Bluetooth signal based on the interrupt instruction; the Bluetooth module on the slave establishes a connection with the Bluetooth module on the host, and waits for the Bluetooth signal transmitted by the host. When the Bluetooth module on the slave detects the Bluetooth signal, the Bluetooth module on the slave decodes the Bluetooth signal and then passes it to the FPGA on the slave; and the FPGA on the slave is used to count the time window of the Bluetooth module broadcasting information to obtain a 5ms timing pulse as the timing pulse of the predetermined time.

[0013] Based on further improvement of the above device, the RC integration circuit includes a resistor and a capacitor, wherein one end of the resistor is connected to the output end of the FPGA as the input end of the RC integration circuit, and the other end is connected to one end of the capacitor and serves as the output end of the RC integration circuit; the other end of the capacitor is grounded.

[0014] On the other hand, an embodiment of the present invention provides a master-slave frequency synchronization method for 5G indoor wireless frequency shifting, including: receiving a base station signal or a Bluetooth signal; demodulating the base station signal or the Bluetooth signal, and extracting a timing pulse of a predetermined time based on the demodulated base station signal or the Bluetooth signal; multiplying the timing pulse of the predetermined time to obtain a given timing pulse T0, adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency and outputting the adjusted square wave level; integrating the adjusted square wave level to generate an adjustment voltage; and oscillating according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

[0015] Based on the further improvement of the above method, adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency and outputting the adjusted square wave level further includes: obtaining the theoretical number of rising edges N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0; calibrating the frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB ; The difference between the theoretical number of rising edges and the calibrated number of rising edges and the target number of rising edges N offsetA comparison is performed, wherein the duty cycle of the square wave level of the FPGA is adjusted according to the comparison result to obtain the adjusted square wave level.

[0016] Based on the further improvement of the above method, adjusting the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level further includes: when the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FB When the difference in rising edges is greater than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is reduced; when the comparison result is that the difference in rising edges is greater than the target number of rising edges N offset And the number of rising edges after calibration N FB When the comparison result is that the rising edge difference is less than or equal to the target rising edge number N0, the duty cycle X of the square wave level of the FPGA is increased; and when the comparison result is that the rising edge difference is less than or equal to the target rising edge number N offset , the duty cycle X of the square wave level of the FPGA remains unchanged.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0018] 1. The embodiment of the present invention adopts Bluetooth networking to realize a frequency calibration architecture with one master and multiple slaves; the anti-interference problem in the wireless communication process is realized by applying the Bluetooth protocol; the host of the present invention adopts 5G_modem to calibrate and align to the base station, and the slave adopts Bluetooth module to calibrate and align to the base station, so as to solve the frequency offset problem existing in the frequency conversion system and realize low cost;

[0019] 2. The present invention uses a 5ms timing pulse to calibrate the local reference clock of the master and slave machines, and can achieve flexible output of the reference clock frequency by changing the VC-TCXO model to adapt to different application scenarios;

[0020] 3. The master and slave use the local reference clock f REF_Z 、f REF_C Generates the local oscillator frequency LO RF_Z , LO IF_Z , LO RF_C With LO IF_C The host and slave modules communicate using a pair of Bluetooth chips. REF_Z 、f REF_CBoth are generated by VC-TCXO (voltage-controlled temperature-compensated oscillator), and FPGA is used to calibrate the VC-TCXO in real time. The host realizes frequency calibration through the 5ms pulse information output by 5G_modem. The host modulates the 5ms pulse information generated by 5G_modem into the Bluetooth signal and sends it to the slave. The slave realizes frequency calibration by demodulating the Bluetooth signal of the host (that is, realizing real-time automatic calibration of the frequency of the host and slave), thereby achieving the purpose of 5G channel homology between the master and slave.

[0021] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0023] Figure 1 A block diagram of a master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to an embodiment of the present invention;

[0024] Figure 2 A system block diagram of a host and a slave according to an embodiment of the present invention;

[0025] Figure 3 A block diagram of host calibration according to an embodiment of the present invention;

[0026] Figure 4 A block diagram of slave calibration according to an embodiment of the present invention;

[0027] Figure 5 is a flow chart of host calibration according to an embodiment of the present invention;

[0028] Figure 6 is a flow chart of slave calibration according to an embodiment of the present invention;

[0029] Figure 7 The present invention is a flowchart of a master-slave frequency synchronization method for 5G indoor wireless frequency shifting according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0031] refer to Figure 1 A specific embodiment of the present invention discloses a master-slave frequency synchronization device for 5G indoor wireless frequency shifting, including a host and multiple slaves, wherein the host and the slaves both include: a receiving module 101, used to receive a base station signal or a Bluetooth signal; a demodulation module 102, used to demodulate the base station signal or the Bluetooth signal, and extract a timing pulse of a predetermined time based on the demodulated base station signal or the Bluetooth signal; an FPGA 103, used to multiply the timing pulse of the predetermined time to obtain a given timing pulse T0, adjust the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and output the adjusted square wave level; an RC integrator circuit 104, used to integrate the adjusted square wave level to generate an adjustment voltage; and a voltage-controlled temperature-compensated oscillator 105, used to oscillate according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

[0032] Compared with the prior art, the master-slave frequency synchronization device for 5G indoor wireless frequency shifting provided in this embodiment adopts Bluetooth networking to realize a frequency calibration architecture with one master and multiple slaves; the anti-interference problem in the wireless communication process is realized by the application of Bluetooth protocol; the host of the present invention adopts 5G_modem to calibrate and align to the base station, and the slave adopts Bluetooth module to calibrate and align to the base station, so as to solve the frequency offset problem existing in the frequency conversion system and realize low cost.

[0033] In the following, reference will be made to Figure 1 , a master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to an embodiment of the present invention is described in detail. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting includes a host and multiple slaves, wherein the host and the slaves both include: a receiving module 101, a demodulation module 102, an FPGA 103, an RC integration circuit 104, a voltage-controlled temperature-compensated oscillator 105, and a two-power divider. Specifically, the receiving module 101 includes a host receiving module and a slave receiving module. The demodulation module 102 includes a host demodulation module (such as a 5G modem) and a slave demodulation module (such as a Bluetooth module). FPGA 103 includes a host FPGA and a slave FPGA. RC integration circuit 104 includes a host RC integration circuit and a slave RC integration circuit. The voltage-controlled temperature-compensated oscillator 105 includes a host voltage-controlled temperature-compensated oscillator and a slave voltage-controlled temperature-compensated oscillator. The two-power divider includes a host two-power divider and a slave two-power divider. In the following, the host and the slave are described in detail respectively.

[0034] The host receiving module (also referred to as the receiving module on the host) is used to receive base station signals. Specifically, the host receiving module receives base station signals from the base station via a receiving antenna.

[0035] The host demodulation module (also called the demodulation module on the host) is used to demodulate the base station signal and extract a timing pulse of a predetermined time based on the demodulated base station signal. The host demodulation module is used to demodulate the base station signal and extract a timing pulse of a first predetermined time based on the demodulated base station signal, such as a timing pulse of 5ms.

[0036] The host FPGA (also called the FPGA on the host) is used to multiply the timing pulse of the predetermined time to obtain a given timing pulse T0, adjust the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and output the adjusted square wave level. The host FPGA includes a theoretical rising edge acquisition module, a calibrated rising edge acquisition module, a comparison module and an adjustment module. The theoretical rising edge acquisition module is used to obtain the theoretical number of rising edges N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0. The calibrated rising edge acquisition module is used to obtain the calibrated frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB The comparison module is used to compare the difference between the theoretical rising edge number and the calibrated rising edge number with the target rising edge number N. offset The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level. The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level, including: when the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration is N FB When the difference in rising edges is greater than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is reduced; when the comparison result is that the difference in rising edges is greater than the target number of rising edges N offset And the number of rising edges after calibration is N FB When the difference in rising edges is less than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is increased; and when the comparison result is that the difference in rising edges is less than or equal to the target number of rising edges N offset When the PWM frequency of the FPGA is adjusted according to the given timing pulse T0, the duty cycle X of the square wave level of the FPGA remains unchanged; wherein, the PWM wave frequency of the FPGA is adjusted according to the given timing pulse T0.

[0037] The host RC integration circuit (also called the RC integration circuit on the host) is used to integrate the adjusted square wave level to generate an adjustment voltage. Specifically, the host RC integration circuit includes a resistor and a capacitor, wherein one end of the resistor is connected to the output end of the FPGA as the input end of the RC integration circuit, and the other end is connected to one end of the capacitor and serves as the output end of the RC integration circuit; the other end of the capacitor is grounded. For example, a 10K resistor in series is connected to a 1uF capacitor to ground. When the input frequency is a PWM wave of 1KHz, the output can be converted into a more stable adjustment voltage. The resistance and capacitance values ​​are determined according to the actual test results.

[0038] The host voltage-controlled temperature-compensated oscillator is used to oscillate according to the adjustment voltage to generate an output frequency, wherein a feedback clock frequency is generated based on the output frequency through the host two-power divider.

[0039] The host two-power divider (also called the two-power divider on the host) is used to divide the output frequency of the host voltage-controlled temperature-compensated oscillator to generate a feedback clock frequency and a calibrated reference clock frequency. Specifically, the frequency conversion system set on the host is connected to one output end of the two-power divider on the host to receive the calibrated reference clock frequency of the host; the other output end of the two-power divider on the host outputs the feedback clock frequency to the host FPGA.

[0040] The host oscillator oscillates based on the calibrated reference clock frequency of the host to generate a host local oscillator clock frequency synchronized with the base station clock frequency.

[0041] The host FPGA is used to use the 5ms timing pulse as an interrupt instruction to trigger an interrupt, and then send the interrupt instruction to the Bluetooth module on the host, and control the Bluetooth module on the host to transmit a Bluetooth signal based on the interrupt instruction.

[0042] After the slave Bluetooth module (also called the Bluetooth module on the slave) establishes a connection with the Bluetooth module on the host, it waits for the Bluetooth signal transmitted by the host. When the Bluetooth module on the slave detects the Bluetooth signal, the Bluetooth module on the slave decodes the Bluetooth signal and then passes it to the FPGA on the slave.

[0043] The slave FPGA (also called the FPGA on the slave) is used to count the time window of the Bluetooth module broadcast information and obtain a 5ms timing pulse as a timing pulse of a predetermined time.

[0044] The slave receiving module is used to receive the Bluetooth signal. Specifically, the slave receiving module receives the Bluetooth signal from the host via the Bluetooth antenna.

[0045] The slave demodulation module is used to demodulate the Bluetooth signal and extract a timing pulse of a predetermined time based on the demodulated Bluetooth signal. The slave demodulation module is used to demodulate the Bluetooth signal and extract a timing pulse of a second predetermined time based on the demodulated Bluetooth signal, for example, a timing pulse of 5 ms.

[0046] The slave FPGA is used to multiply the timing pulse of the predetermined time to obtain a given timing pulse T0, adjust the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and output the adjusted square wave level. The slave FPGA includes a theoretical rising edge acquisition module, a calibrated rising edge acquisition module, a comparison module and an adjustment module. The theoretical rising edge acquisition module is used to obtain the theoretical number of rising edges N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0. The calibrated rising edge acquisition module is used to calibrate the frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB The comparison module is used to compare the difference between the theoretical rising edge number and the calibrated rising edge number with the target rising edge number N. offset The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level. The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level, including: when the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration is N FB When the difference in rising edges is greater than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is reduced; when the comparison result is that the difference in rising edges is greater than the target number of rising edges N offset And the number of rising edges after calibration is N FB When the difference in rising edges is less than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is increased; and when the comparison result is that the difference in rising edges is less than or equal to the target number of rising edges N offset When the FPGA square wave level is set to zero, the duty cycle X remains unchanged.

[0047] The slave RC integration circuit is used to integrate the adjusted square wave level to generate an adjustment voltage. Specifically, the slave RC integration circuit includes a resistor and a capacitor, wherein one end of the resistor is connected to the output end of the FPGA on the slave as the input end of the RC integration circuit, and the other end is connected to one end of the capacitor and serves as the output end of the RC integration circuit; the other end of the capacitor is grounded. For example, a 10K resistor in series is connected to a 1uF capacitor to ground. When the input frequency is a PWM wave of 1KHz, the output can be converted into a more stable adjustment voltage. The resistance and capacitance values ​​are determined according to the actual adjustment results.

[0048] The slave voltage-controlled temperature-compensated oscillator is used to oscillate according to the adjustment voltage to generate an output frequency, wherein a feedback clock frequency is generated based on the output frequency.

[0049] The slave two-power divider is used to divide the output frequency of the host voltage-controlled temperature-compensated oscillator to generate a feedback clock frequency and a calibrated reference clock frequency. Specifically, the frequency conversion system set on the slave is connected to one output end of the slave two-power divider to receive the calibrated reference clock frequency of the slave; the other output end of the slave two-power divider outputs the feedback clock frequency to the slave FPGA.

[0050] The slave oscillator oscillates based on the calibrated reference clock frequency of the slave to generate a slave local oscillator clock frequency synchronized with the master local oscillator clock frequency.

[0051] refer to Figure 7 Another specific embodiment of the present invention discloses a master-slave frequency synchronization method for 5G indoor wireless frequency shifting, including: in step S701, receiving a base station signal or a Bluetooth signal; in step S702, demodulating the base station signal or the Bluetooth signal, and extracting a timing pulse of a predetermined time based on the demodulated base station signal or the Bluetooth signal; in step S703, multiplying the timing pulse of the predetermined time to obtain a given timing pulse T0, adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and outputting the adjusted square wave level; in step S704, integrating the adjusted square wave level to generate an adjustment voltage; and in step S705, oscillating according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

[0052] Adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency and outputting the adjusted square wave level further includes: obtaining the theoretical number of rising edges N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0; calibrating the frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB ; The difference between the theoretical rising edge number and the calibrated rising edge number and the target rising edge number N offset A comparison is performed, wherein the duty cycle of the square wave level of the FPGA is adjusted according to the comparison result to obtain an adjusted square wave level.

[0053] Adjusting the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level further includes: when the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration is N FBWhen the difference in rising edges is greater than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is reduced; when the comparison result is that the difference in rising edges is greater than the target number of rising edges N offset And the number of rising edges after calibration is N FB When the difference in rising edges is less than the theoretical number of rising edges N0, the duty cycle X of the square wave level of the FPGA is increased; and when the comparison result is that the difference in rising edges is less than or equal to the target number of rising edges N offset The duty cycle X of the square wave level of the FPGA remains unchanged. The PWM wave frequency of the FPGA is adjusted according to the given timing pulse T0.

[0054] refer to Figure 2 , the master and slave use the local reference clock f REF_Z 、f REF_C Generates the local oscillator frequency LO RF_Z , LO IF_Z , LO RF_C With LO IF_C The host and slave modules communicate using a pair of Bluetooth chips. REF_Z 、f REF_C Both are generated by VC-TCXO (voltage-controlled temperature-compensated oscillator), and FPGA is used to calibrate the VC-TCXO in real time. The host realizes frequency calibration through the 5ms pulse information output by 5G_modem. The host modulates the 5ms pulse information generated by 5G_modem into the Bluetooth signal and sends it to the slave. The slave realizes frequency calibration by demodulating the Bluetooth signal of the host (that is, realizing real-time automatic calibration of the frequency of the host and slave), thereby achieving the purpose of 5G channel homology between the master and slave.

[0055] In the following, reference Figures 3 to 6 The master-slave frequency synchronization method for 5G indoor wireless frequency shift according to an embodiment of the present invention is described in detail by way of a specific example.

[0056] Parameter definition:

[0057] f REF_Z 、f REF_C : Reference clock generated by local VC-TCXO of master and slave

[0058] V C :V CONT The control voltage of VC-TCXO is adjusted by V C The voltage can achieve the VC-TCXO output frequency f REF Adjustment, V CONT With f REF Linear correlation, the corresponding relationship is:

[0059] V CONT =1.4V±1.0V, f REFThe adjustment range is ±9~±15ppm.

[0060] f FB :Feed Back Frequency Feedback frequency. REF After two power divisions, all the way as f REF_Z or REF_C Output to the local as reference clock, one way as f FB Output to FPGA as feedback frequency.

[0061] f0: target frequency.

[0062] f' FB : Calibrated f FB .

[0063] f offset : Target frequency error, i.e. f offset =f' FB -f0, the calibration threshold is f offset / f0≤0.05ppm.

[0064] N offset :f offset The corresponding rising edge number difference, that is, N offset =|T0 / f' FB -T0 / f0|.

[0065] X: square wave duty cycle output by FPGA, level value 3.3V, default value 42.42%, range 12.12%~72.72%, adjustment step is ±0.04%.

[0066] refer to Figure 3 and Figure 5 , the host frequency calibration implementation steps are as follows:

[0067] Step 1: The host receives the signal from the base station, couples a downlink signal to the 5G_modem, uses the 5G_modem to demodulate the base station signal, obtains a 5ms timing pulse, and inputs it to the host FPGA.

[0068] Step 2: FPGA multiplies the 5ms timing pulse to obtain the timing pulse T0. For example, the 5ms timing pulse is multiplied by 5, and the multiplied T0 is 1ms. The multiplication number is a value defined by the protocol.

[0069] Step 3: The FPGA output duty cycle is X square wave level. The RC integrator circuit is used to integrate the signal and the output voltage V C , VC-TCXO starts oscillating, output frequency f FB .

[0070] Step 4: FPGA to fFB Oversampling is performed, and the FPGA uses T0 as a reference to f FB The rising edge is counted, recorded as N FB .

[0071] Step 5: FPGA compares the theoretical number of rising edges N0 = T0 / f0 with the statistical f FB Number of rising edges N FB Make comparisons.

[0072] A. If | N FB -N0|>N offset And N FB >N0, then adjust the duty cycle X, stepping -0.04%.

[0073] B. If | N FB -N0|>N offset And N FB <N0, then adjust the duty cycle X, step by +0.04%.

[0074] C. If | N FB -N0|≤N offset , the duty cycle X remains unchanged.

[0075] The stepping rate is 0.04% according to the frequency f of the VC-TCXO. FB With calibration voltage V C The slope of is determined by: V C Adjustment range 1.5V±1V, corresponding to f FB The frequency deviation range is ±15ppm. To achieve the calibration index of 0.05ppm (specified in the 3GPP protocol), the theoretical maximum adjustment step is: (1*2) / (15*2 / 0.05)=0.16%. However, since there is a positive and negative deviation of one step when calibrating the master and slave, considering this error, the maximum adjustment step is: 0.16 / (2*2)=0.04%. The step of 0.04% needs to be determined according to the requirements and device performance.

[0076] Step 6: f after power divider output calibration REF_Z .

[0077] Repeat steps 1 to 5 to maintain automatic calibration of the host frequency.

[0078] Block diagram Figure 3 As shown in the flow chart, Figure 5 shown.

[0079] refer to Figure 4 and Figure 6 , the slave frequency calibration implementation steps are as follows:

[0080] Step 1: The host receives the signal from the base station, couples the downlink signal to the 5G_modem, uses the 5G_modem to demodulate the signal from the base station, obtains a 5ms timing pulse, and inputs it to the host FPGA.

[0081] Step 2: The host FPGA uses the 5ms timing pulse as an interrupt trigger and sends a command to the Bluetooth module on the host, and the Bluetooth module host broadcasts once.

[0082] Step 3: After the Bluetooth module on the slave establishes a connection with the Bluetooth module on the host, it waits for the host's broadcast. When the host's broadcast is detected, the Bluetooth module decodes the information and passes it to the FPGA on the slave.

[0083] Step 4: The FPGA on the slave device counts the time window of the Bluetooth module receiving information to obtain 5ms timing information.

[0084] Step 5: FPGA multiplies the frequency of the 5ms timing pulse to obtain the timing pulse T0.

[0085] Step 6: The FPGA output duty cycle is X square wave level. Use RC integration circuit to integrate the signal and output voltage V C , VC-TCXO starts oscillating, output frequency f FB .

[0086] Step 7: FPGA to f FB Oversampling is performed, and the FPGA uses T0 as a reference to f FB The rising edge is counted, recorded as N FB .

[0087] Step 8: FPGA compares the theoretical number of rising edges N0 = T0 / f0 with the statistical f FB Number of rising edges N FB Make comparisons.

[0088] A. If | N FB -N0|>N offset And N FB >N0, then adjust the duty cycle X, stepping -0.04%.

[0089] B. If | N FB -N0|>N offset And N FB <N0, then adjust the duty cycle X, step by +0.04%.

[0090] C. If | N FB -N0|≤N offset , the duty cycle X remains unchanged.

[0091] Step 9: f after power divider output calibrationREF_Z .

[0092] Repeat steps 1 to 8 to maintain automatic calibration of the host frequency.

[0093] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0094] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A master-slave frequency synchronization device for 5G indoor wireless frequency shifting, characterized in that: The invention comprises a host and a plurality of slaves, wherein the host and the slaves each comprise: A receiving module, used for receiving base station signals or Bluetooth signals; A demodulation module, used to demodulate the base station signal or the Bluetooth signal, and extract a timing pulse of a predetermined time based on the demodulated base station signal or Bluetooth signal; FPGA, used for multiplying the timing pulse of the predetermined time to obtain a given timing pulse T0, adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and outputting the adjusted square wave level; an RC integrator circuit, configured to integrate the adjusted square wave level to generate an adjusted voltage; and A voltage-controlled temperature-compensated oscillator is used to oscillate according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

2. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 1 is characterized in that: The FPGA includes a theoretical rising edge acquisition module, a calibrated rising edge acquisition module, a comparison module and an adjustment module, wherein: The theoretical rising edge acquisition module is used to acquire the theoretical rising edge number N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0; The calibration rising edge acquisition module is used to calibrate the frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB ; The comparison module is used to compare the rising edge difference between the theoretical rising edge number and the calibrated rising edge number with the target rising edge number N. offset Make comparisons; and The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level.

3. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 2 is characterized in that: The adjustment module is used to adjust the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level, including: When the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FB When it is greater than the theoretical number of rising edges N0, reducing the duty cycle X of the square wave level of the FPGA; When the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FB When the number of rising edges is less than the theoretical number N0, increasing the duty cycle X of the square wave level of the FPGA; and When the comparison result is that the rising edge difference is less than or equal to the target rising edge number N offset , the duty cycle X of the square wave level of the FPGA remains unchanged.

4. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 2 is characterized in that: The host and the slave also include two power dividers and a frequency conversion system for power-sharing the output frequency of the voltage-controlled temperature-compensated oscillator to generate a feedback clock frequency and a calibrated reference clock frequency, wherein: When the demodulation module is a 5G modem provided on the host, the frequency conversion system on the host is connected to one output end of the two-power divider on the host to receive the calibrated reference clock frequency of the host, and the other output end of the two-power divider on the host is used to output the feedback clock frequency to the FPGA on the host; When the demodulation module is a Bluetooth module set on the slave, the frequency conversion system on the slave is connected to one output end of the two-power divider on the slave to receive the calibrated reference clock frequency of the slave, and the other output end of the two-power divider on the slave is used to output the feedback clock frequency to the FPGA on the slave.

5. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 4 is characterized in that: The host further includes a host oscillator, and the slave further includes a slave oscillator, wherein: The host oscillator oscillates based on the calibrated reference clock frequency of the host to generate a host local oscillator clock frequency synchronized with the base station clock frequency; The slave oscillator oscillates based on the calibrated reference clock frequency of the slave to generate a slave local oscillator clock frequency synchronized with the master local oscillator clock frequency.

6. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 4 is characterized in that: The 5G modem is used to demodulate the base station signal from the 5G base station and extract a 5 ms timing pulse from the demodulated base station signal as the timing pulse of the predetermined time; The FPGA of the host is used to use the 5 ms timing pulse as an interrupt instruction for triggering an interrupt, and then send the interrupt instruction to the Bluetooth module on the host, and control the Bluetooth module on the host to transmit a Bluetooth signal based on the interrupt instruction; After the Bluetooth module on the slave establishes a connection with the Bluetooth module on the host, it waits for a Bluetooth signal transmitted by the host. When the Bluetooth module on the slave detects the Bluetooth signal, the Bluetooth module on the slave decodes the Bluetooth signal and then transmits it to the FPGA on the slave; and The FPGA on the slave device is used to count the time window of the Bluetooth module broadcasting information, and obtain a timing pulse of 5ms as the timing pulse of the predetermined time.

7. The master-slave frequency synchronization device for 5G indoor wireless frequency shifting according to claim 1, characterized in that: The RC integration circuit includes a resistor and a capacitor, wherein, The resistor has one end connected to the output end of the FPGA as the input end of the RC integration circuit, and the other end connected to one end of the capacitor as the output end of the RC integration circuit; The other end of the capacitor is grounded.

8. A master-slave frequency synchronization method for 5G indoor wireless frequency shifting, characterized in that: include: Receive base station signals or Bluetooth signals; Demodulating the base station signal or the Bluetooth signal, and extracting a timing pulse of a predetermined time based on the demodulated base station signal or the Bluetooth signal; Multiplying the timing pulse of the predetermined time to obtain a given timing pulse T0, adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency, and outputting the adjusted square wave level; integrating the adjusted square wave level to generate an adjusted voltage; as well as Oscillate according to the adjustment voltage to generate an output frequency, wherein the feedback clock frequency is generated based on the output frequency.

9. The master-slave frequency synchronization method for 5G indoor wireless frequency shifting according to claim 8, characterized in that: Adjusting the duty cycle of the square wave level based on the given timing pulse, the target frequency and the feedback clock frequency and outputting the adjusted square wave level further includes: Obtaining a theoretical number of rising edges N0=T0 / f0 based on the given timing pulse T0 and the target frequency f0; The calibration frequency f' based on the given timing pulse T0 and the feedback clock frequency FB Get the number of rising edges after calibration N FB =T0 / f' FB ; The difference between the theoretical number of rising edges and the calibrated number of rising edges and the target number of rising edges N offset A comparison is performed, wherein the duty cycle of the square wave level of the FPGA is adjusted according to the comparison result to obtain the adjusted square wave level.

10. The master-slave frequency synchronization method for 5G indoor wireless frequency shifting according to claim 9, characterized in that: Adjusting the duty cycle of the square wave level of the FPGA according to the comparison result to obtain the adjusted square wave level further includes: When the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FB When it is greater than the theoretical number of rising edges N0, reducing the duty cycle X of the square wave level of the FPGA; When the comparison result is that the rising edge difference is greater than the target rising edge number N offset And the number of rising edges after calibration N FB When the number of rising edges is less than the theoretical number N0, increasing the duty cycle X of the square wave level of the FPGA; and When the comparison result is that the rising edge difference is less than or equal to the target rising edge number N offset , the duty cycle X of the square wave level of the FPGA remains unchanged.

Images