Memory structure and forming method of memory structure

Abstract

A memory structure and a forming method thereof are provided, the memory structure comprises a substrate, the substrate comprises a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions are internally provided with a plurality of mutually discrete active regions, the first regions and the second regions are arranged along a second direction, and the active regions stretch across the first regions and the second regions, the first direction and the second direction are parallel to the surface of the substrate, and the first direction is perpendicular to the second direction; the connecting parts are located in the second region and located between the adjacent active regions; the storage gate structures are located in the first region, adjacent to the second region and located on the two sides of the second region respectively; and the source line structure is positioned on the active region of the second region and the connecting part. The source line structure is located between the active regions of the second region and is connected by the connecting part, so that the contact area of the source line structure is increased, the contact resistance is reduced, and the performance of the device structure is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a memory structure and a method for forming the memory structure. Background Art

[0002] NOR Flash is developed based on the ETOX structure proposed by Intel. It is a non-volatile memory, which means that the stored data will not be lost after the chip is powered off. At the same time, NOR Flash is a voltage-controlled device that uses hot electron injection to write data and erases data based on the tunnel effect. One of its notable features is its fast random read speed. As a non-volatile memory, NOR Flash has the characteristics of non-volatility, high device density, low power consumption and electrical rewritability. It is widely used in portable electronic products such as mobile phones, digital cameras, smart cards, etc.

[0003] However, existing NOR Flash devices still have many problems during their formation. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a memory structure and a method for forming the memory structure, so as to improve the performance of the device structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a memory structure, including: a substrate, the substrate including a plurality of first regions, and a second region located between adjacent first regions, the first region and the second region having a plurality of mutually discrete active regions, the active regions being arranged along a first direction, the active regions extending along a second direction, the first region and the second region being arranged along the second direction, and the active regions spanning the first region and the second region, the first direction and the second direction being parallel to a surface of the substrate, and the first direction being perpendicular to the second direction; a connecting portion located in the second region, the connecting portion being located between adjacent active regions; a storage gate structure located in the first region, the storage gate structure being adjacent to the second region, and the storage gate structure being respectively located on both sides of the second region; and a source line structure located on the active region and on the connecting portion of the second region.

[0006] Optionally, the memory structure further includes: an isolation structure located in the first region, wherein the isolation structure is located between the active regions.

[0007] Optionally, the storage gate structure includes: a floating gate structure located on each active region and a control gate structure located on a surface of the floating gate structure and a surface of the isolation structure.

[0008] Optionally, the memory gate structure further includes: a control gate dielectric layer located on the surface of the floating gate structure. Optionally, the memory structure further includes: a first doped layer located in the active region of the second region and in the connecting portion.

[0009] Optionally, the doping ions in the first doping layer include oxygen ions and / or nitrogen ions.

[0010] Optionally, the storage gate structure further includes: a second doped layer located in the active region of the first region, and the first doped layer and the second doped layer are respectively located on two sides of the storage gate structure.

[0011] The technical solution of the present invention also provides a method for forming a memory structure, including: providing an initial substrate, the initial substrate including a plurality of first regions and a second region located between adjacent first regions, the first regions and the second regions being arranged along a second direction; patterning the initial substrate to form a substrate, the substrate including a plurality of discrete active regions and a plurality of connecting portions, the active regions being arranged along a first direction, the active regions being parallel to the second direction, and the active regions spanning the first region and the second region, the connecting portions being located in the second region between adjacent active regions, the first direction and the second direction being parallel to the substrate surface, and the first direction being perpendicular to the second direction; forming a storage gate structure in the first region, the storage gate structure being adjacent to the second region, and the storage gate structure being respectively located on both sides of the second region; and forming a source line structure on the active region and the connecting portions of the second region.

[0012] Optionally, the method for forming a memory structure further includes: forming an isolation structure in the first region, wherein the isolation structure is located between the active regions.

[0013] Optionally, the method for patterning the initial substrate includes: forming a protective layer on the second area; forming a plurality of mutually discrete first masks on the first area and on the protective layer, the first masks being arranged along a first direction, the first masks being parallel to the second direction, and the first masks spanning the surface of the protective layer on the second area; etching the initial substrate using the protective layer and the first masks as masks to form a substrate and an isolation trench; forming an initial isolation structure in the isolation trench, wherein the surface of the initial isolation structure is flush with the protective layer.

[0014] Optionally, the method for forming a memory structure further includes: before forming the protection layer, forming a first doping layer on the active area and the connecting portion in the second region.

[0015] Optionally, the method for forming the first doping layer includes: forming a common source mask on the initial substrate, the common source mask exposing the surface of the second region; and performing ion implantation on the active region and the connecting portion in the second region to form the first doping layer.

[0016] Optionally, the method for forming the protection layer includes: after forming the first doping layer, forming the protection layer in the common source mask opening; after forming the protection layer, removing the common source mask.

[0017] Optionally, the method for forming a storage gate structure includes: after forming an initial isolation structure, forming a floating gate material layer on the active area of ​​the first region, the floating gate material layer exposing the surface of the protective layer and the surface of the initial isolation structure; removing the protective layer, forming a first opening between the floating gate material layers to expose the second region; removing the initial isolation structure above the surface of the substrate, forming a second opening between the floating gate material layers on the first region, and forming an isolation structure exposed at the bottom of the second opening; forming a control gate material layer on the second region and on a portion of the first region adjacent to both sides of the second region, the control gate material layer being located on the surface of the floating gate material layer, in the first opening, and in the second opening; forming a patterned layer on the control gate material layer, the patterned layer exposing the surface of the control gate material layer on the second region; etching a portion of the control gate material layer and the floating gate material layer using the patterned layer as a mask until the top surface of the substrate is exposed, forming a storage gate structure and a source line opening located between the storage gate structures, the source line opening exposing the active area and the connection portion of the second region, the storage gate structure including a floating gate located on the active area of ​​the first region and a control gate located on the floating gate and on the isolation structure.

[0018] Optionally, the method for forming a memory structure further includes: forming a floating gate dielectric layer on the surface of the active region before forming the floating gate material layer; and forming a control gate dielectric layer on the surface of the floating gate material layer before forming the control gate material layer.

[0019] Optionally, the method for forming a memory structure further includes: after forming the memory gate structure, forming a source line structure in the source line opening.

[0020] Optionally, the method for forming a memory structure further includes: forming a second doping structure in the active region on both sides of the memory gate structure and the source line structure.

[0021] Optionally, the method for removing the protective layer includes: removing the protective layer by a wet etching process; the etching solution of the wet etching process includes: hydrofluoric acid.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the storage structure of the technical solution of the present invention, the connecting portion is located between adjacent active areas in the second zone, and the source line structure is located on the active area and the connecting portion in the second zone, so that the source line structure can be connected to the substrate through the connecting portion between adjacent active areas in the second zone, which can increase the contact area between the source line structure and the substrate, reduce the contact resistance of the source line structure, and thus improve the performance of the device structure.

[0024] In the method for forming a storage structure of the technical solution of the present invention, by directly forming the active area and the connecting portion of the second zone on the substrate, and forming a source line structure on the active area and the connecting portion of the second zone, the contact area between the source line structure and the substrate is increased, thereby reducing the contact resistance.

[0025] Furthermore, the technical solution of the present invention forms a protective layer on the active area of ​​the second zone and on the connecting portion, thereby accurately defining the floating gate structure and increasing the process window of lithography alignment; in addition, the technical solution of the present invention forms a storage gate structure through a graphical process and forms a source line structure between the storage gate structures, thereby further achieving precise alignment of the graphical process, reducing the spacing between the storage gate structures without increasing the number of mask layers, thereby achieving a reduction in the area of ​​the memory structure.

[0026] Furthermore, the technical solution of the present invention provides blocking protection for subsequent etching of the storage gate structure by forming a control gate dielectric layer on the surface of the floating gate material layer, thereby increasing the process window of photolithography alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a memory structure formation process in one embodiment;

[0028] Figures 2 to 3 is a schematic diagram of a memory structure formation process in another embodiment;

[0029] Figures 4 to 28 It is a schematic diagram of the memory structure formation process in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the existing Nor Flash device needs to be further improved. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0031] Figure 1 is a schematic diagram of a memory structure forming process in one embodiment.

[0032] Please refer to Figure 1 The memory structure includes: a substrate 100, the substrate 100 includes a plurality of first regions I, and a second region II located between adjacent first regions I, the first region I and the second region II have a plurality of mutually discrete active regions 101, the active regions 101 are arranged along a first direction X, the active regions 101 extend along a second direction Y, the first region I and the second region II are arranged along the second direction Y, and the active regions 101 span the first region I and the second region II, the first direction X and the second direction Y are parallel to the surface of the substrate 100, and the first direction X is perpendicular to the second direction Y; a memory gate structure 102 located in the first region I, the memory gate structure 102 is adjacent to the second region II, and the memory gate structure 102 is respectively located on both sides of the second region II; a source line structure 103 located on the second region II.

[0033] In the above scheme, during the formation of the memory structure, a memory gate structure 102 is formed through a first graphic process; a source line structure 103 is formed on the second region II through a second graphic process. Since there is a deviation in the alignment between the first graphic process and the second graphic process, in order to ensure precise alignment between the graphic processes, it is required that the spacing between the memory gate structures 102 cannot be too small, which leads to an increase in the area of ​​the memory structure.

[0034] In order to reduce the area of ​​the memory structure, the prior art proposes another memory structure, please refer to Figure 2 , Figure 2 The schematic diagram of the top view structure is as follows. The memory structure includes: a substrate 200, the substrate 200 includes a plurality of first regions I, and a second region II located between adjacent first regions I, the first region I and the second region II have a plurality of mutually discrete active regions 201, the active regions 201 are arranged along a first direction X, the active regions 201 extend along a second direction Y, the first region I and the second region II are arranged along the second direction Y, and the active regions 201 span the first region I and the second region II, the first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X is perpendicular to the second direction Y; an isolation structure 204 located in the second region II, the isolation structure 204 is located between adjacent active regions 201; a storage gate structure 202 located in the first region I, the storage gate structure 202 is adjacent to the second region II, and the storage gate structure 202 is respectively located on both sides of the second region II; a doping layer 203 located on the active region 201 of the second region II; and a source line structure (not shown in the figure) located on the doping layer 203 and the isolation structure 204.

[0035] Please refer to Figure 3 , Figure 3 for Figure 2 The cross-sectional structural diagram along the AA1 direction in FIG. 1 , the memory structure further includes: a source line structure 205 located on the doped layer 203 and the isolation structure 204 .

[0036] In the above scheme, during the formation of the memory structure, the spacing between the memory gate structures 202 is reduced through the manufacturing method of the self-aligned memory gate structure 202 and the source line structure 205, thereby reducing the area of ​​the memory structure. However, due to the existence of the isolation structure 204 located between the adjacent active areas 201 in the second area II, the contact area of ​​the source line structure 205 is reduced, thereby increasing the contact resistance.

[0037] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the memory structure, adopting a manufacturing method of a self-aligned memory gate structure and a source line structure, and the source line structure is located between the active areas of the second area and connected by a connecting part, thereby increasing the contact area of ​​the source line structure without changing the spacing between the memory gate structures, reducing the contact resistance, and thereby improving the performance of the device structure.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 28 It is a schematic diagram of the memory structure formation process in an embodiment of the present invention.

[0040] Please refer to Figure 4 , an initial substrate 300 is provided, the initial substrate 300 includes a plurality of first regions I, and second regions II located between adjacent first regions I, and the first regions I and the second regions II are arranged along a second direction Y.

[0041] In this embodiment, the initial substrate 300 is subsequently patterned to form a substrate. Figures 5 to 21 .

[0042] In this embodiment, the material of the substrate is silicon.

[0043] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0044] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 In the cross-sectional diagram along line BB1, a common source mask 301 and a common source mask opening 302 are formed on the initial substrate 300, and the common source mask 301 exposes the surface of the second region II; ion implantation is performed on the substrate surface on the second region II to form a first doped layer 303 on the second region II.

[0045] In this embodiment, the first doping layer 303 is used to improve the hot carrier injection effect problem.

[0046] In this embodiment, the doping ions in the first doping layer 303 include oxygen ions and / or nitrogen ions.

[0047] In this embodiment, the material of the common source mask 301 includes silicon nitride.

[0048] In this embodiment, the process further includes: before forming the common source mask 301 , forming a buffer layer (not shown in the figure) on the surface of the initial substrate 300 .

[0049] The buffer layer (not shown in the figure) is used to protect the surface of the initial substrate 300 from being damaged.

[0050] The material of the buffer layer (not shown in the figure) includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0051] In this embodiment, the material of the buffer layer includes silicon oxide, and the process of forming the buffer layer includes a wet oxidation process.

[0052] In this embodiment, the process of removing the buffer layer includes a wet etching process, and the wet etching process will not cause damage to the surface of the initial substrate 300 .

[0053] In this embodiment, the material of the common source mask 301 is different from that of the buffer layer, so that the buffer layer can better protect the surface of the initial substrate 300 during the process of forming the common source mask 301 .

[0054] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 In the cross-sectional view along line BB1 ​​, after forming the first doping layer 303 , a protection layer 304 is formed in the common source mask opening 302 .

[0055] In this embodiment, the protection layer 304 is used to protect the active region in the second region II and the first doped layer 303 on the connecting portion, and to provide precise alignment for a subsequently formed memory gate structure.

[0056] In this embodiment, the method for forming the protective layer 304 includes: depositing an initial protective layer (not shown in the figure) in the common source mask opening 302; and flattening the initial protective layer (not shown in the figure) until the surface of the common source mask 301 is exposed to form the protective layer 304.

[0057] The deposition method includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0058] The planarization method includes: chemical mechanical polishing process.

[0059] In this embodiment, the material of the protection layer 304 includes silicon oxide, and the height of the protection layer 304 is flush with the common source mask 301 .

[0060] Please refer to Fig. 9 and Fig.10 , Fig. 9 yes Fig.10 In the cross-sectional diagram along line BB1, a plurality of mutually discrete first masks 305 are formed on the first region I and a portion of the protective layer 304. The first masks 305 are arranged along the first direction X, the first masks 305 are parallel to the second direction Y, and the first masks 305 span the surface of the protective layer 304 on the second region II.

[0061] In this embodiment, the material of the first mask 305 includes silicon nitride.

[0062] In this embodiment, the method for forming the first mask 305 includes: forming a plurality of separate initial first mask layers (not shown in the figure) on the first region I and the protective layer 304; performing a patterning process on the initial first mask layer (not shown in the figure) to form a first mask layer 305 on the common source mask 301 and the protective layer, wherein the first mask layer 305 exposes a portion of the surface of the initial substrate 300.

[0063] Please refer to Fig.11 , Fig.11 The viewing direction and Fig.10 Consistently, the initial substrate 300 is etched with the protection layer 304 and the first mask 305 as masks to form a substrate 306 and an isolation trench 309. The substrate 306 includes a plurality of mutually discrete active areas 307 and a plurality of connecting portions 308. The active areas 307 are arranged along a first direction X, the active areas 307 are parallel to a second direction Y, and the active areas 307 span the first area I and the second area II. The connecting portions 308 are located in the second area II between adjacent active areas 307. The first direction X and the second direction Y are parallel to the surface of the substrate 306, and the first direction X is perpendicular to the second direction Y.

[0064] In this embodiment, the process of etching the initial substrate 300 includes a dry etching process.

[0065] Please refer to Fig.12 and Fig.13 , Fig.12 yes Fig.13 In the cross-sectional view along line BB1, after forming the protection layer 304, the common source mask 301 is removed.

[0066] In this embodiment, after the protection layer 304 is formed, the first mask layer 305 is removed.

[0067] In this embodiment, the method for removing the common source mask 301 and the first mask layer 305 includes: a first wet etching process, and the etching solution of the first wet etching process includes phosphoric acid.

[0068] It should be noted that, in the present embodiment, during the process of removing the common source mask 301, since the active area 307 is covered by the protective layer 304, by adjusting the process parameters of the first wet etching process, it is possible to ensure that only the common source mask 301 in the first area I is removed, while the etching damage to the first doping layer 303 on the lower surface of the protective layer 304 in other areas is very small.

[0069] Please refer to Fig.14 , Fig.15 and Fig.16 , Fig.14 yes Fig.16 Schematic diagram of the cross section along line BB1, Fig.15 yes Fig.16 In the cross-sectional view along line CC1 , an initial isolation structure 310 is formed in the isolation trench 309 , and a surface of the initial isolation structure 310 is flush with the protection layer 304 .

[0070] In this embodiment, the method for forming the initial isolation structure 310 includes: depositing an initial isolation material (not shown in the figure) in the isolation trench 309; and flattening the initial isolation material (not shown in the figure) until the surface of the protective layer 304 is exposed to form the initial isolation structure 310.

[0071] The deposition forming method includes: one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0072] The planarization method includes: chemical mechanical polishing process.

[0073] In this embodiment, the material of the initial isolation structure 310 is consistent with that of the protection layer 304 .

[0074] In this embodiment, the initial isolation structure 310 includes silicon oxide.

[0075] In this embodiment, the initial isolation structure 310 is flush with the protection layer 304 , and the portion of the initial isolation structure that is higher than the substrate determines the thickness of the floating gate formed subsequently.

[0076] Please refer to Fig.17 , Fig.18 and Fig.19 , Fig.17 yes Fig.19 Schematic diagram of the cross section along line BB1, Fig.18 yes Fig.19 In the cross-sectional diagram along line CC1, after the initial isolation structure 310 is formed, a floating gate material layer 311 is formed on the active area 307 of the first region I, and the floating gate material layer 311 exposes the surface of the protection layer 304 and the surface of the initial isolation structure 310.

[0077] In this embodiment, the method for forming the floating gate material layer 311 includes: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0078] Please refer to Fig. 20 , Fig.21 Fig. 22 and Fig.23 , Fig. 20 yes Fig.23 Schematic diagram of the cross section along line DD1, Fig.21 yes Fig.23 Schematic diagram of the cross section along line BB1, Fig. 22 yes Fig.23 In the cross-sectional schematic diagram along the CC1 line, the protection layer 304 is removed, and a first opening (not shown in the figure) exposing the second region II is formed between the floating gate material layers 311; the initial isolation structure 310 higher than the surface of the substrate 306 is removed, and a second opening (not shown in the figure) is formed between the floating gate material layers 311 on the first region I, and an isolation structure 315 exposed at the bottom of the second opening (not shown in the figure) is formed; a control gate material layer 314 is formed on the second region II and on a portion of the first region I adjacent to both sides of the second region II, and the control gate material layer 314 is located on the surface of the floating gate material layer 311, in the first opening (not shown in the figure) and in the second opening (not shown in the figure).

[0079] In this embodiment, the method for removing the protective layer 304 includes: removing the protective layer 304 by using a wet etching process; the etching solution of the wet etching process includes: hydrofluoric acid.

[0080] The protective layer 304 can protect the surface of the first doped layer 303 from being damaged, so that the width loss of the first doped layer 303 is small, and the width of the floating gate material layer can be accurately controlled, thereby accurately controlling the size and spacing of the floating gate formed subsequently, avoiding the problem of reduced reliability due to too small floating gate spacing, and reducing process deviation.

[0081] In this embodiment, the method of removing the initial isolation structure 310 that is higher than the surface of the substrate 306 includes: planarization processing.

[0082] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0083] In this embodiment, by adjusting the process parameters of chemical mechanical polishing, it is ensured that during the polishing process, the silicon oxide above the surface of the substrate 306 is removed and the silicon oxide surface flush with the substrate 306 is removed.

[0084] In this embodiment, before forming the floating gate material layer 311 , a floating gate dielectric layer 312 is formed on the surface of the active region 307 ; before forming the control gate material layer 314 , a control gate dielectric layer 313 is formed on the surface of the floating gate material layer 311 .

[0085] In this embodiment, the material of the floating gate dielectric layer 312 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0086] In this embodiment, the material of the control gate dielectric layer 313 includes: one or more of silicon nitride and silicon oxide.

[0087] Please refer to Fig.24 , Fig.25 and Fig.26 , Fig.24 yes Fig.26 Schematic diagram of the cross section along line DD1, Fig.25 yes Fig.26 In the cross-sectional schematic diagram along line BB1, a patterned layer (not shown in the figure) is formed on the control gate material layer 314, and the patterned layer (not shown in the figure) exposes the surface of the control gate material layer 314 on the second region II; a portion of the control gate material layer 314 and the floating gate material layer 311 are etched using the patterned layer (not shown in the figure) as a mask until the top surface of the substrate 306 is exposed, forming a storage gate structure and a source line opening 318 located between the storage gate structures, the source line opening 318 exposes the active area 307 and the connecting portion 308 of the second region II, and the storage gate structure 319 includes a floating gate 316 located on the active area 307 of the first region I and a control gate 317 located on the floating gate 316 and the isolation structure 315.

[0088] In this embodiment, the material of the floating gate 316 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0089] In this embodiment, the material of the control gate 317 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0090] In this embodiment, the size of the control gate 317 in the direction parallel to the surface of the substrate 306 ranges from 50 nm to 200 nm.

[0091] In this embodiment, a source line structure 320 is formed on the active region and the connecting portion of the second region II.

[0092] In this embodiment, please refer to Fig. 27 , Fig. 27 and Fig.26 The method for forming the source line structure 320 includes: forming the source line structure 320 in the source line opening 318 after forming the storage gate structure 319; and forming a second doping structure 321 in the active area on both sides of the storage gate structure 319.

[0093] Please refer to Fig.28 , Fig.28 yes Fig. 27 The cross-sectional view along the CC1 line in FIG. 3 shows that ion implantation is performed directly on the surface of the substrate 306 to form a first doping layer 303, and a source line structure 320 is formed on the surface of the first doping layer 303, thereby forming Fig.28 The flat structure shown increases the contact area of ​​the source line structure 320, avoids the depth of the isolation trench affecting the resistance of the first doped layer 303, and further reduces the contact resistance.

[0094] Please continue to refer to Fig. 27 The technical solution of the present invention also provides a memory structure, including: a substrate 306, the substrate 306 includes a plurality of first regions I, and a second region II located between adjacent first regions I, the first region I and the second region II have a plurality of mutually discrete active regions 307, the active regions 307 are arranged along a first direction X, the active regions 307 extend along a second direction Y, the first region I and the second region II are arranged along the second direction Y, and the active regions 307 span the first region I and the second region II, the first direction X and the second direction Y are parallel to the surface of the substrate 306, and the first direction X is perpendicular to the second direction Y; a connecting portion 308 located in the second region II, the connecting portion 308 is located between adjacent active regions 307; a storage gate structure 319 located in the first region I, the storage gate structure 319 is adjacent to the second region II, and the storage gate structure 319 is respectively located on both sides of the second region II; and a source line structure 320 located on the active region 307 and the connecting portion 308 of the second region II.

[0095] In this embodiment, the material of the substrate 306 is silicon.

[0096] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0097] In this embodiment, the storage gate structure 319 includes a floating gate 316 and a control gate 317 .

[0098] In this embodiment, the memory structure further includes: an isolation structure 315 located in the first region I, and the isolation structure 315 is located between the active regions 307 .

[0099] In this embodiment, the material of the isolation structure 315 includes silicon oxide.

[0100] In this embodiment, the memory structure further includes: a first doped layer 303 located in the active region 307 of the second region II and in the connecting portion 308 .

[0101] In this embodiment, the doping ions in the first doping layer 303 include oxygen ions and nitrogen ions.

[0102] In this embodiment, the memory structure further includes: a floating gate 316 structure located on each active region and a control gate 317 structure located on the surface of the floating gate 316 structure and the surface of the isolation structure 315 .

[0103] In this embodiment, the material of the floating gate 316 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0104] In this embodiment, the material of the control gate 317 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0105] In this embodiment, the memory structure further includes: a control gate dielectric layer 313 located on the surface of the floating gate 316 structure.

[0106] In this embodiment, the material of the control gate dielectric layer 313 includes: one or more of silicon nitride and silicon oxide.

[0107] In this embodiment, the memory structure further includes: a second doping layer 321 located in the active region 307 of the first region I, and the first doping layer 303 and the second doping layer 321 are respectively located on both sides of the memory gate structure 319 .

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: A substrate, the substrate comprising a plurality of first regions and a second region located between adjacent first regions, the first regions and the second regions having a plurality of mutually discrete active regions, the active regions being arranged along a first direction, the active regions extending along a second direction, the first regions and the second regions being arranged along the second direction, and the active regions spanning the first regions and the second regions, the first direction and the second direction being parallel to a surface of the substrate, and the first direction being perpendicular to the second direction; A connecting portion located in the second region, wherein the connecting portion is located between adjacent active regions; A storage gate structure located in the first region, the storage gate structure is adjacent to the second region, and the storage gate structure is located on both sides of the second region respectively; A source line structure is located on the active region and the connecting portion of the second region.

2. The memory structure according to claim 1, characterized in that: Also includes: An isolation structure is located in the first region, and the isolation structure is located between the active regions.

3. The memory structure according to claim 2, characterized in that: The storage gate structure includes: a floating gate structure located on each active region and a control gate structure located on the surface of the floating gate structure and the surface of the isolation structure.

4. The memory structure according to claim 3, characterized in that: Also includes: A control gate dielectric layer is located on the surface of the floating gate structure.

5. The memory structure according to claim 1, wherein: Also includes: A first doped layer is located in the active area of ​​the second region and in the connecting portion.

6. The memory structure according to claim 5, characterized in that: The doping ions in the first doping layer include oxygen ions and / or nitrogen ions.

7. The memory structure according to claim 5, characterized in that: Also includes: A second doped layer is located in the active area of ​​the first region, and the first doped layer and the second doped layer are respectively located on two sides of the storage gate structure.

8. A method for forming a memory structure, characterized in that: include: Providing an initial substrate, the initial substrate comprising a plurality of first regions and second regions located between adjacent first regions, wherein the first regions and the second regions are arranged along a second direction; Patterning the initial substrate to form a substrate, wherein the substrate includes a plurality of mutually discrete active regions and a plurality of connecting portions, wherein the active regions are arranged along a first direction, the active regions are parallel to a second direction, and the active regions span the first region and the second region, and the connecting portions are located in the second region between adjacent active regions, the first direction and the second direction are parallel to a substrate surface, and the first direction is perpendicular to the second direction; forming a storage gate structure in the first region, the storage gate structure being adjacent to the second region and the storage gate structure being located at two sides of the second region respectively; A source line structure is formed on the active region and the connecting portion of the second region.

9. The method for forming a memory structure according to claim 8, wherein: Also includes: An isolation structure is formed in the first region, wherein the isolation structure is located between the active regions.

10. The method for forming a memory structure according to claim 9, wherein: The method for patterning the initial substrate includes: forming a protective layer on the second area; forming a plurality of mutually discrete first masks on the first area and on the protective layer, wherein the first masks are arranged along a first direction, the first masks are parallel to a second direction, and the first masks span the surface of the protective layer on the second area; etching the initial substrate using the protective layer and the first masks as masks to form a substrate and an isolation trench; forming an initial isolation structure in the isolation trench, wherein the surface of the initial isolation structure is flush with the protective layer.

11. The method for forming a memory structure according to claim 10, wherein: Also includes: Before forming the protection layer, a first doping layer is formed on the active region and the connecting portion in the second region.

12. The method for forming a memory structure according to claim 11, wherein: The method for forming the first doping layer includes: forming a common source mask on an initial substrate, wherein the common source mask exposes the surface of the second region; and performing ion implantation on the active region and the connecting portion in the second region to form the first doping layer.

13. The method for forming a memory structure according to claim 12, wherein: The method for forming the protection layer comprises: forming the protection layer in the common source mask opening after forming the first doping layer; After forming the protection layer, the common source mask is removed.

14. The method for forming a memory structure according to claim 10, wherein: The method for forming the storage gate structure comprises: after forming the initial isolation structure, forming a floating gate material layer on the active area of ​​the first region, the floating gate material layer exposing the surface of the protection layer and the surface of the initial isolation structure; removing the protection layer, forming a first opening between the floating gate material layers to expose the second region; removing the initial isolation structure above the substrate surface, forming a second opening between the floating gate material layers on the first region, and forming an isolation structure exposed at the bottom of the second opening; forming a control gate material layer on the second region and on a portion of the first region adjacent to both sides of the second region, the control gate material layer being located in the The surface of the floating gate material layer, the inside of the first opening and the inside of the second opening; a patterned layer is formed on the control gate material layer, the patterned layer exposes the surface of the control gate material layer on the second region; the control gate material layer and the floating gate material layer are partially etched using the patterned layer as a mask until the top surface of the substrate is exposed, forming the storage gate structure and the source line opening located between the storage gate structures, the source line opening exposes the active area and the connecting portion of the second region, the storage gate structure includes a floating gate located on the active area of ​​the first region and a control gate located on the floating gate and on the isolation structure.

15. The method for forming a memory structure according to claim 14, wherein: Also includes: Before forming the floating gate material layer, forming a floating gate dielectric layer on the surface of the active area; Before forming the control gate material layer, a control gate dielectric layer is formed on the surface of the floating gate material layer.

16. The method for forming a memory structure according to claim 14, wherein: Also includes: After forming the storage gate structure, a source line structure is formed in the source line opening.

17. The method for forming a memory structure according to claim 14, wherein: Also includes: A second doping structure is formed in the active region on both sides of the storage gate structure and the source line structure.

18. The method for forming a memory structure according to claim 14, wherein: The method for removing the protective layer comprises: removing the protective layer by a wet etching process; the etching solution of the wet etching process comprises: hydrofluoric acid.

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