SiC MOSFET device and preparation method thereof

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and relates to the technical field of semiconductors. The epitaxial layer is located on the first surface of the substrate; the first graphene layers are located on the surface, away from the substrate, of the epitaxial layer, and the two first graphene layers are arranged at intervals in the direction parallel to the substrate; the source electrodes are located on the surface, away from the substrate, of the first graphene layer, the two source electrodes are arranged at intervals in the direction parallel to the substrate, and the orthographic projection of the source electrodes is overlapped with the orthographic projection of the first graphene layer in the direction perpendicular to the substrate; the second graphene layer is located on the second surface of the substrate; wherein the first surface and the second surface of the substrate are oppositely arranged; the drain electrode is located on the surface, away from the substrate, of the second graphene layer; the gate dielectric layer is located on the surface, away from the substrate, of the epitaxial layer and located between the two source electrodes; and the gate is located on the surface, deviating from the substrate, of the gate dielectric layer. According to the invention, the performance of the SiC MOSFET device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a SiC MOSFET device and a preparation method thereof. Background Art

[0002] In the integrated circuit manufacturing process, ohmic contact is a key process for device preparation. With the improvement of SiC MOSFET integration and the expansion of its application range, higher requirements are placed on the electrode's specific contact resistance and high-temperature reliability.

[0003] SiC devices are widely used in electronic power systems. The working environment is often under high power, high temperature and high pressure conditions. Under such working conditions, a smaller specific contact resistance is required to reduce conduction loss. In addition, the high temperature and high pressure environment will accelerate the aging of the contact, causing the specific contact resistance to increase or even damage the device and make it unable to work. Therefore, a good ohmic contact needs to take into account both the specific contact resistance and the contact reliability. At present, it is difficult to achieve good contact characteristics and reliability at the same time by changing the components and process conditions of the contact metal. The two often restrict each other in terms of process. In addition, it currently mainly relies on adding additional heat dissipation structures to dissipate heat, and does not change the materials and structures of the MOSFET itself. This approach not only increases the process difficulty and cost, but is also not conducive to the high integration development of SiC MOSFET. The additional heat dissipation structure also increases the risk of failure and reduces the overall reliability. Therefore, it is urgent to provide a SiC MOSFET device and a preparation method thereof to improve the above defects. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a SiC MOSFET device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a SiC MOSFET device, comprising:

[0006] substrate;

[0007] an epitaxial layer, located on a first surface of the substrate;

[0008] The first graphene layer is located on the surface of the epitaxial layer facing away from the substrate, and two first graphene layers are arranged at intervals in a direction parallel to the substrate;

[0009] A source electrode is located on a surface of the first graphene layer facing away from the substrate, two source electrodes are arranged at intervals in a direction parallel to the substrate, and an orthographic projection of the source electrode overlaps with an orthographic projection of the first graphene layer in a direction perpendicular to the substrate;

[0010] A second graphene layer is located on a second surface of the substrate; wherein the first surface and the second surface of the substrate are arranged opposite to each other;

[0011] A drain electrode is located on a surface of the second graphene layer facing away from the substrate;

[0012] A gate dielectric layer is located on the surface of the epitaxial layer facing away from the substrate and between the two source electrodes;

[0013] The gate is located on the surface of the gate dielectric layer facing away from the substrate.

[0014] In a second aspect, the present invention further provides a method for preparing a SiC MOSFET device, comprising:

[0015] Providing a substrate, and implanting N ions into the second surface of the substrate;

[0016] epitaxially growing an epitaxial layer on a first surface of the substrate;

[0017] epitaxially growing a first graphene layer on a surface of the epitaxial layer facing away from the substrate, and epitaxially growing a second graphene layer on a second surface of the substrate;

[0018] Sputtering metal on the first graphene layer to form a source electrode, and sputtering metal in a direction parallel to the substrate to form two source electrodes arranged at intervals;

[0019] sputtering metal on the second graphene layer to form a drain;

[0020] A gate dielectric layer is prepared on the surface of the epitaxial layer facing away from the substrate and between the two source electrodes;

[0021] A gate is formed on the gate dielectric layer.

[0022] Beneficial effects of the present invention:

[0023] The present invention provides a SiC MOSFET device and a preparation method thereof, wherein the source and drain electrodes include a graphene layer. On the one hand, the device has low contact resistance and high thermal stability, and utilizes the flat, dense and uniform characteristics of graphene to effectively prevent the penetration of large atoms and molecules, thereby improving the device's anti-electromigration capability. On the other hand, due to the contact resistance of the source and drain electrodes and the high mobility of graphene, the on-current is improved compared with a traditional structure, and the good heat dissipation of such electrodes is beneficial to the integration and packaging of the device. In addition, the good thermal conductivity of graphene makes the device more thermally stable, reduces the design requirements and difficulty of the heat dissipation structure, and is beneficial to improving the integration of SiC MOSFET.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a SiC MOSFET device provided by an embodiment of the present invention;

[0026] Figure 2 The present invention provides a flow chart of a method for manufacturing a SiC MOSFET device. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] See also Figure 1 , Figure 1 is a schematic diagram of a SiC MOSFET device provided by an embodiment of the present invention. A SiC MOSFET device provided by the present invention includes:

[0029] Substrate 10;

[0030] The epitaxial layer 20 is located on the first surface of the substrate 10;

[0031] The first graphene layer 30 is located on the surface of the epitaxial layer 20 facing away from the substrate 10, and two first graphene layers 30 are arranged at intervals along a direction D1 parallel to the substrate;

[0032] The source electrode 40 is located on the surface of the first graphene layer 30 facing away from the substrate 10. Two source electrodes 40 are arranged at intervals along a direction D1 parallel to the substrate. Along a direction D2 perpendicular to the substrate, the orthographic projection of the source electrode 40 overlaps with the orthographic projection of the first graphene layer 30.

[0033] The second graphene layer 50 is located on the second surface of the substrate 10; wherein the first surface and the second surface of the substrate 10 are arranged opposite to each other;

[0034] a drain electrode 60 , located on a surface of the second graphene layer 50 facing away from the substrate 10 ;

[0035] The gate dielectric layer 70 is located on the surface of the epitaxial layer 20 facing away from the substrate 10 and between the two source electrodes 40;

[0036] The gate 80 is located on the surface of the gate dielectric layer 70 facing away from the substrate 10 .

[0037] For more details, please see Figure 1In this embodiment, a SiC MOSFET device is provided, which is stacked with a substrate 10 and an epitaxial layer 20, a source 40 and a gate 80 are arranged on the epitaxial layer 20, and a drain 60 is arranged on the back of the substrate 10. SiCMOSFET plays an important role in new energy vehicle motors, solar inverters, high-voltage transmission and other occasions due to its high power density and low on-resistance. Although SiC chips can work at high temperatures, the materials (such as electrode materials) supporting them cannot withstand such high temperatures, thereby limiting the application of the device. In addition, the large on-resistance under high power will reduce the working efficiency of the system; therefore, in this embodiment, a metal / graphene / SiC electrode is provided, that is, in addition to a layer of metal, a layer of graphene is also included in the source 40 and the drain 60.

[0038] On the one hand, considering that the port electrode of SiC MOSFET in the prior art adopts the ohmic contact form, the conventional ohmic contact has specific requirements on the doping concentration of the substrate and requires careful selection of the metal system and metal composition; in addition, in order to form an ohmic contact, most processes require an annealing temperature of 950°C or above, while the contact metal of the metal / graphene / SiC structure used in this embodiment has a relatively simple and single structure, and the annealing temperature for achieving ohmic contact is relatively low, and even under certain conditions, ohmic contact can be formed without annealing. Under appropriate conditions, the specific contact resistance can reach 10 -6 Ω·cm 2 , which simplifies the process steps and reduces the process costs to a certain extent.

[0039] On the other hand, SiC MOSFET is often used under high power conditions, and its high thermal stability has always been a research focus. Currently, mainstream Si-based devices introduce cooling systems to ensure thermal stability. This method not only increases the complexity and volume power consumption of the system, but also reduces reliability. The good thermal conductivity inherent in graphene in the metal / graphene / SiC structure provided in this embodiment can improve the heat dissipation performance at the contact point and improve the thermal stability of the device.

[0040] On the other hand, at submicron size, when faced with high current density, high field strength and high temperature conditions, the diffusion or electromigration of the contact metal to the semiconductor becomes a serious problem; under the stress of high current density, the junction temperature will rise rapidly, causing electromigration of the contact metal, thereby destroying the original flat contact morphology, generating peaks, voids and other phenomena, thereby reducing the contact area and increasing the on-resistance. This embodiment introduces graphene at the SiC-Metal interface. Compared with the step-like morphology of the SiC surface, graphene is flatter and denser, and can effectively improve electromigration under high current density.

[0041] In an optional embodiment of the present invention, two P-type well regions 90 arranged at intervals are provided on the side of the epitaxial layer 20 facing away from the substrate 10, and an N+ region 100 is provided on the side of each P-type well region 90 facing away from the substrate 10, and both the P-type well region 90 and the N+ region 100 are provided in the epitaxial layer 20;

[0042] Along a direction D2 perpendicular to the substrate, the orthographic projection of the first graphene layer 30 overlaps with both the orthographic projection of the P-type well region 90 and the orthographic projection of the N+ region 100 .

[0043] In an optional embodiment of the present invention, along a direction D2 perpendicular to the substrate, the first graphene layer 30 and the second graphene layer 50 have the same thickness, and both the first graphene layer 30 and the second graphene layer 50 include multiple graphene layers, and the thickness of a single graphene layer is 0.33 to 0.35 nm.

[0044] Specifically, the metal / graphene electrode provided in this embodiment achieves good heat dissipation at the contact point through the excellent thermal conductivity of graphene. If a heat dissipation structure is added on this basis, the thermal reliability of the device can be further improved.

[0045] Optionally, the first graphene layer 30 and the second graphene layer 50 both include 1 to 5 graphene layers. As the number of graphene layers increases, the thickness of the first graphene layer 30 and the second graphene layer 50 increases, the number of carriers increases, the resistivity decreases, and the bandgap width of the device is improved, see Table 1.

[0046] Table 1 Relationship between graphene layer and device bandgap width

[0047] Bandgap(eV) Thickness(nm) Single graphene layer 0.26 0.35 Double-layer graphene 0.14 0.7 Three graphene layers 0.066 1.05

[0048] In an optional embodiment of the present invention, the substrate 10 is an N+ type SiC substrate 10 .

[0049] Based on the same invention concept, please continue to refer to Figure 2 , Figure 2 : is a flow chart of a method for preparing a SiC MOSFET device provided in an embodiment of the present invention. The present invention also provides a method for preparing a SiC MOSFET device, which is used to prepare the SiC MOSFET device provided in the above embodiment of the present invention. The embodiment of the device is referred to above and will not be described in detail here. The preparation method comprises:

[0050] S101, providing a substrate 10, and implanting N ions into a second surface of the substrate 10;

[0051] S102, epitaxially growing an epitaxial layer 20 on a first surface of the substrate 10;

[0052] S103, epitaxially growing a first graphene layer 30 on a surface of the epitaxial layer 20 facing away from the substrate 10, and epitaxially growing a second graphene layer 50 on a second surface of the substrate 10;

[0053] S104, sputtering metal on the first graphene layer 30 to form a source electrode 40, and sputtering metal along a direction D1 parallel to the substrate to form two source electrodes 40 arranged at intervals;

[0054] S105, sputtering metal on the second graphene layer 50 to form a drain electrode 60;

[0055] S106, forming a gate dielectric layer 70 on the surface of the epitaxial layer 20 facing away from the substrate 10 and between the two source electrodes 40;

[0056] S107 , preparing a gate 80 on the gate dielectric layer 70 .

[0057] In an optional embodiment of the present invention, before epitaxially growing the first graphene layer 30 on the surface of the epitaxial layer 20 facing away from the substrate 10 and epitaxially growing the second graphene layer 50 on the second surface of the substrate 10, the method includes:

[0058] The surface of the epitaxial layer 20 facing away from the substrate 10 and the second surface of the substrate 10 are subjected to hydrogen etching; wherein the hydrogen etching includes an etching temperature of 1500-1700° C., an etching time of 80-100 min, an etching pressure of 95-97 mbar, and a hydrogen flow rate of 89-91 L / min;

[0059] The surface of the epitaxial layer 20 facing away from the substrate 10 and the derivatives of the second surface of the substrate 10 are removed.

[0060] In an optional embodiment of the present invention, removing the surface of the epitaxial layer 20 facing away from the substrate 10 and the derivative of the second surface of the substrate 10 includes:

[0061] After hydrogen etching, the temperature is lowered to 950-1050°C, and hydrogen is introduced at a rate of 1.8-2.1 L / min for 14-16 min;

[0062] Then cool down to 800-850°C, and introduce monosilane at 0.4-0.6 ml / min for 9-11 min under low vacuum;

[0063] Raise the temperature to 950-1000°C under low vacuum and maintain for 4-6 minutes;

[0064] Raise the temperature to 1100-1150°C under low vacuum and maintain for 4-6 minutes;

[0065] Raise the temperature to 1200-1250°C under low vacuum and maintain for 9-11 minutes.

[0066] In an optional embodiment of the present invention, epitaxially growing a first graphene layer 30 on a surface of the epitaxial layer 20 facing away from the substrate 10, and epitaxially growing a second graphene layer 50 on a second surface of the substrate 10, comprises:

[0067] The epitaxial growth temperature is 1600-1700°C, and high-purity argon gas is introduced at 850-950 mbar;

[0068] The duration of epitaxial growth is controlled to obtain a single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 facing away from the substrate 10 and the second surface of the substrate 10 .

[0069] In an optional embodiment of the present invention, metal is sputtered on the first graphene layer 30 to form a source electrode 40, and metal is sputtered on the second graphene layer 50 to form a drain electrode 60, including:

[0070] Sputtering metal on the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 facing away from the substrate 10 to form a first metal layer, and sputtering metal on the single-layer silicon carbide-based epitaxial graphene layer on the second surface of the substrate 10 to form a second metal layer, i.e., a drain 60;

[0071] Coating photoresist on the surface of the first metal layer facing away from the substrate 10, and coating photoresist on the surface of the second metal layer facing away from the substrate 10;

[0072] Patterning the photoresist coated on the first metal layer, wet etching the first metal to form a source electrode 40, and etching the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 away from the substrate 10 by oxygen plasma to form a first graphene layer 30;

[0073] The photoresist coated on the second metal layer is removed, and the photoresist remaining on the first metal layer is removed.

[0074] In this embodiment, in the process steps, for the graphene protection part, the pre-deposited metal (source 40 metal deposition) is directly used to protect the graphene, which reduces the process steps, protects the graphene and facilitates the lithography of the pattern.

[0075] In an optional embodiment of the present invention, implanting N ions into the second surface of the substrate 10 includes:

[0076] Depositing a silicon dioxide layer on the second surface of the substrate 10, using the silicon dioxide layer as a mask;

[0077] The temperature was controlled at 1100-1200°C, the oxygen flow rate was 500-550 ml / min, and maintained for 160-170 min;

[0078] Keep the temperature constant, introduce nitrogen, and perform annealing, cooling to 280-320°C;

[0079] N ions are implanted into the second surface of the substrate 10 at a temperature of 480-520°C.

[0080] In an optional embodiment of the present invention, a SiC MOSFET device is prepared by the following process, specifically:

[0081] S101 , providing a substrate 10 , and implanting N ions into a second surface of the substrate 10 .

[0082] Specifically, a 100 nm thick silicon dioxide layer is deposited on the second surface of the substrate 10, and the silicon dioxide layer is used as a mask;

[0083] The temperature was controlled at 1180°C, the oxygen flow rate was 540 ml / min, and maintained for 165 min;

[0084] Keep the temperature constant, introduce nitrogen, and anneal for 30 minutes; keep the nitrogen atmosphere and gradually cool the sample to below 300°C;

[0085] N ions are implanted into the second surface of the substrate 10 at a temperature of 500° C.

[0086] It should be noted that the ion implantation was performed in four times, and the energy and dose of each implantation were reduced successively; they were: 150keV / 3.1×10 15 cm -2 , 100keV / 1.75×10 15 cm -2 , 62keV / 1.45×10 15 cm -2 , 35keV / 1.1×10 15 cm -2 .

[0087] S102 , epitaxially growing an epitaxial layer 20 on the first surface of the substrate 10 .

[0088] Specifically, after the grown epitaxial layer 20 is cleaned by standard RCA, a 2 μm thick silicon dioxide layer is deposited on the surface of the epitaxial layer 20 facing away from the substrate 10 as an ICP etching mask, photolithography is used to form an injection pattern, and ICP etching is used to open the injection window, remove the resist, inject Al ions, remove the silicon dioxide layer and clean the photoresist to form a P-type well region 90.

[0089] Next, a 2 μm thick silicon dioxide layer is deposited on the side of the epitaxial layer 20 facing away from the substrate 10 as an ICP etching mask, photolithography is performed to form an injection pattern, and ICP etching is used to open the injection window, remove the resist, inject N ions, remove the silicon dioxide layer, clean the photoresist, and form an N+ region 100.

[0090] A layer of C film is magnetron sputtered on the side of the epitaxial layer 20 facing away from the substrate 10 and on the second surface of the substrate 10, and activated annealing is performed at 1700° C. for 30 minutes to remove the C film and clean the optical wafer.

[0091] S103, epitaxially grow a first graphene layer 30 on the surface of the epitaxial layer 20 facing away from the substrate 10, and epitaxially grow a second graphene layer 50 on the second surface of the substrate 10; epitaxially grow two first graphene layers 30 arranged at intervals along a direction D1 parallel to the substrate.

[0092] Specifically, in order to avoid the influence of the epitaxial graphene process on the structure of the gate 80 , the source 40 and the drain 60 are first manufactured in this embodiment.

[0093] First, the surface is etched to form nucleation sites;

[0094] The surface of the epitaxial layer 20 facing away from the substrate 10 and the second surface of the substrate 10 are subjected to hydrogen etching; wherein the hydrogen etching includes an etching temperature of 1600° C., an etching time of 90 min, an etching pressure of 96 mbar, and a hydrogen flow rate of 90 L / min;

[0095] Secondly, remove surface derivatives (Si2C, SiC2, Si2O3, etc.);

[0096] The surface of the epitaxial layer 20 facing away from the substrate 10 and the derivatives of the second surface of the substrate 10 are removed, specifically:

[0097] After hydrogen etching, the temperature is lowered to 950-1050°C, and hydrogen is introduced at a rate of 1.8-2.1 L / min for 14-16 min;

[0098] Then cool down to 800-850°C, and introduce monosilane at 0.4-0.6 ml / min for 9-11 min under low vacuum;

[0099] Raise the temperature to 950-1000°C under low vacuum and maintain for 4-6 minutes;

[0100] Raise the temperature to 1100-1150°C under low vacuum and maintain for 4-6 minutes;

[0101] Raise the temperature to 1200-1250°C under low vacuum and maintain for 9-11 minutes.

[0102] Finally, graphene is grown epitaxially;

[0103] The epitaxial growth temperature is 1650°C, and the heating is as uniform as possible to prevent the generation of temperature gradients. The heating rate is as fast as possible, and high-purity argon gas is introduced at 850-950 mbar;

[0104] The duration of epitaxial growth is controlled to obtain a single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 away from the substrate 10 and the second surface of the substrate 10. Optionally, in this embodiment, the number of epitaxially grown graphene layers is determined according to actual needs, and can be 1 to 5 layers.

[0105] It should be noted that single-layer graphene can also be prepared by transfer plus annealing.

[0106] S104 , sputtering metal on the first graphene layer 30 to form a source electrode 40 , and sputtering metal along a direction D1 parallel to the substrate to form two source electrodes 40 arranged at intervals.

[0107] S105 , sputtering metal on the second graphene layer 50 to form a drain electrode 60 .

[0108] Specifically, metal is sputtered on the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 facing away from the substrate 10 to form a first metal layer, and metal is sputtered on the single-layer silicon carbide-based epitaxial graphene layer on the second surface of the substrate 10 to form a second metal layer, i.e., the drain 60;

[0109] Coating photoresist on the surface of the first metal layer facing away from the substrate 10, and coating photoresist on the surface of the second metal layer facing away from the substrate 10;

[0110] Patterning the photoresist coated on the first metal layer, wet etching the first metal to form a source electrode 40, and etching the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer 20 away from the substrate 10 by oxygen plasma to form a first graphene layer 30;

[0111] The photoresist coated on the second metal layer is removed, and the photoresist remaining on the first metal layer is removed.

[0112] Optionally, the first metal and the second metal are both Au with a thickness of 200 nm. Of course, the metal can also be Ni, Ti, or Pt.

[0113] S106, forming a gate dielectric layer 70 on the surface of the epitaxial layer 20 facing away from the substrate 10 and between the two source electrodes 40;

[0114] S107 , preparing a gate 80 on the gate dielectric layer 70 .

[0115] Specifically, PECVD is used to deposit gate oxide, and then photoresist is applied and exposed to etch away excess silicon oxide. Then, photoresist is applied and exposed again to pattern polysilicon, and then polysilicon is deposited and peeled off to form the gate 80 .

[0116] In this embodiment, a positive source-drain voltage VDS is applied between the drain 60 and the source 40, and a positive voltage VGS is applied between the gate 80 and the source 40, and electrons are attracted to the P-type semiconductor region to form an N-type channel. The current flows from the drain 60 to the source through the channel, reducing the relative contact resistance between the drain 60 and the source 40, and further increasing the saturation current of the drain 60. For the source-drain electrode, SiC epitaxial graphene, due to the high surface state concentration at the contact interface, the height of the contact barrier is pinned by the high-density surface state, and part of the barrier height falls inside the semiconductor, and does not completely depend on the work function of the metal. The carrier concentration at the interface is very high, and electrons and holes are transported by recombination, so that the forward and reverse recombination currents are very large, which destroys the Schottky barrier formed by the contact between graphene and SiC, thereby forming and reducing the contact resistance of the SiC ohmic contact. On the other hand, graphene contacts the SiC substrate 10, and the narrow-bandgap semiconductor and the wide-bandgap semiconductor form a gradual heterojunction, which itself reduces the contact barrier, thereby promoting the formation of ohmic contact and reducing the specific contact resistance. In addition, graphene has high thermal conductivity and can dissipate the heat generated by the device to the environment in a timely manner.

[0117] In summary, the present invention provides a SiC MOSFET device and a preparation method thereof, wherein the source and drain electrodes include a graphene layer. On the one hand, the device has low contact resistance and high thermal stability, and utilizes the flat, dense and uniform characteristics of graphene, which can effectively prevent the penetration of large atoms and molecules and improve the device's resistance to electromigration. On the other hand, due to the contact resistance of the source and drain electrodes and the high mobility of graphene, the on-current is improved compared to the traditional structure, and the good heat dissipation of such electrodes is beneficial to the integration and packaging of the device. In addition, the good thermal conductivity of graphene makes the device more thermally stable, reduces the design requirements and difficulty of the heat dissipation structure, and is beneficial to improving the integration of SiC MOSFET.

[0118] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0119] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0120] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A SiC MOSFET device, characterized in that: include: substrate; an epitaxial layer, located on the first surface of the substrate; A first graphene layer is located on a surface of the epitaxial layer facing away from the substrate, and two first graphene layers are arranged at intervals in a direction parallel to the substrate; A source electrode is located on a surface of the first graphene layer facing away from the substrate, two of the source electrodes are arranged at intervals in a direction parallel to the substrate, and an orthographic projection of the source electrode overlaps with an orthographic projection of the first graphene layer in a direction perpendicular to the substrate; A second graphene layer is located on the second surface of the substrate; wherein the first surface and the second surface of the substrate are arranged opposite to each other; A drain electrode, located on a surface of the second graphene layer facing away from the substrate; A gate dielectric layer, located on a surface of the epitaxial layer facing away from the substrate and between the two source electrodes; The gate is located on a surface of the gate dielectric layer facing away from the substrate.

2. The SiC MOSFET device according to claim 1, characterized in that: Two P-type well regions arranged at intervals are arranged on one side of the epitaxial layer away from the substrate, an N+ region is arranged on one side of each P-type well region away from the substrate, and both the P-type well region and the N+ region are arranged in the epitaxial layer; Along a direction perpendicular to the substrate, an orthographic projection of the first graphene layer overlaps with an orthographic projection of the P-type well region and an orthographic projection of the N+ region.

3. The SiC MOSFET device according to claim 1, characterized in that: Along a direction perpendicular to the substrate, the first graphene layer and the second graphene layer have the same thickness, and both the first graphene layer and the second graphene layer include multiple graphene layers, and the thickness of a single graphene layer is 0.33-0.35 nm.

4. The SiC MOSFET device according to claim 1, characterized in that: The substrate is an N+ type SiC substrate.

5. A method for preparing a SiC MOSFET device, characterized in that: include: Providing a substrate, and implanting N ions into a second surface of the substrate; epitaxially growing an epitaxial layer on a first surface of the substrate; epitaxially growing a first graphene layer on a surface of the epitaxial layer facing away from the substrate, and epitaxially growing a second graphene layer on a second surface of the substrate; Sputtering metal on the first graphene layer to form a source electrode, and sputtering metal in a direction parallel to the substrate to form two source electrodes arranged at intervals; sputtering metal on the second graphene layer to form a drain; Prepare a gate dielectric layer on a surface of the epitaxial layer facing away from the substrate and between the two source electrodes; A gate is prepared on the gate dielectric layer.

6. The method for preparing a SiC MOSFET device according to claim 5, characterized in that: Epitaxially growing a first graphene layer on a surface of the epitaxial layer facing away from the substrate, and before epitaxially growing a second graphene layer on a second surface of the substrate, comprising: The surface of the epitaxial layer facing away from the substrate and the second surface of the substrate are subjected to hydrogen etching; wherein the hydrogen etching includes an etching temperature of 1500-1700° C., an etching time of 80-100 min, an etching pressure of 95-97 mbar, and a hydrogen flow rate of 89-91 L / min; A surface of the epitaxial layer facing away from the substrate and derivatives of the second surface of the substrate are removed.

7. The method for preparing a SiC MOSFET device according to claim 6, characterized in that: The removing of the surface of the epitaxial layer away from the substrate and the derivative of the second surface of the substrate comprises: After hydrogen etching, the temperature is lowered to 950-1050°C, and hydrogen is introduced at a rate of 1.8-2.1 L / min for 14-16 min; Then cool down to 800-850°C, and introduce monosilane at 0.4-0.6 ml / min for 9-11 min under low vacuum; Raise the temperature to 950-1000°C under low vacuum and maintain for 4-6 minutes; Raise the temperature to 1100-1150°C under low vacuum and maintain for 4-6 minutes; Raise the temperature to 1200-1250°C under low vacuum and maintain for 9-11 minutes.

8. The method for preparing a SiC MOSFET device according to claim 5, characterized in that: Epitaxially growing a first graphene layer on a surface of the epitaxial layer facing away from the substrate, and epitaxially growing a second graphene layer on a second surface of the substrate, comprising: The epitaxial growth temperature is 1600-1700°C, and high-purity argon gas is introduced at 850-950 mbar; The duration of epitaxial growth is controlled to obtain a single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer facing away from the substrate and the second surface of the substrate.

9. The method for preparing a SiC MOSFET device according to claim 5, characterized in that: Sputtering metal on the first graphene layer to form a source electrode, and sputtering metal on the second graphene layer to form a drain electrode, comprising: Sputtering metal on the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer away from the substrate to form a first metal layer, and sputtering metal on the single-layer silicon carbide-based epitaxial graphene layer on the second surface of the substrate to form a second metal layer, i.e., the drain; Coating a photoresist on a surface of the first metal layer facing away from the substrate, and coating a photoresist on a surface of the second metal layer facing away from the substrate; Patterning the photoresist coated on the first metal layer, wet etching the first metal to form the source electrode, and etching the single-layer silicon carbide-based epitaxial graphene layer on the surface of the epitaxial layer away from the substrate by oxygen plasma to form the first graphene layer; The photoresist coated on the second metal layer is removed, and the photoresist remaining on the first metal layer is removed.

10. The method for preparing a SiC MOSFET device according to claim 5, characterized in that: Implanting N ions on the second surface of the substrate comprises: Depositing a silicon dioxide layer on the second surface of the substrate, using the silicon dioxide layer as a mask; The temperature was controlled at 1100-1200°C, the oxygen flow rate was 500-550 ml / min, and maintained for 160-170 min; Keep the temperature constant, introduce nitrogen, and perform annealing, cooling to below 300°C; N ions are implanted into the second surface of the substrate at a temperature of 480-520°C.

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