Semiconductor memory device and method of manufacturing the same

Abstract

Semiconductor memory devices and methods of fabricating the same are provided herein. The semiconductor memory device includes: a transistor; a cell array structure; a molded insulation structure including a first region and a second region laterally extending from the first region, the first region being disposed between the transistor and the cell array structure and overlapping the transistor; a transfer gate disposed in a second region of the shaped insulating structure; an active pillar penetrating the transfer gate; and a transfer gate insulating layer disposed between the active pillar and the transfer gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0114326 filed in the Korean Intellectual Property Office on August 30, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional (3D) semiconductor memory device and a method of manufacturing the 3D semiconductor memory device. Background Art

[0004] Semiconductor memory devices are used not only in small electronic devices but also in electronic devices in various fields such as vehicles, medical equipment, and data centers. Therefore, the demand for semiconductor memory devices is increasing.

[0005] A semiconductor memory device may include memory cells for storing data. In order to achieve high capacity in a semiconductor memory device, technical development of a 3D semiconductor memory device including memory cells arranged in a three-dimensional manner is being actively conducted. Summary of the invention

[0006] According to one embodiment of the present disclosure, a semiconductor memory device may include: a transistor; a molded insulating structure including a first region overlapping the transistor and a second region extending laterally from the first region; a transfer gate disposed in the second region of the molded insulating structure; an active pillar penetrating the transfer gate; a transfer gate insulating layer disposed between the active pillar and the transfer gate; a first conductive connection structure disposed in the first region of the molded insulating structure and coupled to the transistor; and a cell array structure including a plurality of memory cells arranged in a three-dimensional manner above the molded insulating structure.

[0007] According to one embodiment of the present disclosure, a semiconductor memory device may include: a semiconductor substrate including a first surface facing a first direction and a second surface facing a direction opposite to the first direction; a gate stack including a plurality of conductive layers stacked above the first surface of the semiconductor substrate in the first direction; a molded insulating structure disposed between the gate stack and the semiconductor substrate and including a first region and a second region extending laterally from the first region; a first conductive connection structure disposed in the first region of the molded insulating structure and extending to contact the semiconductor substrate; a transfer gate disposed in the second region of the molded insulating structure; an active pillar penetrating the transfer gate; and a transfer gate insulating layer disposed between the active pillar and the transfer gate.

[0008] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include: forming a first insulating layer, the first insulating layer including a first region covering a transistor and a second region extending laterally from the first region; forming a second insulating layer above the first insulating layer; etching the first insulating layer and the second insulating layer to form contact holes and active holes, wherein the contact holes pass through portions of the first insulating layer and the second insulating layer overlapping with the first region of the first insulating layer, and wherein the active holes pass through portions of the first insulating layer and the second insulating layer overlapping with the second region of the first insulating layer; forming a transfer gate insulating layer and an active pillar in the active hole; forming a first conductive connection structure in the contact hole; forming a third insulating layer above the second insulating layer to cover the first conductive connection structure and the active pillar; forming a slit passing through the second insulating layer and the third insulating layer; and replacing a portion of the second insulating layer with a transfer gate via the slit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0010] Figure 2 is a circuit diagram illustrating a memory cell array and a transfer circuit according to one embodiment of the present disclosure.

[0011] Figure 3 and Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 5A is a cross-sectional view illustrating a pass transistor group according to one embodiment of the present disclosure, and Figure 5B The diagram is along Figure 5A Line AA' captures a plan view of the pass transistor group.

[0013] FIG. 6A to FIG. 6K is a cross-sectional view illustrating a method of manufacturing a first conductive connection structure and a transfer transistor group of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 7 is a block diagram illustrating an electronic system including a semiconductor memory device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The specific structure or functional description of the embodiment according to the concept of the present disclosure disclosed in this specification or application is exemplified to illustrate the embodiment according to the concept of the present disclosure. The embodiment according to the concept of the present disclosure should not be interpreted as being limited to the embodiment described in this specification or application, and can be modified in various forms and replaced by other equivalent embodiments.

[0016] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and the order or number of components is not limited by these terms. In addition, unless there is a special limitation on the components expressed in the singular or plural, it is not interpreted as limiting the number of components.

[0017] Various embodiments of the present disclosure relate to a semiconductor memory device having an improved level of integration and a method of manufacturing the semiconductor memory device.

[0018] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0019] refer to Figure 1 , the semiconductor memory device 50 may include a memory cell array 10, a transfer circuit 40, and a peripheral circuit structure PS.

[0020] The memory cell array 10 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory cell may be a non-volatile memory cell. In one embodiment, each memory cell may be a NAND flash memory cell. Hereinafter, the embodiments of the present disclosure will be described based on a semiconductor memory device 50 including a NAND flash memory cell, but the embodiments of the present disclosure are not limited thereto. For example, each memory cell may be implemented as a ferroelectric memory cell, a variable resistance memory cell, etc.

[0021] The transfer circuit 40 may be coupled to the memory cell array 10 through a plurality of local lines. In one embodiment, the plurality of local lines may include a plurality of word lines WL, at least one source select line SSL, and at least one drain select line DSL.

[0022] The peripheral circuit structure PS may perform a program operation of storing data in the memory cell array 10, a read operation of outputting data stored in the memory cell array 10, and an erase operation of erasing data stored in the memory cell array 10. In one embodiment, the peripheral circuit structure PS may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a block decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0023] The input / output circuit 21 may transfer a command CMD and an address ADD received from a device (eg, a memory controller) outside the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 may exchange data DATA with the external device and the column decoder 35.

[0024] The control circuit 23 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0025] The voltage generating circuit 31 may generate and output various operating voltages for program operation, read operation, and erase operation in response to the operating signal OP_S. The operating voltages output from the voltage generating circuit 31 may be transmitted to the transfer circuit 40 through a plurality of global lines GLL.

[0026] The block decoder 33 may output a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 may be transmitted to the transfer circuit 40 through the block selection line BSEL.

[0027] In response to a block selection signal received through the block selection line BSEL, the transfer circuit 40 may transfer an operation voltage received through the plurality of global lines GLL to the drain selection line DSL, the word line WL, and the source selection line SSL.

[0028] In response to the column address CADD, the column decoder 35 may transfer data DATA input from the input / output circuit 21 to the page buffer 37 or transfer data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 may exchange data DATA with the input / output circuit 21 through the column lines CL. The column decoder 35 may exchange data DATA with the page buffer 37 through the data lines DL.

[0029] The page buffer 37 may store read data received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 may sense a voltage or current of the bit line BL during a read operation. The page buffer 37 may be coupled to the memory cell array 10 through the bit line BL.

[0030] The source line driver 39 may control a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 may be coupled to the memory cell array 10 through the common source line CSL.

[0031] Figure 2 is a circuit diagram illustrating a memory cell array and a transfer circuit according to one embodiment of the present disclosure.

[0032] refer to Figure 2 , the memory cell array 10 may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may be coupled to a plurality of bit lines BL and a common source line CSL.

[0033] Each memory cell string CS may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0034] The source select transistor SST may control the electrical connection between the plurality of memory cells MC and the common source line CSL, and the drain select transistor DST may control the electrical connection between the plurality of memory cells MC and the corresponding bit line BL.

[0035] A source selection transistor SST or two source selection transistors connected in series may be provided between the common source line CSL and the plurality of memory cells MC. A drain selection transistor DST or two or more drain selection transistors connected in series may be provided between each bit line BL and the plurality of memory cells MC of the memory cell string CS corresponding to the bit line BL.

[0036] A plurality of gates of a plurality of memory cells MC may be coupled to a plurality of word lines WL, respectively. A gate of a source select transistor SST may be coupled to a source select line SSL. A gate of a drain select transistor DST may be coupled to a drain select line DSL.

[0037] The source selection line SSL, the drain selection line DSL, and the plurality of word lines WL may be coupled to the transfer circuit 40. The transfer circuit 40 may include a transfer transistor group, each transfer transistor group including a plurality of transfer transistors PT coupled to the same block selection line BSEL. The plurality of transfer transistors PT may be coupled to a plurality of gate contact plugs GCT, respectively. The plurality of gate contact plugs GCT may be coupled to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL, respectively. Each of the transfer transistors PT may be coupled to a corresponding local line among the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL via the gate contact plug GCT corresponding to the transfer transistor PT.

[0038] In response to a block selection signal applied to a block selection line BSEL, a plurality of transfer transistors PT may transfer a voltage applied to a plurality of global lines GLL to a source selection line SSL, a drain selection line DSL, and a plurality of word lines WL. The plurality of global lines GLL may include a global source selection line GSSL, a global drain selection line GDSL, and a plurality of global word lines GWL corresponding to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL, respectively.

[0039] Figure 3 and Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] refer to Figure 3 and 4, the semiconductor memory devices 50A and 50B may include a cell array structure CAS, a doped semiconductor structure DPS, a transistor TR and a transfer transistor PT of a peripheral circuit structure PS, and an interconnection structure for electrical connection between the peripheral circuit structure PS and the cell array structure CAS.

[0041] The cell array structure CAS may include a plurality of memory cells arranged in a three-dimensional manner. In one embodiment, the plurality of memory cells may be included in a plurality of memory cell strings CS, as described above with reference to Figure 2 Each memory cell string CS may be coupled to a plurality of conductive layers CDL included in a gate stack GST. The plurality of conductive layers CDL may be used as Figure 2 At least one drain select line DSL, a plurality of word lines WL, and at least one source select line SSL illustrated in FIG. Each of the memory cells may be coupled to a conductive layer serving as a word line among the plurality of conductive layers CDL.

[0042] The gate stack GST may be disposed above the semiconductor substrate 61. The semiconductor substrate 61 may include a first surface SU1 facing the first direction DR1. The gate stack GST may further include a plurality of interlayer insulating layers ILD and a plurality of conductive layers CDL alternately stacked in the first direction DR1. Each conductive layer CDL and each interlayer insulating layer ILD may extend in a plane created by the second direction DR2 and the third direction DR3, the plane being parallel to the first surface SU1 and perpendicular to the first direction DR1. The above-mentioned first direction DR1, second direction DR2, and third direction DR3 may correspond to the X-axis, the Y-axis, and the Z-axis, respectively. Hereinafter, the direction facing the second surface SU2 of the semiconductor substrate 61 may be defined as a fourth direction DR4, the fourth direction DR4 being the opposite direction of the first direction DR1, and the second surface SU2 may be defined as a surface on the opposite side of the first surface SU1.

[0043] Each of the plurality of conductive layers CDL may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of each conductive layer CDL may include a doped silicon layer. The metal layer of each conductive layer CDL may include tungsten, copper, molybdenum, etc. The plurality of conductive layers CDL may further include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. Each of the plurality of interlayer insulating layers ILD may include a silicon oxide layer, etc.

[0044] The channel region of each memory cell string CS may be defined by a channel layer CHL, and the data storage region of each memory cell string CS may be defined by a memory layer ML. The memory layer ML and the channel layer CHL may penetrate the gate stack GST. The memory layer ML and the channel layer CHL may be disposed in a channel hole of the gate stack GST. The channel hole may extend in a first direction DR1 to pass through a plurality of conductive layers CDL and a plurality of interlayer insulating layers ILD. The channel layer CHL may be formed of a semiconductor material. In one embodiment, the channel layer CHL may include silicon, germanium, or a mixture thereof.

[0045] The channel layer CHL may include a contact surface CTS contacting the doped semiconductor structure DPS. The doped semiconductor structure DPS may be used as at least one of a source region and a well region. In one embodiment, a doped semiconductor structure DPS may be provided as a source region, the source region including n-type impurities as majority carriers. However, the embodiments of the present disclosure are not limited thereto. In one embodiment, the doped semiconductor structure DPS may include at least one of: a first conductive doped region including n-type impurities as majority carriers, and a second conductive doped region including p-type impurities as majority carriers. The first conductive doped region may be provided as a source region, and the second conductive doped region may be provided as a well region.

[0046] The doped semiconductor structure DPS and the gate stack GST may be disposed to be spaced apart from the semiconductor substrate 61 in the first direction DR1. The position of the doped semiconductor structure DPS and the position of the gate stack GST may be designed in various ways. Figure 3 As shown, the doped semiconductor structure DPS may be disposed farther from the semiconductor substrate 61 in the first direction DR1 than the gate stack GST is from the semiconductor substrate 61. Figure 4 As shown, the doped semiconductor structure DPS may be disposed closer to the semiconductor substrate 61 in the first direction DR1 than the distance between the gate stack GST and the semiconductor substrate 61 .

[0047] refer to Figure 3 , the gate stack GST may be disposed between the doped semiconductor structure DPS and the semiconductor substrate 61. The contact surface CTS of the channel layer CHL may be coplanar with the surface of the doped semiconductor structure DPS. In one embodiment, the doped semiconductor structure DPS may include a trench, the channel layer CHL may be inserted into the trench, and the contact surface CTS of the channel layer CHL may be coplanar with the surface of the trench defined in the doped semiconductor structure DPS.

[0048] The gate stack GST and the doped semiconductor structure DPS may be covered with an upper insulating layer UI. A conductive contact CT coupled to the doped semiconductor structure DPS may be disposed in the upper insulating layer UI. Although not illustrated in the drawings, the conductive contact CT may transmit an electrical signal from a common source line disposed above the upper insulating layer UI to the doped semiconductor structure DPS.

[0049] refer to Figure 4 , the doped semiconductor structure DPS may be disposed between the gate stack GST and the semiconductor substrate 61. The contact surface CTS of the channel layer CHL may be coplanar with the surface of the doped semiconductor structure DPS. In one embodiment, the doped semiconductor structure DPS may include a first semiconductor layer L1, a second semiconductor layer L2, and a third semiconductor layer L3 stacked in a first direction DR1. The channel layer CHL may penetrate the third semiconductor layer L3 and may extend into the first semiconductor layer L1. The second semiconductor layer L2 may include a sidewall coplanar with the contact surface CTS of the channel layer CHL. In other words, the sidewall of the second semiconductor layer L2 may contact the channel layer CHL.

[0050] Each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may include at least one of an n-type impurity and a p-type impurity. In one embodiment, each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may be provided as a first conductive doping region including an n-type impurity as a majority carrier. In another embodiment, each of the second semiconductor layer L2 and the third semiconductor layer L3 may be provided as a first conductive doping region including an n-type impurity as a majority carrier, and the first semiconductor layer L1 may be provided as a second conductive doping region including a p-type impurity as a majority carrier. The first conductive doping region may be provided as a source region, and the second conductive doping region may be provided as a well region. Each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may include a semiconductor material, such as silicon. However, the embodiments of the present disclosure are not limited thereto, and the doping regions of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may be designed in various ways.

[0051] The memory layer ML may be interposed between each of the first semiconductor layer L1 and the third semiconductor layer L3 and the channel layer CHL. The memory layer ML may be separated into the first memory layer ML1 and the second memory layer ML2 by a contact portion between the second semiconductor layer L2 and the channel layer CHL. The first memory layer ML1 may be interposed between the third semiconductor layer L3 and the channel layer CHL, and may extend in the first direction DR1 to be interposed between the gate stack GST and the channel layer CHL. The second memory layer ML2 may be interposed between the channel layer CHL and the first semiconductor layer L1.

[0052] refer to Figure 3 and Figure 4 , the core insulating layer CO and the capping pattern CAP may be disposed in a central region of a channel hole passing through the gate stack GST. The channel layer CHL may extend along a side of the core insulating layer CO and a side of the capping pattern CAP. The capping pattern CAP may serve as a drain junction of the memory cell string CS. The capping pattern CAP may include at least one of an n-type impurity and a p-type impurity. In one embodiment, the capping pattern CAP may include an n-type impurity as a majority carrier.

[0053] Figure 3 The memory layer ML and Figure 4 Each of the first memory layers ML1 illustrated in the figure may include: a blocking insulating layer between the channel layer CHL and the gate stack GST, a data storage layer between the blocking insulating layer and the channel layer CHL, and a tunnel insulating layer between the data storage layer and the channel layer CHL. The blocking insulating layer may include an insulating material capable of blocking charges. The tunnel insulating layer may include an insulating material capable of realizing charge tunneling. The blocking insulating layer may include an insulating layer having a dielectric constant higher than that of the tunnel insulating layer. The data storage layer may be formed of a material layer capable of storing data changed by Fowler-Nordheim tunneling. In one embodiment, the data storage layer may be formed of a charge trapping insulating layer or an insulating layer containing conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. However, the embodiments of the present disclosure are not limited thereto, and the data storage layer may be formed of a material layer capable of storing information based on an operating principle other than Fowler-Nordheim tunneling. In one embodiment, the data storage layer may include a phase change material layer, a ferroelectric layer, etc. In this case, each of the channel layer CHL, the core insulating layer CO, and the capping pattern CAP may be replaced with a pillar electrode structure.

[0054] Figure 4 The second memory layer ML2 illustrated in FIG. 8 may be configured in the same manner as the first memory layer ML1 .

[0055] refer to Figure 3 and Figure 4 The semiconductor memory devices 50A and 50B may further include a bit line BL. The bit line BL may be disposed to be spaced apart from the semiconductor substrate 61 in the first direction DR1. The position of the bit line BL may be designed in various ways. In one embodiment, as shown in FIG. Figure 3 As shown, the bit line BL may be disposed closer to the semiconductor substrate 61 in the first direction DR1 than the distance between the gate stack GST and the semiconductor substrate 61. In other words, the bit line BL may be disposed between the gate stack GST and the semiconductor substrate 61. Figure 4 As shown, the bit line BL may be disposed farther from the semiconductor substrate 61 in the first direction DR1 than the gate stack GST is from the semiconductor substrate 61. In other words, the gate stack GST may be disposed between the bit line BL and the semiconductor substrate 61.

[0056] refer to Figure 3 and Figure 4 , each bit line BL may be coupled to the capping pattern CAP via a bit line connection structure disposed between the gate stack GST and the bit line BL. In one embodiment, the bit line connection structure may include a conductive bit contact plug BCT and a first conductive via structure V1. The conductive bit contact plug BCT may be disposed in a first interlayer insulating structure 89 between the gate stack GST and the bit line BL, and may be coupled to the capping pattern CAP. The first conductive via structure V1 may be disposed in a second interlayer insulating structure 91 between the first interlayer insulating structure 89 and the bit line BL, and may electrically connect the conductive bit contact plug BCT to the bit line BL. The bit line BL may be disposed in a bit line level insulating layer 93. The bit line level insulating layer 93 may overlap the first interlayer insulating structure 89, with the second interlayer insulating structure 91 interposed therebetween.

[0057] The connection between the bit line BL and the capping pattern CAP is not limited to the above-described embodiment. Although not illustrated in the drawings, the bit line BL may be directly coupled to the capping pattern CAP.

[0058] A capping insulating structure CI may be formed between the gate stack GST and the first interlayer insulating layer 89. The channel layer CHL and the capping pattern CAP may extend toward the bit line BL to penetrate a portion of the capping insulating structure CI.

[0059] In one embodiment, the plurality of conductive layers CDL of the gate stack GST may include an end portion forming a step structure. Here, the capping insulating structure CI may cover the step structure. The embodiments of the present disclosure are not limited thereto, and the plurality of conductive layers CDL of the gate stack GST may have substantially the same length in the second direction DR2 without forming a step structure.

[0060] refer to Figure 3 and Figure 4, the semiconductor substrate 61 may include a plurality of active regions 61A separated by an isolation layer 63. Each active region 61A may include a first junction region 61J1 and a second junction region 61J2 provided as a source junction and a drain junction of the transistor TR, respectively, or may include a third junction region 61J3 provided as a source junction of the transfer transistor PT. Each of the first junction region 61J1, the second junction region 61J2, and the third junction region 61J3 may include at least one of an n-type impurity and a p-type impurity. In one embodiment, when each of the transistor TR and the transfer transistor PT is provided as an N-channel metal oxide semiconductor (NMOS) transistor, each of the first junction region 61J1, the second junction region 61J2, and the third junction region 61J3 may include an n-type impurity as a majority carrier.

[0061] The transistor TR may be included in a circuit other than the transfer circuit 40 of the peripheral circuit structure PS and may be distinguished from the transfer transistor PT forming the transfer transistor group. In one embodiment, the transistor TR may be included in the page buffer 37 .

[0062] A gate insulating layer 65 and a gate electrode 66 of the transistor TR may be stacked on the semiconductor substrate 61 disposed between the first junction region 61J1 and the second junction region 61J2 within the active region 61A of the semiconductor substrate 61 .

[0063] The molded insulating structure MIS may be disposed between the semiconductor substrate 61 and the gate stack GST. The molded insulating structure MIS may include a first region AR1 overlapping the transistor TR and a second region AR2 extending laterally (eg, in a second direction DR2) from the first region AR1.

[0064] The plurality of first conductive connection structures 81 may be disposed in the first area AR1 of the molded insulation structure MIS. The plurality of first conductive connection structures 81 may be included in the interconnection structure.

[0065] A transfer gate 79 provided as a gate electrode of the transfer transistor PT may be disposed in the second region AR2 of the molded insulating structure MIS. The transfer gate 79 may be penetrated by the active pillar 70. A transfer gate insulating layer 71 may be disposed between the active pillar 70 and the transfer gate 79.

[0066] The molded insulating structure MIS may include a first insulating layer 67, a second insulating layer 69, and a third insulating layer 83. The first insulating layer 67 may be disposed over the semiconductor substrate 61 to cover the transistor TR. The first insulating layer 67 may extend along the lower surface of the transfer gate 79. The second insulating layer 69 may be disposed over the first insulating layer 67. The second insulating layer 69 may face the side surface of the transfer gate 79. The third insulating layer 83 may be disposed over the second insulating layer 69. The third insulating layer 83 may extend along the upper surface of the transfer gate 79.

[0067] The plurality of first conductive connection structures 81 may include: a first type of first conductive connection structure coupled to the gate electrode 66 of the transistor TR, a second type of first conductive connection structure coupled to the first junction region 61J1 of the transistor TR, and a third type of first conductive connection structure coupled to the second junction region 61J2 of the transistor TR. The plurality of first conductive connection structures 81 may penetrate at least one of the first insulating layer 67, the second insulating layer 69, and the third insulating layer 83 in the first region AR1 of the molded insulating structure MIS. In one embodiment, each of the first conductive connection structures 81 may contact the corresponding gate electrode 66, the first junction region 61J1, or the second junction region 61J2 of the transistor TR, and may extend toward the cell array structure CAS to penetrate the first insulating layer 67 and the second insulating layer 69.

[0068] Figure 5A is a cross-sectional view illustrating a pass transistor group according to one embodiment of the present disclosure, and Figure 5B The diagram is along Figure 5A Line AA' captures a plan view of the pass transistor group.

[0069] refer to Figure 5A and Figure 5B , the transfer transistor group may include corresponding to Figure 3 or Figure 4 The plurality of transfer transistors PT of the plurality of conductive layers CDL illustrated in FIG.

[0070] The channel of each transfer transistor PT of the transfer transistor group may be defined by an active pillar 70. The active pillar 70 may be surrounded by a transfer gate 79. According to this structure, each transfer transistor PT may be formed in a wrap-around gate transistor (SGT) structure. When the transfer transistor PT is formed in an SGT structure, the area occupied by the transfer transistor PT may be reduced, and the on / off characteristics of the transfer transistor PT may be improved.

[0071] The transfer gate 79 may be formed of a conductive material. Due to the first insulating layer 67 of the molded insulating structure MIS, the transfer gate 79 may be spaced apart from the semiconductor substrate 61. The transfer gate 79 may be formed using a process of replacing a portion of the second insulating layer 69 of the molded insulating structure MIS with a conductive material. In order to replace a portion of the second insulating layer 69 with a conductive material, a plurality of slits SI may be formed during the process of manufacturing the semiconductor memory device. A plurality of slits SI may remain in the transfer gate 79 while being spaced apart from each other. Each of the slits SI may be filled with an insulating material or a conductive material.

[0072] In order to use the process of replacing a portion of the second insulating layer 69 with a conductive material, the second insulating material 69 may include a material having an etching selectivity with respect to the first insulating layer 67 and the third insulating layer 83. In one embodiment, each of the first insulating layer 67 and the third insulating layer 83 may include a silicon oxide layer, and the second insulating layer 69 may include a silicon nitride layer.

[0073] The active pillar 70 may penetrate the first insulating layer 67 to contact the semiconductor substrate 61. The active pillar 70 may include a channel layer 73 and a semiconductor capping pattern 77. The channel layer 73 and the semiconductor capping pattern 77 may include a semiconductor material such as silicon or germanium.

[0074] The channel layer 73 may penetrate the first insulating layer 67 to contact the active region 61A of the semiconductor substrate 61. The channel layer 73 may include a horizontal portion 73HP and a vertical portion 73VP. The horizontal portion 73HP may contact the third junction region 61J3 formed in the active region 61A of the semiconductor substrate 61. The vertical portion 73VP may extend from the horizontal portion 73HP in the first direction DR1. The vertical portion 73VP may serve as a channel of the transfer transistor PT. The vertical portion 73VP may be an undoped region or a doped region including at least one of a p-type impurity and an n-type impurity. In one embodiment, the horizontal portion 73HP may be an undoped region or a doped region in the same manner as the vertical portion 73VP. In one embodiment, the horizontal portion 73HP may be a doped region doped with the same conductive impurities as the third junction region 61J3.

[0075] The vertical portion 73VP of the channel layer 73 may be formed into a tubular shape. A semiconductor capping pattern 77 may be disposed in a central region of the tubular shape provided by the vertical portion 73VP. The semiconductor capping pattern 77 may be disposed in an upper portion of the central region of the tubular shape, and a core insulating layer 75 may be disposed in a portion of the central region of the tubular shape below the semiconductor capping pattern 77. The semiconductor capping pattern 77 may be provided as a drain junction of the transfer transistor PT. The semiconductor capping pattern 77 may include the same conductive impurities as the third junction region 61J3.

[0076] The channel length of the transfer transistor PT may be proportional to the length of the vertical portion 73VP of the channel layer 73 in the first direction DR1. The length of the vertical portion 73VP may be proportional to the thickness of the second insulating layer 69 in the first direction DR1. The channel length of the transfer transistor PT may be designed to transmit a higher operating voltage. The channel length of the transfer transistor PT may be increased by controlling the thickness of the second insulating layer 69 in the first direction DR1. That is, since the channel length of the transfer transistor PT may be increased even without increasing the planar area of ​​the semiconductor substrate 61, the planar area of ​​the semiconductor substrate 61 allocated by the transfer transistor PT may be reduced. In order to ensure the channel length of the transfer transistor PT, the second insulating layer 69 may be formed to be thicker in the first direction DR1 than each of the first insulating layer 67 and the third insulating layer 83.

[0077] The transfer gate insulating layer 71 may surround the sidewall of the vertical portion 73VP of the channel layer 73 .

[0078] refer to Figure 3 and Figure 4 , the interconnect structure of the memory device 50A or 50B may further include a plurality of second conductive connection structures 85, a plurality of gate contact plugs GCT, a plurality of second conductive via structures V2, and a plurality of conductive lines CLI.

[0079] A plurality of second conductive connection structures 85 may be disposed in the first intercalated insulating structure IS1. The first intercalated insulating structure IS1 may be disposed between the gate stack GST and the molded insulating structure MIS. The plurality of second conductive connection structures 85 may include: a first type of second conductive connection structure connected to the first conductive connection structure 81, and a second type of second conductive connection structure connected to the active pillar 70. Each of the second conductive connection structures 85 may include a vertical via pattern and a line pattern. The plurality of second conductive connection structures 85 may penetrate the third insulating layer 83 to contact the semiconductor capping pattern (e.g., the first conductive connection structure 81 or the active pillar 70). Figure 5A of 77).

[0080] The plurality of gate contact plugs GCT may be respectively coupled to the plurality of conductive layers CDL of the gate stack GST. The plurality of gate contact plugs GCT may extend into the capping insulating structure CI. The plurality of gate contact plugs GCT may extend to penetrate the first interlayer insulating structure 89.

[0081] A plurality of second conductive via structures V2 may be disposed in the second interlayer insulating structure 91. The plurality of second conductive via structures V2 may be coupled to the plurality of gate contact plugs GCT, respectively.

[0082] A plurality of conductive lines CLI may be disposed in the bit line level insulating layer 93. The respective conductive lines CLI may be coupled to the pass transistors PT corresponding thereto via conductive patterns having various structures.

[0083] In one embodiment, each conductive line CLI may be connected via Figure 3 The corresponding first conductive bonding structure 87 and Figure 3 The corresponding second conductive bonding structure 99 illustrated in FIG. 1 is coupled to the corresponding pass transistor PT.

[0084] refer to Figure 3 , a plurality of first conductive bonding structures 87 may be disposed in the second intercalated insulating structure IS2. The second intercalated insulating structure IS2 may be disposed between the first intercalated insulating structure IS1 and the gate stack GST. The plurality of first conductive bonding structures 87 may include a metal, such as copper. The plurality of first conductive bonding structures 87 may be coupled to the plurality of second conductive connection structures 85, respectively. The plurality of first conductive bonding structures 87 may be coupled to the plurality of second conductive bonding structures 99.

[0085] The plurality of second conductive bonding structures 99 may be disposed in the third interposing insulating structure IS3. The third interposing insulating structure IS3 may be disposed between the second interposing insulating structure IS2 and the gate stack GST. The plurality of second conductive bonding structures 99 may include metal, such as copper.

[0086] The interconnect structure of the semiconductor memory device 50A may further include a plurality of third conductive via structures 97. The plurality of third conductive via structures 97 may be disposed in the fourth interlayer insulating structure 95. The plurality of third conductive via structures 97 may be respectively coupled to the plurality of second conductive bonding structures 99. The plurality of third conductive via structures 97 may include a first type of third conductive via structure coupled to the bit line BL and a second type of third conductive via structure coupled to the conductive line CLI.

[0087] The active pillar 70 of each transfer transistor PT may be arranged to overlap with the corresponding gate contact plug GCT. Therefore, the interconnection structure (e.g., GCT, V2, CLI, and 85) for connection between the transfer transistor PT and the corresponding conductive layer CDL may be simplified. The corresponding gate contact plug GCT may contact the corresponding conductive layer CDL among the plurality of conductive layers CDL, and then may extend toward the second conductive bonding structure 99. The gate contact plug GCT may be electrically connected to the corresponding active pillar 70 via the second conductive via structure V2, the conductive line CLI, the second type of third conductive via structure 97, the second conductive bonding structure 99, the first conductive bonding structure 87, and the second type of second conductive connection structure 85.

[0088] Figure 3The semiconductor memory device 50A illustrated in the figure can be provided by the following process: performing the first structure forming process and the second structure forming process separately, and then combining the first structure to the second structure. The first structure may include a transistor TR, a transfer transistor PT, a first conductive connection structure 81, a second conductive connection structure 85, and a first conductive bonding structure 87. The second structure may include a cell array structure CAS, a gate contact plug GCT, a conductive bit contact plug BCT, a bit line BL, a conductive line CLI, a first conductive via structure V1, a second conductive via structure V2, a third conductive via structure 97, and a second conductive bonding structure 99. The process of combining the first structure to the second structure may include combining the first conductive bonding structure 87 and the second conductive bonding structure 99 with each other. The doped semiconductor structure DPS, the upper insulating layer UI, and the conductive contact portion CT may be formed after the first structure is combined with the second structure.

[0089] In one embodiment, Figure 4 As shown, the gate stack GST may be interposed between the conductive line CLI and the transfer transistor PT. In this case, the conductive line CLI and the second type of second conductive connection structure 85 coupled to the transfer transistor PT may extend to overlap with the peripheral region (not shown) of the semiconductor substrate 61. A via contact plug (not shown) may be provided between a portion of the conductive line CLI and a portion of the second type of second conductive connection structure 85 overlapping with the peripheral region (not shown) of the semiconductor substrate 61. The conductive line CLI may be coupled to the transfer transistor PT via the via contact plug.

[0090] refer to Figure 4 The second interposing insulating structure IS2 may be disposed between the first interposing insulating structure IS1 and the gate stack GST. The doped semiconductor structure DPS may be disposed between the second interposing insulating structure IS2 and the gate stack GST such that the doped semiconductor structure DPS is spaced apart from the second conductive connection structure 85 .

[0091] manufacture Figure 4 The method of the semiconductor memory device 50B illustrated in FIG. 1 may include a process of forming a lower structure including a transistor TR, a transfer transistor PT, a first conductive connection structure 81, and a second conductive connection structure 85. Above the lower structure, a formation may be performed. Figure 4 2 , and a process of doping the semiconductor structure DPS and a process of forming the cell array structure CAS of the semiconductor memory device 50B illustrated in FIG.

[0092] FIG. 6A to FIG. 6K is a cross-sectional view illustrating a method of manufacturing a first conductive connection structure and a transfer transistor group of a semiconductor memory device according to an embodiment of the present disclosure.

[0093] refer to Fig. 6A , a structure including a transistor TR can be formed. In one embodiment, the step of forming the structure may include: a step of forming an isolation layer 103 separating a plurality of active regions 101A in a semiconductor substrate 101, a step of forming a stacked structure of a gate insulating layer 105 and a gate electrode 107 on some of the plurality of active regions 101A, and a step of forming a first junction region 101J1 and a second junction region 101J2 by ​​injecting conductive impurities into the active region 101A around the gate electrode 107.

[0094] Then, a first insulating layer 111 may be formed over the semiconductor substrate 101 to cover the transistor TR. The first insulating layer 111 may include a first region AR1 overlapping the transistor TR and a second region AR2 extending laterally from the first region AR1.

[0095] Thereafter, a second insulating layer 113 may be formed over the first insulating layer 111. The second insulating layer 113 may include a material having an etch selectivity with respect to the first insulating layer 111. In one embodiment, the first insulating layer 111 may include a silicon oxide layer, and the second insulating layer 113 may include a silicon nitride layer.

[0096] The second insulating layer 113 may extend to overlap the first area AR1 and the second area AR2 of the first insulating layer 111 .

[0097] refer to Figure 6B , a plurality of contact holes 115A and active holes 115B may be formed through the first insulating layer 111 and the second insulating layer 113. In one embodiment, the process of forming the plurality of contact holes 115A and the active holes 115B may include: a step of forming a mask pattern (not shown) over the second insulating layer 113, a step of etching the first insulating layer 111 and the second insulating layer 113 through a plurality of openings in the mask pattern, and a step of removing the mask pattern. The plurality of openings in the mask pattern may correspond to the plurality of contact holes 115A and the active holes 115B, respectively.

[0098] The plurality of contact holes 115A may pass through the first region AR1 of the first insulating layer 111 and a portion of the second insulating layer 113 overlapping the first region AR1. The plurality of contact holes 115A may include a first type contact hole for exposing the gate electrode 107 of the transistor TR, a second type contact hole for exposing the first junction region 101J1 of the transistor TR, and a third type contact hole for exposing the second junction region 101J2 of the transistor TR.

[0099] The active hole 115B may pass through the second area AR2 of the first insulating layer 111 and a portion of the second insulating layer 113 overlapping the second area AR2. A first width W1 of the active hole 115B may be formed twice or more than a second width W2 of each contact hole 115A.

[0100] refer to Figure 6C , a preliminary insulating layer 121 may be formed over the second insulating layer 113. The thickness of the preliminary insulating layer 121 may be controlled so that the preliminary insulating layer 121 fills the central area of ​​each contact hole 115A, but the central area of ​​the active hole 115B is open. In one embodiment, the thickness of the preliminary insulating layer 121 may be controlled to be half or more of the second width W2, and may be controlled to be less than half of the first width W1.

[0101] Then, the conductive impurities 117 may be implanted through the central region of the active hole 115B opened by the preliminary insulating layer 121. In this manner, the third junction region 101J3 may be formed in the active region 101A of the semiconductor substrate 101.

[0102] refer to Fig.6D , can be etched Figure 6C The portion of the preliminary insulating layer 121 illustrated in FIG. 1 is removed so that the preliminary insulating layer 121 is separated into a transfer gate insulating layer 121G and a dummy insulating layer 121D. In this case, a portion of the semiconductor substrate 101 overlapping the active hole 115B may be exposed, and the second insulating layer 113 may be exposed.

[0103] The dummy insulating layer 121D may remain in each of the contact holes 115A, and the transfer gate insulating layer 121G may remain on the sidewalls of the active holes 115B. Figure 6C The preliminary insulating layer 121 shown in FIG. 1 may be etched by an etching process such as an etch-back process. Figure 6C The transfer gate insulating layer 121G remaining on the sidewall of the active hole 115B may have a reduced thickness compared to the preliminary insulating layer 121 illustrated in FIG.

[0104] refer to Fig. 6E , in a state in which the dummy insulating layer 121D remains, the active pillar 120 may be formed in the active hole 115B.

[0105] The step of forming the active pillar 120 may include the step of forming a channel layer 123 in the active hole 115B. The channel layer 123 may include silicon, germanium, or a mixture thereof. The channel layer 123 may be spaced apart from the second insulating layer 113 by the transfer gate insulating layer 121G. The channel layer 123 may extend along the transfer gate insulating layer 121G. The channel layer 123 may extend along the surface of the portion of the semiconductor substrate 101 opened by the active hole 115B, and may contact the third junction region 101J3.

[0106] The channel layer 123 may be formed to open a portion of the central region of the active hole 115B. In this case, the step of forming the active pillar 120 may further include the step of forming a core insulating layer 125 and a semiconductor capping pattern 127 in a portion of the central region of the active hole 115B opened by the channel layer 123. Due to the core insulating layer 125, the semiconductor capping pattern 127 may be spaced apart from the third junction region 101J3. The semiconductor capping pattern 127 may include silicon, germanium, or a mixture thereof. The semiconductor capping pattern 127 may be doped with the same conductive impurities 129 as the third junction region 101J3.

[0107] According to the above-described series of processes, the active hole 115B for the active pillar 120 may be formed using the process of forming the contact hole 115A, thereby reducing the number of unit processes required to manufacture a semiconductor device.

[0108] refer to Fig. 6F , a buffer layer 129 may be formed over the second insulating layer 113. The buffer layer 129 may include a plurality of openings OP. Each opening OP may expose a corresponding dummy insulating layer 121D. Figure 6G As shown, by removing the dummy insulating layer 121D exposed through the opening OP, a plurality of contact holes 115A may be opened.

[0109] refer to Figure 6G , the gate electrode 107 , the first junction region 101J1 , and the second junction region 101J2 of the transistor TR may be exposed through the plurality of open contact holes 115A.

[0110] refer to Figure 6H , a plurality of first conductive connection structures 131 may be formed in the plurality of contact holes 115A, respectively.

[0111] In one embodiment, the step of forming a plurality of first conductive connection structures 131 may include: forming a conductive material to fill the plurality of contact holes 115A, and separating the conductive material into the plurality of first conductive connection structures 131. In one embodiment, the step of separating the conductive material into the plurality of first conductive connection structures 131 may include: removing a portion of the conductive material to expose the second insulating layer 113 by a planarization process such as chemical mechanical polishing (CMP). Here, the conductive material may be removed. Figure 6G Buffer layer 129 is shown.

[0112] The process of forming the plurality of first conductive connection structures 131 and the active pillars 120 is not limited to the above series of processes. Figure 6B The process of forming the active hole 115B shown in FIG. Figure 6B The process of forming the contact hole 115A illustrated in FIG. 1 and the process of forming the contact hole 115A may be performed after filling the contact hole with the first conductive connection structure 131. Figure 6B After forming the first conductive connection structure 131, a transfer gate insulating layer 121G and an active pillar 120 may be formed in the active hole. In one embodiment, the active hole 115B may be formed in the active hole 115B. Figure 6B The process of forming the contact hole 115A is performed before Figure 6B The process of forming the active hole 115B shown in FIG. 1 and the formation of the active hole 115B may be performed after forming the transfer gate insulating layer 121G and the active pillar 120 in the active hole. Figure 6B After forming the active pillar 120, a first conductive connection structure 131 may be formed in the contact hole.

[0113] As described above, after the first conductive connection structure 131 and the active pillar 120 are formed in various ways, the third insulating layer 137 may be formed over the second insulating layer 113, such as Figure 6H The third insulating layer 137 may extend to cover the plurality of first conductive connection structures 131 and the active pillars 120. The third insulating layer 137 may be formed of the same material as the first insulating layer 111. In one embodiment, the third insulating layer 137 may include a silicon oxide layer.

[0114] refer to Fig.6I , a slit 141 may be formed passing through the second insulating layer 113 and the third insulating layer 137. The slit 141 may overlap the second area AR2 of the first insulating layer 111.

[0115] refer to Figure 6J, the portion of the second insulating layer 113 exposed by the slit 141 may be selectively removed. In this manner, a gate region 143 may be opened between the first insulating layer 111 and the third insulating layer 137. The gate region 143 may be defined near the active pillar 120 and the transfer gate insulating layer 121G.

[0116] Then, if Figure 6K As shown, gate region 143 may be filled with transfer gate 145 .

[0117] refer to Figure 6K , the transfer gate 145 may be formed by injecting a conductive material through the slit 141. The transfer gate 145 may be formed to surround the active pillar 120 and the transfer gate insulating layer 121G.

[0118] The second insulating layer 113 may remain between the first region AR1 of the first insulating layer 111 and the third insulating layer 137 , and may face a side of the transfer gate 145 .

[0119] The slit 141 may be filled with a conductive material for the transfer gate 145 or filled with an insulating material.

[0120] Through the above-described series of processes, the transfer transistor PT may be formed to include the transfer gate 145 , the active pillar 120 , and the transfer gate insulating layer 121G.

[0121] Next, you can execute the above reference Figure 3 and Figure 4 The subsequent processes of the described second conductive connection structure, unit array structure, etc.

[0122] Figure 7 is a block diagram illustrating an electronic system including a semiconductor memory device according to one embodiment of the present disclosure.

[0123] refer to Figure 7 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200 .

[0124] Based on the interface, the host 1100 may store data in the storage device 1200 or may read data stored in the storage device 1200. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial-ATA (SATA) interface, a parallel-ATA (PATA) interface, a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash storage (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0125] The storage device 1200 may include a memory controller 1210 and a semiconductor memory device 1220. In one embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD) or a universal serial bus (USB) memory.

[0126] The memory controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100 .

[0127] The semiconductor memory device 1220 may include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data under the control of the memory controller 1210.

[0128] The semiconductor memory device 1220 may be a non-volatile memory device. Figure 3 or Figure 4 As described, the semiconductor memory device 1220 may include: a transistor; a cell array structure; a molded insulating structure including a first region and a second region extending laterally from the first region, the first region being arranged between the transistor and the cell array structure and overlapping with the transistor; a transfer gate being arranged in the second region of the molded insulating structure; an active pillar penetrating the transfer gate; and a transfer gate insulating layer being arranged between the active pillar and the transfer gate.

[0129] According to the embodiments of the present disclosure, the area occupied by the pass transistor can be reduced, so that the integration level of the semiconductor memory device can be improved.

Claims

1. A semiconductor memory device, comprising: transistor; a molded insulating structure comprising a first region overlapping the transistor and a second region extending laterally from the first region; a transfer gate disposed in the second region of the molded insulating structure; an active pillar penetrating the transfer gate; a transfer gate insulating layer disposed between the active pillar and the transfer gate; a first conductive connection structure disposed in the first region of the molded insulating structure and coupled to the transistor; as well as A cell array structure includes a plurality of memory cells arranged in a three-dimensional manner above the molded insulating structure.

2. The semiconductor memory device according to claim 1, wherein the molded insulating structure comprises: a first insulating layer covering the transistor and extending along a lower surface of the transfer gate; a second insulating layer disposed over the first insulating layer and adjacent to the transfer gate, wherein a side surface of the second insulating layer contacts a side surface of the transfer gate; as well as A third insulating layer is disposed above the second insulating layer and extends along an upper surface of the transfer gate. 3 . The semiconductor memory device according to claim 2 , wherein the second insulating layer includes a material having an etching selectivity with respect to the first insulating layer and the third insulating layer.

4. The semiconductor memory device according to claim 2, wherein each of the first insulating layer and the third insulating layer comprises a silicon oxide layer, and The second insulating layer includes a silicon nitride layer. 5 . The semiconductor memory device according to claim 2 , wherein the active pillar penetrates the first insulating layer.

6. The semiconductor memory device according to claim 1, further comprising: a semiconductor substrate overlapping the cell array structure, wherein the molded insulating structure is interposed between the semiconductor substrate and the cell array structure, wherein the transistor comprises a first junction region and a second junction region disposed in the semiconductor substrate, and The first conductive connection structure contacts the corresponding first junction region or the corresponding second junction region to extend toward the unit array structure.

7. The semiconductor memory device of claim 6, wherein the active pillar comprises: a channel layer including a horizontal portion in contact with the semiconductor substrate and a tubular vertical portion extending from the horizontal portion toward the cell array structure; as well as A semiconductor capping pattern is disposed in a central region of the tubular vertical portion of the channel layer.

8. The semiconductor memory device according to claim 7, wherein the semiconductor substrate includes a third junction region contacting the horizontal portion of the channel layer, and The third junction region includes the same conductive impurities as the semiconductor capping pattern.

9. The semiconductor memory device according to claim 1, further comprising: A plurality of slits are disposed to be spaced apart from each other in the transfer gate.

10. The semiconductor memory device according to claim 1, wherein the cell array structure comprises: a gate stack comprising a plurality of conductive layers stacked in a first direction over the molded insulating structure and spaced apart from each other; a channel layer penetrating the gate stack; as well as A memory layer is disposed between the channel layer and the gate stack.

11. The semiconductor memory device according to claim 10, further comprising: A first interposed insulating structure disposed between the gate stack and the molded insulating structure; a second conductive connection structure disposed in the first interposed insulating structure and coupled to the active pillar; a second interposed insulating structure disposed between the first interposed insulating structure and the gate stack; a first conductive bonding structure disposed in the second interposed insulating structure and coupled to the second conductive connecting structure; a third interposed insulating structure disposed between the second interposed insulating structure and the gate stack; a second conductive bonding structure disposed in the third interposed insulating structure and bonded to the first conductive bonding structure; as well as A gate contact plug extends from a conductive layer corresponding to the second conductive bonding structure among the plurality of conductive layers toward the second conductive bonding structure.

12. The semiconductor memory device according to claim 10, further comprising: A first interposed insulating structure disposed between the gate stack and the molded insulating structure; a second conductive connection structure disposed in the first interposed insulating structure and coupled to the active pillar; a second interposed insulating structure disposed between the first interposed insulating structure and the gate stack; a doped semiconductor structure disposed between the second intervening insulating structure and the gate stack and connected to the channel layer; as well as A plurality of gate contact plugs are respectively coupled to the plurality of conductive layers and extend in the first direction.

13. A semiconductor memory device comprising: a semiconductor substrate comprising a first surface facing a first direction and a second surface facing a direction opposite to the first direction; a gate stack comprising a plurality of conductive layers stacked in the first direction over the first surface of the semiconductor substrate; a molded insulating structure disposed between the gate stack and the semiconductor substrate and comprising a first region and a second region extending laterally from the first region; a first conductive connection structure disposed in the first region of the molded insulating structure and extending to contact the semiconductor substrate; a transfer gate disposed in the second region of the molded insulating structure; an active pillar penetrating the transfer gate; as well as A transfer gate insulating layer is disposed between the active pillar and the transfer gate.

14. The semiconductor memory device according to claim 13, further comprising: an interposed insulating structure disposed between the molded insulating structure and the gate stack; as well as A second conductive connection structure is disposed in the interposed insulating structure and is coupled to the active pillar and the first conductive connection structure, respectively.

15. The semiconductor memory device according to claim 13, wherein the molded insulating structure comprises: a first insulating layer disposed above the semiconductor substrate and extending along a lower surface of the transfer gate; a second insulating layer disposed over the first insulating layer and adjacent to the transfer gate, wherein a side surface of the second insulating layer contacts a side surface of the transfer gate; as well as A third insulating layer is disposed above the second insulating layer and extends along an upper surface of the transfer gate.

16. The semiconductor memory device according to claim 15, wherein the second insulating layer includes a material having an etching selectivity with respect to the first insulating layer and the third insulating layer. 17 . The semiconductor memory device according to claim 15 , wherein the first insulating layer is penetrated by the first conductive connection structure and the active pillar.

18. The semiconductor memory device according to claim 13, further comprising: A plurality of slits are disposed to be spaced apart from each other in the transfer gate.

19. The semiconductor memory device according to claim 14, further comprising: a channel layer penetrating the gate stack; a memory layer disposed between the channel layer and the gate stack; a gate contact plug disposed between the gate stack and the molded insulating structure and coupled to a corresponding conductive layer among the plurality of conductive layers; a first conductive bonding structure coupled to a second conductive connection structure corresponding to the gate contact plug among the second conductive connection structures; as well as A second conductive bonding structure is coupled to the gate contact plug and bonded to the first conductive bonding structure.

20. The semiconductor memory device according to claim 13, further comprising: a channel layer penetrating the gate stack; a memory layer disposed between the channel layer and the gate stack; a doped semiconductor structure disposed between the gate stack and the molded insulating structure and coupled to the channel layer; as well as A plurality of gate contact plugs are respectively coupled to the plurality of conductive layers and extend in the first direction.

21. A method of manufacturing a semiconductor memory device, comprising: forming a first insulating layer, the first insulating layer comprising a first region covering the transistor and a second region extending laterally from the first region; forming a second insulating layer over the first insulating layer; Etching the first insulating layer and the second insulating layer to form a contact hole and an active hole, wherein the contact hole passes through portions of the first insulating layer and the second insulating layer overlapping the first region of the first insulating layer, and wherein the active hole passes through portions of the first insulating layer and the second insulating layer overlapping the second region of the first insulating layer; forming a transfer gate insulating layer and an active pillar in the active hole; forming a first conductive connection structure in the contact hole; forming a third insulating layer over the second insulating layer to cover the first conductive connection structure and the active pillar; forming a slit passing through the second insulating layer and the third insulating layer; as well as A portion of the second insulating layer is replaced with a transfer gate via the slit.

22. The method according to claim 21, wherein the first insulating layer is formed above the semiconductor substrate, The transistor comprises: a first junction region and a second junction region, wherein the first junction region and the second junction region are disposed in the semiconductor substrate; as well as a gate insulating layer and a gate electrode, the gate insulating layer and the gate electrode being stacked above the semiconductor substrate between the first junction region and the second junction region, and The contact hole is formed to expose the corresponding first junction region, second junction region or gate electrode.

23. The method according to claim 22, further comprising: forming a third junction region by implanting conductive impurities into a partial region of the semiconductor substrate through the active hole, Wherein the active pillar is coupled to the third junction region.

24. The method according to claim 21, wherein forming the transfer gate insulating layer and the active pillar comprises: forming a preliminary insulating layer to open the central area of ​​the active hole and fill the central area of ​​the contact hole; etching a portion of the preliminary insulating layer so that the preliminary insulating layer is separated into the transfer gate insulating layer and a dummy insulating layer in the contact hole; In a state where the dummy insulating layer remains, forming a channel layer in the active hole; forming a core insulating layer and a semiconductor capping pattern in a portion of the central region of the active hole opened by the channel layer; implanting conductive impurities into the semiconductor capping pattern; as well as The dummy insulating layer is removed so that the contact hole is opened.

25. The method according to claim 21, wherein the slit overlaps the second region of the first insulating layer, wherein the transfer gate is formed to surround the active pillar, and The second insulating layer remains between the first region of the first insulating layer and the third insulating layer to be adjacent to a portion of the transfer gate, wherein a side surface of the second insulating layer contacts a side surface of the transfer gate. 26 . The method according to claim 21 , wherein the second insulating layer comprises a material having an etching selectivity with respect to the first insulating layer and the third insulating layer.

27. The method according to claim 21, wherein each of the first insulating layer and the third insulating layer comprises a silicon oxide layer, and The second insulating layer includes a silicon nitride layer.

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